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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h6
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h14
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h1
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h3
5 files changed, 21 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3a59abb10e..862ec2e2f1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -409,6 +409,12 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
/* RGMIIPCR bit definitions*/
#define SCFG_RGMIIPCR_EN_AUTO BIT(3)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 234440b5fe..35719d747b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
#define SVR_LS1043A_P23 0x879202
#define SVR_LS1023A_P23 0x87920A
+#define SVR_LS1017A 0x870B24
+#define SVR_LS1018A 0x870B20
+#define SVR_LS1027A 0x870B04
#define SVR_LS1028A 0x870B00
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
@@ -100,9 +103,9 @@ enum boot_src get_boot_src(void);
#define SVR_LS2044A 0x870930
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
-#define SVR_LX2160A 0x873601
-#define SVR_LX2120A 0x873621
-#define SVR_LX2080A 0x873603
+#define SVR_LX2160A 0x873600
+#define SVR_LX2120A 0x873620
+#define SVR_LX2080A 0x873602
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
@@ -112,6 +115,9 @@ enum boot_src get_boot_src(void);
#ifdef CONFIG_ARCH_LX2160A
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
#endif
+#ifdef CONFIG_ARCH_LS1028A
+#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
+#endif
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
#define SVR_DEV(svr) ((svr) >> 8)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 137cd61804..f2ba182346 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -155,7 +155,7 @@ struct ccsr_gur {
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
-#define SCFG_QSPI_CLKSEL 0xc0100000
+#define SCFG_QSPI_CLKSEL 0x50100000
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index 0a1da02376..49a8a66f7b 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,6 +315,7 @@ struct dram_para {
u8 cols;
u8 rows;
u8 ranks;
+ u8 bus_full_width;
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..a646ea6a3c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
+#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
+#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
+
#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])