diff options
Diffstat (limited to 'arch/arm/include/asm')
23 files changed, 292 insertions, 605 deletions
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index af7f3bff57..92b1c5e2d6 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Broadcom Corporation. + * Copyright 2014-2017 Broadcom. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,10 +23,6 @@ #define CONFIG_SYS_NS16550_COM3 0x18023000 /* Ethernet */ -#define CONFIG_BCM_SF2_ETH -#define CONFIG_BCM_SF2_ETH_GMAC - -#define CONFIG_PHYLIB #define CONFIG_PHY_BROADCOM #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f60a..4afc338b8e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,6 +35,7 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index fd3f851b53..88f40c0897 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -13,7 +13,7 @@ * uint64_t entry_addr; * uint64_t status; * uint64_t lpid; -* uint64_t os_arch; +* uint64_t arch_comp; * }; * we pad this struct to 64 bytes so each entry is in its own cacheline * the actual spin table is an array of these structures @@ -21,10 +21,16 @@ #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 #define SPIN_TABLE_ELEM_STATUS_IDX 1 #define SPIN_TABLE_ELEM_LPID_IDX 2 -#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 +/* compare os arch and cpu arch */ +#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ #define SPIN_TABLE_ELEM_SIZE 64 +/* os arch is same as cpu arch */ +#define OS_ARCH_SAME 0 +/* os arch is different from cpu arch */ +#define OS_ARCH_DIFF 1 + #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ extern u64 __spin_table[]; @@ -43,7 +49,4 @@ int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif -#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_ARM64 22 /* ARM64 */ - #endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 497afe7b15..aeb12739aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -65,8 +65,8 @@ struct cpu_type { #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870919 -#define SVR_LS2041A 0x870915 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 #define SVR_DEV_LS2080A 0x8701 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 0c99bbdc93..dbe340d23e 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -236,8 +236,21 @@ #define VDD_MPU_ES2_HIGH 1250 #define VDD_MM_ES2_OD 1120 -#define VDD_MPU_ES2_LOW 880 -#define VDD_MM_ES2_LOW 880 +/* Efuse register offsets for OMAP5 platform */ +#define OMAP5_ES2_EFUSE_BASE 0x4A002000 +#define OMAP5_ES2_PROD_REGBITS 16 + +/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ +#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) + +/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ +#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) +/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ +#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ +#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ +#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ #define VDD_MPU_DRA7_NOM 1150 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2f005dd3ad..b047f0d650 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -224,8 +224,8 @@ struct s32ktimer { #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) /* ABB efuse masks */ -#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) -#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) +#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 7346876dc2..72d264bcbe 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -1,3 +1,4 @@ + /* * Copyright 2017 Theobroma Systems Design und Consulting GmbH * @@ -13,7 +14,17 @@ */ #ifdef CONFIG_SPL_BUILD - .space 0x4 /* space for the 'RK33' */ + /* + * We need to add 4 bytes of space for the 'RK33' at the + * beginning of the executable. However, as we want to keep + * this generic and make it applicable to builds that are like + * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no + * TPL, but extra space needed in the SPL), we simply repeat + * the 'b reset' with the expectation that the first one will + * be overwritten, if this is the first stage contained in the + * final image created with mkimage)... + */ + b reset /* may be overwritten --- should be 'nop' or a 'b reset' */ #endif b reset diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index cb0a935edc..c7e21bd605 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -85,7 +85,7 @@ enum { EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 4910ee7387..2b1197fd46 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -51,8 +51,6 @@ check_member(rk3368_cru, emmc_con[1], 0x41c); struct rk3368_clk_priv { struct rk3368_cru *cru; - ulong rate; - bool has_bwadj; }; enum { @@ -91,19 +89,26 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL43_CON */ + GMAC_MUX_SEL_EXTCLK = BIT(8), + /* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT = 8, MMC_PLL_SEL_MASK = GENMASK(9, 8), - MMC_PLL_SEL_CPLL = 0, - MMC_PLL_SEL_GPLL, - MMC_PLL_SEL_USBPHY_480M, - MMC_PLL_SEL_24M, + MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), MMC_CLK_DIV_SHIFT = 0, MMC_CLK_DIV_MASK = GENMASK(6, 0), /* SOFTRST1_CON */ MCU_PO_SRST_MASK = BIT(13), MCU_SYS_SRST_MASK = BIT(12), + DMA1_SRST_REQ = BIT(2), + + /* SOFTRST4_CON */ + DMA2_SRST_REQ = BIT(0), /* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index cf830d04ea..033f067122 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -12,12 +12,10 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { struct rk3399_cru *cru; - ulong rate; }; struct rk3399_pmuclk_priv { struct rk3399_pmucru *pmucru; - ulong rate; }; struct rk3399_pmucru { diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file mode 100644 index 0000000000..4e2b2337f2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; + u32 reserved5[45]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3368_ddr_pctl, iptr, 0x03fc); + +struct rk3368_ddrphy { + u32 reg[0x100]; +}; +check_member(rk3368_ddrphy, reg[0xff], 0x03fc); + +struct rk3368_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3368_msch, devtodev, 0x003c); + +/* GRF_SOC_CON0 */ +enum { + NOC_RSP_ERR_STALL = BIT(9), + MOBILE_DDR_SEL = BIT(4), + DDR0_16BIT_EN = BIT(3), + MSCH0_MAINDDR3_DDR3 = BIT(2), + MSCH0_MAINPARTIALPOP = BIT(1), + UPCTL_C_ACTIVE = BIT(0), +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 93c4e7d4e1..6b6651acab 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -1,4 +1,6 @@ -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ @@ -74,8 +76,11 @@ struct rk3368_grf { u32 soc_con15; u32 soc_con16; u32 soc_con17; + u32 reserved5[0x6e]; + u32 ddrc0_con0; }; check_member(rk3368_grf, soc_con17, 0x444); +check_member(rk3368_grf, ddrc0_con0, 0x600); struct rk3368_pmu_grf { u32 gpio0a_iomux; @@ -92,323 +97,11 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; - u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 reserved[0x72]; u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, os_reg[3], 0x20c); - -/*GRF_GPIO0C_IOMUX*/ -enum { - GPIO0C7_SHIFT = 14, - GPIO0C7_MASK = 3 << GPIO0C7_SHIFT, - GPIO0C7_GPIO = 0, - GPIO0C7_LCDC_D19, - GPIO0C7_TRACE_D9, - GPIO0C7_UART1_RTSN, - - GPIO0C6_SHIFT = 12, - GPIO0C6_MASK = 3 << GPIO0C6_SHIFT, - GPIO0C6_GPIO = 0, - GPIO0C6_LCDC_D18, - GPIO0C6_TRACE_D8, - GPIO0C6_UART1_CTSN, - - GPIO0C5_SHIFT = 10, - GPIO0C5_MASK = 3 << GPIO0C5_SHIFT, - GPIO0C5_GPIO = 0, - GPIO0C5_LCDC_D17, - GPIO0C5_TRACE_D7, - GPIO0C5_UART1_SOUT, - - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_LCDC_D16, - GPIO0C4_TRACE_D6, - GPIO0C4_UART1_SIN, - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 3 << GPIO0C3_SHIFT, - GPIO0C3_GPIO = 0, - GPIO0C3_LCDC_D15, - GPIO0C3_TRACE_D5, - GPIO0C3_MCU_JTAG_TDO, - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 3 << GPIO0C2_SHIFT, - GPIO0C2_GPIO = 0, - GPIO0C2_LCDC_D14, - GPIO0C2_TRACE_D4, - GPIO0C2_MCU_JTAG_TDI, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_LCDC_D13, - GPIO0C1_TRACE_D3, - GPIO0C1_MCU_JTAG_TRTSN, - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 3 << GPIO0C0_SHIFT, - GPIO0C0_GPIO = 0, - GPIO0C0_LCDC_D12, - GPIO0C0_TRACE_D2, - GPIO0C0_MCU_JTAG_TDO, -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = 3 << GPIO0D7_SHIFT, - GPIO0D7_GPIO = 0, - GPIO0D7_LCDC_DCLK, - GPIO0D7_TRACE_CTL, - GPIO0D7_PMU_DEBUG5, - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_LCDC_DEN, - GPIO0D6_TRACE_CLK, - GPIO0D6_PMU_DEBUG4, - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = 3 << GPIO0D5_SHIFT, - GPIO0D5_GPIO = 0, - GPIO0D5_LCDC_VSYNC, - GPIO0D5_TRACE_D15, - GPIO0D5_PMU_DEBUG3, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_LCDC_HSYNC, - GPIO0D4_TRACE_D14, - GPIO0D4_PMU_DEBUG2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_LCDC_D23, - GPIO0D3_TRACE_D13, - GPIO0D3_UART4_SIN, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_LCDC_D22, - GPIO0D2_TRACE_D12, - GPIO0D2_UART4_SOUT, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 3 << GPIO0D1_SHIFT, - GPIO0D1_GPIO = 0, - GPIO0D1_LCDC_D21, - GPIO0D1_TRACE_D11, - GPIO0D1_UART4_RTSN, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, - GPIO0D0_GPIO = 0, - GPIO0D0_LCDC_D20, - GPIO0D0_TRACE_D10, - GPIO0D0_UART4_CTSN, -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_D2, - GPIO2A7_JTAG_TCK, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_SDMMC0_D1, - GPIO2A6_UART2_SIN, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_SDMMC0_D0, - GPIO2A5_UART2_SOUT, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_DQS, - GPIO2A4_EMMC_CLKO, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_CSN3, - GPIO2A3_EMMC_RSTNO, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_CSN2, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_CSN1, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_CSN0, -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = 3 << GPIO2D7_SHIFT, - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO0_D3, - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO0_D2, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 3 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO0_D1, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 3 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_SDIO0_D0, - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = 3 << GPIO2D3_SHIFT, - GPIO2D3_GPIO = 0, - GPIO2D3_UART0_RTS0, - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, - GPIO2D2_GPIO = 0, - GPIO2D2_UART0_CTS0, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3 << GPIO2D0_SHIFT, - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN, -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 3 << GPIO3C7_SHIFT, - GPIO3C7_GPIO = 0, - GPIO3C7_EDPHDMI_CECINOUT, - GPIO3C7_ISP_FLASHTRIGIN, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_MAC_CLK, - GPIO3C6_ISP_SHUTTERTRIG, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_MAC_RXER, - GPIO3C5_ISP_PRELIGHTTRIG, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 3 << GPIO3C4_SHIFT, - GPIO3C4_GPIO = 0, - GPIO3C4_MAC_RXDV, - GPIO3C4_ISP_FLASHTRIGOUT, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, - GPIO3C3_GPIO = 0, - GPIO3C3_MAC_RXDV, - GPIO3C3_EMMC_RSTNO, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, - GPIO3C2_MAC_MDC = 0, - GPIO3C2_ISP_SHUTTEREN, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, - GPIO3C1_GPIO = 0, - GPIO3C1_MAC_RXD2, - GPIO3C1_UART3_RTSN, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3 << GPIO3C0_SHIFT, - GPIO3C0_GPIO = 0, - GPIO3C0_MAC_RXD1, - GPIO3C0_UART3_CTSN, - GPIO3C0_GPS_RFCLK, -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { - GPIO3D7_SHIFT = 14, - GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, - GPIO3D7_GPIO = 0, - GPIO3D7_SC_VCC18V, - GPIO3D7_I2C2_SDA, - GPIO3D7_GPUJTAG_TCK, - - GPIO3D6_SHIFT = 12, - GPIO3D6_MASK = 3 << GPIO3D6_SHIFT, - GPIO3D6_GPIO = 0, - GPIO3D6_IR_TX, - GPIO3D6_UART3_SOUT, - GPIO3D6_PWM3, - - GPIO3D5_SHIFT = 10, - GPIO3D5_MASK = 3 << GPIO3D5_SHIFT, - GPIO3D5_GPIO = 0, - GPIO3D5_IR_RX, - GPIO3D5_UART3_SIN, - - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = 3 << GPIO3D4_SHIFT, - GPIO3D4_GPIO = 0, - GPIO3D4_MAC_TXCLKOUT, - GPIO3D4_SPI1_CSN1, - - GPIO3D3_SHIFT = 6, - GPIO3D3_MASK = 3 << GPIO3D3_SHIFT, - GPIO3D3_GPIO = 0, - GPIO3D3_HDMII2C_SCL, - GPIO3D3_I2C5_SCL, - - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, - GPIO3D2_GPIO = 0, - GPIO3D2_HDMII2C_SDA, - GPIO3D2_I2C5_SDA, - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = 3 << GPIO3D1_SHIFT, - GPIO3D1_GPIO = 0, - GPIO3D1_MAC_RXCLKIN, - GPIO3D1_I2C4_SCL, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 3 << GPIO3D0_SHIFT, - GPIO3D0_GPIO = 0, - GPIO3D0_MAC_MDIO, - GPIO3D0_I2C4_SDA, -}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[0], 0x200); /*GRF_SOC_CON11/12/13*/ enum { @@ -439,4 +132,5 @@ enum { MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), }; + #endif diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h index 08ff94591c..b1d8047691 100644 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -25,9 +25,11 @@ check_member(rk3288_pwm, ctrl, 0xc); #define PWM_DUTY_POSTIVE (1 << 3) #define PWM_DUTY_NEGATIVE (0 << 3) +#define PWM_DUTY_MASK (1 << 3) #define PWM_INACTIVE_POSTIVE (1 << 4) #define PWM_INACTIVE_NEGATIVE (0 << 4) +#define PWM_INACTIVE_MASK (1 << 4) #define PWM_OUTPUT_LEFT (0 << 5) #define PWM_OUTPUT_CENTER (1 << 5) diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index 1d044bbda5..c23c5093b7 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -8,12 +8,12 @@ #define __ASM_ARCH_TIMER_H struct rk_timer { - unsigned int timer_load_count0; - unsigned int timer_load_count1; - unsigned int timer_curr_value0; - unsigned int timer_curr_value1; - unsigned int timer_ctrl_reg; - unsigned int timer_int_status; + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; }; void rockchip_timer_init(void); diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h deleted file mode 100644 index 8e8712fecc..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - -enum stm32_gpio_icnf { - STM32_GPIO_ICNF_AN = 0, - STM32_GPIO_ICNF_IN_FLT, - STM32_GPIO_ICNF_IN_PUD, - STM32_GPIO_ICNF_RSVD -}; - -enum stm32_gpio_ocnf { - STM32_GPIO_OCNF_GP_PP = 0, - STM32_GPIO_OCNF_GP_OD, - STM32_GPIO_OCNF_AF_PP, - STM32_GPIO_OCNF_AF_OD -}; - -enum stm32_gpio_pupd { - STM32_GPIO_PUPD_DOWN = 0, - STM32_GPIO_PUPD_UP, -}; - -enum stm32_gpio_mode { - STM32_GPIO_MODE_IN = 0, - STM32_GPIO_MODE_OUT_10M, - STM32_GPIO_MODE_OUT_2M, - STM32_GPIO_MODE_OUT_50M -}; - -enum stm32_gpio_af { - STM32_GPIO_AF0 = 0, - STM32_GPIO_AF1, - STM32_GPIO_AF2, - STM32_GPIO_AF3, - STM32_GPIO_AF4, - STM32_GPIO_AF5, - STM32_GPIO_AF6, - STM32_GPIO_AF7, - STM32_GPIO_AF8, - STM32_GPIO_AF9, - STM32_GPIO_AF10, - STM32_GPIO_AF11, - STM32_GPIO_AF12, - STM32_GPIO_AF13, - STM32_GPIO_AF14, - STM32_GPIO_AF15 -}; - -struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; -}; - -struct stm32_gpio_ctl { - enum stm32_gpio_icnf icnf; - enum stm32_gpio_ocnf ocnf; - enum stm32_gpio_mode mode; - enum stm32_gpio_pupd pupd; - enum stm32_gpio_af af; -}; - -static inline unsigned stm32_gpio_to_port(unsigned gpio) -{ - return gpio / 16; -} - -static inline unsigned stm32_gpio_to_pin(unsigned gpio) -{ - return gpio % 16; -} - -int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, - const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h deleted file mode 100644 index 1af73c5428..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_STM32_H_ -#define _MACH_STM32_H_ - -/* - * Peripheral memory map - */ -#define STM32_PERIPH_BASE 0x40000000 -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000) - -#define STM32_BUS_MASK 0xFFFF0000 - -#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) -#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) -#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) -#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) -#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) - -/* - * Register maps - */ -struct stm32_des_regs { - u16 flash_size; - u16 pad1; - u32 pad2; - u32 uid0; - u32 uid1; - u32 uid2; -}; - -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 ahbenr; /* RCC AHB peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ -}; - -struct stm32_pwr_regs { - u32 cr; - u32 csr; -}; - -struct stm32_flash_regs { - u32 acr; - u32 keyr; - u32 optkeyr; - u32 sr; - u32 cr; - u32 ar; - u32 rsvd1; /* Reserved */ - u32 obr; - u32 wrpr; - u32 rsvd2[8]; /* Reserved */ - u32 keyr2; - u32 rsvd3; - u32 sr2; - u32 cr2; - u32 ar2; -}; - -/* Per bank register set for XL devices */ -struct stm32_flash_bank_regs { - u32 keyr; - u32 rsvd; /* Reserved */ - u32 sr; - u32 cr; - u32 ar; -}; - -/* - * Registers access macros - */ -#define STM32_DES_BASE (0x1ffff7e0) -#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE) - -#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000) -#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) - -#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) -#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) - -#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000) -#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) - -#define STM32_FLASH_SR_BSY (1 << 0) - -#define STM32_FLASH_CR_PG (1 << 0) -#define STM32_FLASH_CR_PER (1 << 1) -#define STM32_FLASH_CR_STRT (1 << 6) -#define STM32_FLASH_CR_LOCK (1 << 7) - -enum clock { - CLOCK_CORE, - CLOCK_AHB, - CLOCK_APB1, - CLOCK_APB2 -}; - -int configure_clocks(void); -unsigned long clock_get(enum clock clck); - -#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index f62b2a4378..92180db321 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -266,7 +266,7 @@ void clock_ll_start_uart(enum periph_id periph_id); * @param node Node to look at * @return peripheral ID, or PERIPH_ID_NONE if none */ -enum periph_id clock_decode_periph_id(const void *blob, int node); +int clock_decode_periph_id(struct udevice *dev); /** * Checks if the oscillator bypass is enabled (XOBP bit) diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3c09..3b9711d28e 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -97,6 +97,11 @@ enum { TEGRA_SOC_UNKNOWN = -1, }; +/* Tegra system controller (SYSCON) devices */ +enum { + TEGRA_SYSCON_PMC, +}; + #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL NV_PA_PMC_BASE #endif diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h index b4b4c8ba4d..deccdf455d 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -15,7 +15,7 @@ struct tegra_xusb_phy; */ struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); -void tegra_xusb_padctl_init(const void *fdt); +void tegra_xusb_padctl_init(void); int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index cf187f3111..cab29ba036 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -48,18 +48,9 @@ struct crlapb_regs { #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 -#define ZYNQMP_IOU_SCNTR 0xFF250000 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 -struct iou_scntr { - u32 counter_control_register; - u32 reserved0[7]; - u32 base_frequency_id_register; -}; - -#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) - struct iou_scntr_secure { u32 counter_control_register; u32 reserved0[7]; @@ -153,4 +144,7 @@ struct pmu_regs { #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) +#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 +#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index d91d98a119..e52abd71a5 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -10,6 +10,25 @@ #define PAYLOAD_ARG_CNT 5 +#define ZYNQMP_CSU_SILICON_VER_MASK 0xF + +enum { + IDCODE, + VERSION, +}; + +enum { + ZYNQMP_SILICON_V1, + ZYNQMP_SILICON_V2, + ZYNQMP_SILICON_V3, + ZYNQMP_SILICON_V4, +}; + +enum { + TCM_LOCK, + TCM_SPLIT, +}; + int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); @@ -24,4 +43,8 @@ int zynqmp_mmio_read(const u32 address, u32 *value); int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); +void initialize_tcm(bool mode); + +int chip_id(unsigned char id); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index 5a53e403a6..9dbb2c4c66 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -19,11 +19,7 @@ enum usbhs_omap_port_mode { OMAP_EHCI_PORT_MODE_HSIC, }; -#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#else #define OMAP_HS_USB_PORTS 3 -#endif #define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) #define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 0e674704ab..df45511699 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, BOOT_DEVICE_NONE }; #endif |