summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-am33xx/mmc_host_def.h4
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_dra7xx.h3
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h3
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h1
-rw-r--r--arch/arm/include/asm/emif.h50
-rw-r--r--arch/arm/include/asm/omap_common.h15
-rw-r--r--arch/arm/include/asm/omap_mmc.h19
-rw-r--r--arch/arm/include/asm/ti-common/ti-edma3.h2
10 files changed, 96 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 724e252946..5a2ea8faef 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -21,8 +21,8 @@
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x48060100
-#define OMAP_HSMMC2_BASE 0x481D8100
+#define OMAP_HSMMC1_BASE 0x48060000
+#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -31,8 +31,8 @@
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -31,8 +31,8 @@
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x4809C100
-#define OMAP_HSMMC2_BASE 0x480B4100
-#define OMAP_HSMMC3_BASE 0x480AD100
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
index 55f49c7848..dc2eb608e2 100644
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -351,4 +351,7 @@
#define NMIN_DSP 0x460
#define RSTOUTN 0x464
+#define MCAN_SEL_ALT_MASK 0x6000
+#define MCAN_SEL 0x2000
+
#endif /* _MUX_DRA7XX_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 81feac704a..f8e7f06442 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -66,6 +66,9 @@
#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
+#define DRA762_ABZ_PACKAGE 0x2
+#define DRA762_ACD_PACKAGE 0x3
+
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index ab0e7fae9c..a6b3557b50 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -62,6 +62,7 @@ u32 omap_sdram_size(void);
u32 cortex_rev(void);
void save_omap_boot_params(void);
void init_omap_revision(void);
+void init_package_revision(void);
void do_io_settings(void);
void sri2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 9a46340deb..dc398efd32 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -17,7 +17,9 @@
#include <asm/io.h>
/* Base address */
+#ifndef EMIF1_BASE
#define EMIF1_BASE 0x4c000000
+#endif
#define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4
@@ -604,6 +606,34 @@
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
+/* EMIF ECC CTRL reg */
+#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31
+#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30)
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29)
+#define EMIF_ECC_REG_RMW_EN_SHIFT 28
+#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0)
+
+/* EMIF ECC ADDRESS RANGE */
+#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16
+#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16)
+#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0
+#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0)
+
+/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5)
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4)
+#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3
+#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3)
+
/* Reg mapping structure */
struct emif_reg_struct {
u32 emif_mod_id_rev;
@@ -664,12 +694,27 @@ struct emif_reg_struct {
u32 emif_prio_class_serv_map;
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
- u32 padding8[5];
+ u32 padding8;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
+ u32 padding8_1;
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
+ u32 padding9[2];
+ u32 emif_1b_ecc_err_cnt;
+ u32 emif_1b_ecc_err_thrush;
+ u32 emif_1b_ecc_err_dist_1;
+ u32 emif_1b_ecc_err_addr_log;
+ u32 emif_2b_ecc_err_addr_log;
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[19];
+#else
u32 padding9[6];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
+#endif
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -1190,6 +1235,9 @@ struct emif_regs {
u32 emif_connect_id_serv_1_map;
u32 emif_connect_id_serv_2_map;
u32 emif_cos_config;
+ u32 emif_ecc_ctrl_reg;
+ u32 emif_ecc_address_range_1;
+ u32 emif_ecc_address_range_2;
};
struct lpddr2_mr_regs {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 481e9389c4..5710136e88 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -597,6 +597,7 @@ extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
extern struct dplls dra7xx_dplls;
extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
@@ -743,6 +744,18 @@ static inline u8 is_dra76x(void)
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA76X;
}
+
+static inline u8 is_dra76x_abz(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 3;
+}
#endif
/*
@@ -778,6 +791,8 @@ static inline u8 is_dra76x(void)
#define DRA722_ES2_0 0x07220200
#define DRA722_ES2_1 0x07220210
+#define DRA762_ABZ_ES1_0 0x07620102
+#define DRA762_ACD_ES1_0 0x07620103
/*
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index fd33408622..bf9de9b211 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -28,6 +28,12 @@
#include <mmc.h>
struct hsmmc {
+#ifndef CONFIG_OMAP34XX
+ unsigned int hl_rev;
+ unsigned int hl_hwinfo;
+ unsigned int hl_sysconfig;
+ unsigned char res0[0xf4];
+#endif
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
@@ -49,6 +55,9 @@ struct hsmmc {
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
+ unsigned char res5[0x10];
+ unsigned int admaes; /* 0x154 */
+ unsigned int admasal; /* 0x158 */
};
struct omap_hsmmc_plat {
@@ -61,6 +70,7 @@ struct omap_hsmmc_plat {
/*
* OMAP HS MMC Bit definitions
*/
+#define MADMA_EN (0x1 << 0)
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
@@ -77,12 +87,12 @@ struct omap_hsmmc_plat {
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
+#define DMA_MASTER (0x1 << 20)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
+#define DE_ENABLE (0x1 << 0)
#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
+#define ACEN_ENABLE (0x1 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
@@ -116,13 +126,13 @@ struct omap_hsmmc_plat {
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
+#define DMA_SELECT (0x2 << 3)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
@@ -145,6 +155,7 @@ struct omap_hsmmc_plat {
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
+#define IE_ADMAE (0x01 << 25)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
index 6a7a321c1b..3f41d34a7a 100644
--- a/arch/arm/include/asm/ti-common/ti-edma3.h
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -119,5 +119,7 @@ void edma3_set_transfer_params(u32 base, int slot, int acnt,
enum edma3_sync_dimension sync_mode);
void edma3_transfer(unsigned long edma3_base_addr, unsigned int
edma_slot_num, void *dst, void *src, size_t len);
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+ void *dst, u8 val, size_t len);
#endif
generated by cgit (git 2.34.1) at 2025-02-07 00:26:45 +0000