17 files changed, 275 insertions, 9 deletions

diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 350e7f6b72..93ebf3429a 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR	0x38000000
 #define ESW_CONTRL_BASE_ADDR	0x38200000
 #define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
 #define KONA_MST_CLK_BASE_ADDR	0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR	0x3e011000
 #define PMU_BSC_BASE_ADDR	0x3500d000
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 0289ba6a91..88d2ec11a7 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -140,6 +140,7 @@ struct bcm2835_mbox_tag_hdr {
 #define BCM2835_BOARD_REV_B_REV2_f	0xf
 #define BCM2835_BOARD_REV_B_PLUS	0x10
 #define BCM2835_BOARD_REV_CM		0x11
+#define BCM2835_BOARD_REV_A_PLUS	0x12
 
 struct bcm2835_mbox_tag_get_board_rev {
 	struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h
index 320763fd8c..4968d3dd2e 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,7 +41,4 @@ void set_usbhost_mode(unsigned int mode);
 void set_system_display_ctrl(void);
 int exynos_lcd_early_init(const void *blob);
 
-/* Initialize the Parade dP<->LVDS bridge if present */
-int parade_init(const void *blob);
-
 #endif	/* _EXYNOS4_SYSTEM_H */
diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h
new file mode 100644
index 0000000000..130b58bef1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/powergate.h
@@ -0,0 +1,38 @@
+#ifndef _TEGRA_POWERGATE_H_
+#define _TEGRA_POWERGATE_H_
+
+#include <asm/arch/clock.h>
+
+enum tegra_powergate {
+	TEGRA_POWERGATE_CPU,
+	TEGRA_POWERGATE_3D,
+	TEGRA_POWERGATE_VENC,
+	TEGRA_POWERGATE_PCIE,
+	TEGRA_POWERGATE_VDEC,
+	TEGRA_POWERGATE_L2,
+	TEGRA_POWERGATE_MPE,
+	TEGRA_POWERGATE_HEG,
+	TEGRA_POWERGATE_SATA,
+	TEGRA_POWERGATE_CPU1,
+	TEGRA_POWERGATE_CPU2,
+	TEGRA_POWERGATE_CPU3,
+	TEGRA_POWERGATE_CELP,
+	TEGRA_POWERGATE_3D1,
+	TEGRA_POWERGATE_CPU0,
+	TEGRA_POWERGATE_C0NC,
+	TEGRA_POWERGATE_C1NC,
+	TEGRA_POWERGATE_SOR,
+	TEGRA_POWERGATE_DIS,
+	TEGRA_POWERGATE_DISB,
+	TEGRA_POWERGATE_XUSBA,
+	TEGRA_POWERGATE_XUSBB,
+	TEGRA_POWERGATE_XUSBC,
+	TEGRA_POWERGATE_VIC,
+	TEGRA_POWERGATE_IRAM,
+};
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+				      enum periph_id periph);
+int tegra_powergate_power_off(enum tegra_powergate id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
new file mode 100644
index 0000000000..b4b4c8ba4d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -0,0 +1,24 @@
+#ifndef _TEGRA_XUSB_PADCTL_H_
+#define _TEGRA_XUSB_PADCTL_H_
+
+struct tegra_xusb_phy;
+
+/**
+ * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
+ * @type: the type of PHY to obtain
+ *
+ * The type of PHY varies between SoC generations. Typically there are XUSB,
+ * PCIe and SATA PHYs, though not all generations support all of them. The
+ * value of type can usually be directly parsed from a device tree.
+ *
+ * Return: a pointer to the PHY or NULL if no such PHY exists
+ */
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
+
+void tegra_xusb_padctl_init(const void *fdt);
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h
new file mode 100644
index 0000000000..260ea801b8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA114_POWERGATE_H_
+#define _TEGRA114_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA114_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
index 8e39d21a7b..8e65086252 100644
--- a/arch/arm/include/asm/arch-tegra124/clock.h
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -16,4 +16,6 @@
 #define OSC_FREQ_SHIFT          28
 #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h
new file mode 100644
index 0000000000..8a0cfbaf96
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA124_POWERGATE_H_
+#define _TEGRA124_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA124_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index a09cb01978..894be088cd 100644
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -131,7 +131,7 @@ enum periph_id {
 	/* 72 */
 	PERIPH_ID_AFI,
 	PERIPH_ID_CORESIGHT,
-	PERIPH_ID_RESERVED74,
+	PERIPH_ID_PCIEXCLK,
 	PERIPH_ID_AVPUCQ,
 	PERIPH_ID_RESERVED76,
 	PERIPH_ID_RESERVED77,
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
index 889c65a16f..4df8da96e2 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -15,4 +15,6 @@
 #define OSC_FREQ_SHIFT          30
 #define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h
new file mode 100644
index 0000000000..439d88b702
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA20_POWERGATE_H_
+#define _TEGRA20_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA20_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
index 2f24a75cc4..410c352899 100644
--- a/arch/arm/include/asm/arch-tegra30/clock.h
+++ b/arch/arm/include/asm/arch-tegra30/clock.h
@@ -25,4 +25,6 @@
 #define OSC_FREQ_SHIFT          28
 #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
 
+int tegra_plle_enable(void);
+
 #endif	/* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h
new file mode 100644
index 0000000000..c70e44b621
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA30_POWERGATE_H_
+#define _TEGRA30_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA30_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
new file mode 100644
index 0000000000..484559c6cd
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
@@ -0,0 +1,172 @@
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+	u32 ridr;		/* Revision Identification Register */
+	u32 pir;		/* PHY Initialixation Register */
+	u32 pgcr[2];		/* PHY General Configuration Register */
+	u32 pgsr[2];		/* PHY General Status Register */
+	u32 pllcr;		/* PLL Control Register */
+	u32 ptr[5];		/* PHY Timing Register */
+	u32 acmdlr;		/* AC Master Delay Line Register */
+	u32 acbdlr;		/* AC Bit Delay Line Register */
+	u32 aciocr;		/* AC I/O Configuration Register */
+	u32 dxccr;		/* DATX8 Common Configuration Register */
+	u32 dsgcr;		/* DDR System General Configuration Register */
+	u32 dcr;		/* DRAM Configuration Register */
+	u32 dtpr[3];		/* DRAM Timing Parameters Register */
+	u32 mr0;		/* Mode Register 0 */
+	u32 mr1;		/* Mode Register 1 */
+	u32 mr2;		/* Mode Register 2 */
+	u32 mr3;		/* Mode Register 3 */
+	u32 odtcr;		/* ODT Configuration Register */
+	u32 dtcr;		/* Data Training Configuration Register */
+	u32 dtar[4];		/* Data Training Address Register */
+	u32 dtdr[2];		/* Data Training Data Register */
+	u32 dtedr[2];		/* Data Training Eye Data Register */
+	u32 rsv0[13];		/* Reserved */
+	u32 dcuar;		/* DCU Address Register */
+	u32 dcudr;		/* DCU Data Register */
+	u32 dcurr;		/* DCU Run Register */
+	u32 dculr;		/* DCU Loop Register */
+	u32 dcugcr;		/* DCU General Configuration Register */
+	u32 dcutpr;		/* DCU Timing Parameters Register */
+	u32 dcusr[2];		/* DCU Status Register */
+	u32 rsv1[8];		/* Reserved */
+	u32 bistrr;		/* BIST Run Register */
+	u32 bistwcr;		/* BIST Word Count Register */
+	u32 bistmskr[3];	/* BIST Mask Register */
+	u32 bistlsr;		/* BIST LFSR Sed Register */
+	u32 bistar[3];		/* BIST Address Register */
+	u32 bistudpr;		/* BIST User Data Pattern Register */
+	u32 bistgsr;		/* BIST General Status Register */
+	u32 bistwer;		/* BIST Word Error Register */
+	u32 bistber[4];		/* BIST Bit Error Register */
+	u32 bistwcsr;		/* BIST Word Count Status Register */
+	u32 bistfwr[3];		/* BIST Fail Word Register */
+	u32 rsv2[10];		/* Reserved */
+	u32 gpr[2];		/* General Purpose Register */
+	struct ddrphy_zq {	/* ZQ */
+		u32 cr[2];	/* Impedance Control Register */
+		u32 sr[2];	/* Impedance Status Register */
+	} zq[4];
+	struct ddrphy_datx8 {	/* DATX8 */
+		u32 gcr;	/* General Configuration Register */
+		u32 gsr[2];	/* General Status Register */
+		u32 bdlr[5];	/* Bit Delay Line Register */
+		u32 lcdlr[3];	/* Local Calibrated Delay Line Register */
+		u32 mdlr;	/* Master Delay Line Register */
+		u32 gtr;	/* General Timing Register */
+		u32 rsv[3];	/* Reserved */
+	} dx[9];
+} __packed;
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT		(1 <<  0)	/* Initialization Trigger */
+#define PIR_ZCAL		(1 <<  1)	/* Impedance Calibration */
+#define PIR_PLLINIT		(1 <<  4)	/* PLL Initialization */
+#define PIR_DCAL		(1 <<  5)	/* DDL Calibration */
+#define PIR_PHYRST		(1 <<  6)	/* PHY Reset */
+#define PIR_DRAMRST		(1 <<  7)	/* DRAM Reset */
+#define PIR_DRAMINIT		(1 <<  8)	/* DRAM Initialization */
+#define PIR_WL			(1 <<  9)	/* Write Leveling */
+#define PIR_QSGATE		(1 << 10)	/* Read DQS Gate Training */
+#define PIR_WLADJ		(1 << 11)	/* Write Leveling Adjust */
+#define PIR_RDDSKW		(1 << 12)	/* Read Data Bit Deskew */
+#define PIR_WRDSKW		(1 << 13)	/* Write Data Bit Deskew */
+#define PIR_RDEYE		(1 << 14)	/* Read Data Eye Training */
+#define PIR_WREYE		(1 << 15)	/* Write Data Eye Training */
+#define PIR_LOCKBYP		(1 << 28)	/* PLL Lock Bypass */
+#define PIR_DCALBYP		(1 << 29)	/* DDL Calibration Bypass */
+#define PIR_ZCALBYP		(1 << 30)	/* Impedance Calib Bypass */
+#define PIR_INITBYP		(1 << 31)	/* Initialization Bypass */
+
+#define PGSR0_IDONE		(1 <<  0)	/* Initialization Done */
+#define PGSR0_PLDONE		(1 <<  1)	/* PLL Lock Done */
+#define PGSR0_DCDONE		(1 <<  2)	/* DDL Calibration Done */
+#define PGSR0_ZCDONE		(1 <<  3)	/* Impedance Calibration Done */
+#define PGSR0_DIDONE		(1 <<  4)	/* DRAM Initialization Done */
+#define PGSR0_WLDONE		(1 <<  5)	/* Write Leveling Done */
+#define PGSR0_QSGDONE		(1 <<  6)	/* DQS Gate Training Done */
+#define PGSR0_WLADONE		(1 <<  7)	/* Write Leveling Adjust Done */
+#define PGSR0_RDDONE		(1 <<  8)	/* Read Bit Deskew Done */
+#define PGSR0_WDDONE		(1 <<  9)	/* Write Bit Deskew Done */
+#define PGSR0_REDONE		(1 << 10)	/* Read Eye Training Done */
+#define PGSR0_WEDONE		(1 << 11)	/* Write Eye Training Done */
+#define PGSR0_IERR		(1 << 16)	/* Initialization Error */
+#define PGSR0_PLERR		(1 << 17)	/* PLL Lock Error */
+#define PGSR0_DCERR		(1 << 18)	/* DDL Calibration Error */
+#define PGSR0_ZCERR		(1 << 19)	/* Impedance Calib Error */
+#define PGSR0_DIERR		(1 << 20)	/* DRAM Initialization Error */
+#define PGSR0_WLERR		(1 << 21)	/* Write Leveling Error */
+#define PGSR0_QSGERR		(1 << 22)	/* DQS Gate Training Error */
+#define PGSR0_WLAERR		(1 << 23)	/* Write Leveling Adj Error */
+#define PGSR0_RDERR		(1 << 24)	/* Read Bit Deskew Error */
+#define PGSR0_WDERR		(1 << 25)	/* Write Bit Deskew Error */
+#define PGSR0_REERR		(1 << 26)	/* Read Eye Training Error */
+#define PGSR0_WEERR		(1 << 27)	/* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT	28		/* Data Training Error Status*/
+#define PGSR0_DTERR		(7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK		(1 << 31)	/* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN	(0 << 5)
+#define DXCCR_DQSRES_688_OHM	(1 << 5)
+#define DXCCR_DQSRES_611_OHM	(2 << 5)
+#define DXCCR_DQSRES_550_OHM	(3 << 5)
+#define DXCCR_DQSRES_500_OHM	(4 << 5)
+#define DXCCR_DQSRES_458_OHM	(5 << 5)
+#define DXCCR_DQSRES_393_OHM	(6 << 5)
+#define DXCCR_DQSRES_344_OHM	(7 << 5)
+
+#define DXCCR_DQSNRES_OPEN	(0 << 9)
+#define DXCCR_DQSNRES_688_OHM	(1 << 9)
+#define DXCCR_DQSNRES_611_OHM	(2 << 9)
+#define DXCCR_DQSNRES_550_OHM	(3 << 9)
+#define DXCCR_DQSNRES_500_OHM	(4 << 9)
+#define DXCCR_DQSNRES_458_OHM	(5 << 9)
+#define DXCCR_DQSNRES_393_OHM	(6 << 9)
+#define DXCCR_DQSNRES_344_OHM	(7 << 9)
+
+#define DTCR_DTRANK_SHIFT	4		/* Data Training Rank */
+#define DTCR_DTRANK_MASK	(0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR		(1 << 6)	/* Data Training using MPR */
+#define DTCR_RNKEN_SHIFT	24		/* Rank Enable */
+#define DTCR_RNKEN_MASK		(0xf << (DTCR_RNKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT	26		/* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK	(0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY	2
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define NR_DDRPHY_PER_CH		1
+#else
+#define NR_DDRPHY_PER_CH		2
+#endif
+
+#define NR_DDRCH		2
+
+#define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h
index 2c7e829994..a5e2fd9d6c 100644
--- a/arch/arm/include/asm/kona-common/clk.h
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif
diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h
index 74111dc359..835ca7e4b6 100644
--- a/arch/arm/include/asm/semihosting.h
+++ b/arch/arm/include/asm/semihosting.h
@@ -12,10 +12,6 @@
  * code for more information.
  */
 int smh_load(const char *fname, void *memp, int avail, int verbose);
-int smh_read(int fd, void *memp, int len);
-int smh_open(const char *fname, char *modestr);
-int smh_close(int fd);
-int smh_len_fd(int fd);
-int smh_len(const char *fname);
+long smh_len(const char *fname);
 
 #endif /* __SEMIHOSTING_H__ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 61e2914d44..89f2294689 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -212,6 +212,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  */
 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)