diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-omap3/omap.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stih410/sdhci.h | 68 | ||||
| -rw-r--r-- | arch/arm/include/asm/gpio.h | 2 |
3 files changed, 70 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h index 91d73c2f1d..db763e49a3 100644 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ b/arch/arm/include/asm/arch-omap3/omap.h @@ -243,6 +243,7 @@ struct gpio { * ROM code API related flags */ #define OMAP3_GP_ROMCODE_API_L2_INVAL 1 +#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2 #define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 /* diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h new file mode 100644 index 0000000000..8cd77fc687 --- /dev/null +++ b/arch/arm/include/asm/arch-stih410/sdhci.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STI_SDHCI_H__ +#define __STI_SDHCI_H__ + +#define FLASHSS_MMC_CORE_CONFIG_1 0x400 +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) + +#define STI_FLASHSS_MMC_CORE_CONFIG_1 \ + (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ + FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) + +#define FLASHSS_MMC_CORE_CONFIG_2 0x404 +#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) +#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) +#define MAX_BLK_LENGTH_1024 BIT(16) +#define BASE_CLK_FREQ_200 0xc8 + +#define STI_FLASHSS_MMC_CORE_CONFIG2 \ + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ + FLASHSS_MMC_CORECFG_8BIT_EMMC | \ + MAX_BLK_LENGTH_1024 | \ + BASE_CLK_FREQ_200 << 0) + +#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ + MAX_BLK_LENGTH_1024 | \ + BASE_CLK_FREQ_200) + +#define FLASHSS_MMC_CORE_CONFIG_3 0x408 +#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) +#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) +#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) +#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) +#define FLASHSS_MMC_CORECFG_SDMA BIT(0) + +#define STI_FLASHSS_MMC_CORE_CONFIG3 \ + (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ + FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ + FLASHSS_MMC_CORECFG_3P3_VOLT | \ + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ + FLASHSS_MMC_CORECFG_SDMA) + +#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ + (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ + FLASHSS_MMC_CORECFG_3P3_VOLT | \ + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ + FLASHSS_MMC_CORECFG_SDMA) + +#define FLASHSS_MMC_CORE_CONFIG_4 0x40c +#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) +#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) +#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) + +#define STI_FLASHSS_MMC_CORE_CONFIG4 \ + (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ + FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ + FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) + +#define ST_MMC_CCONFIG_REG_5 0x210 +#define SYSCONF_MMC1_ENABLE_BIT 3 + +#endif /* _STI_SDHCI_H_ */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index fe4419cae4..1c5e87340c 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,4 +1,4 @@ -#ifndef CONFIG_ARCH_UNIPHIER +#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> |