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-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h16
-rw-r--r--arch/arm/include/asm/arch-sunxi/spl.h2
-rw-r--r--arch/arm/include/asm/arch-vf610/clock.h3
-rw-r--r--arch/arm/include/asm/arch-vf610/crm_regs.h1
-rw-r--r--arch/arm/include/asm/arch-vf610/ddrmc-vf610.h2
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h2
-rw-r--r--arch/arm/include/asm/arch-vf610/iomux-vf610.h6
-rw-r--r--arch/arm/include/asm/gpio.h3
-rw-r--r--arch/arm/include/asm/io.h21
-rw-r--r--arch/arm/include/asm/mach-imx/video.h1
-rw-r--r--arch/arm/include/asm/secure.h31
11 files changed, 86 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index d8ddecc0bd..15a5b641ff 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -84,6 +84,22 @@
#define MT41K128MJT187E_PHY_FIFO_WE 0x100
#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
+/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */
+#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07
+#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB
+#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA
+#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF
+#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2
+#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30
+#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4
+#define MT41K128M16JT125K_RATIO 0x80
+#define MT41K128M16JT125K_INVERT_CLKOUT 0x0
+#define MT41K128M16JT125K_RD_DQS 0x38
+#define MT41K128M16JT125K_WR_DQS 0x46
+#define MT41K128M16JT125K_PHY_WR_DATA 0x7D
+#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B
+#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B
+
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index 4baba38b00..8c916e8c75 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -28,6 +28,8 @@
#define SUNXI_BOOTED_FROM_NAND 1
#define SUNXI_BOOTED_FROM_MMC2 2
#define SUNXI_BOOTED_FROM_SPI 3
+#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
+#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
/* boot head definition from sun4i boot code */
struct boot_file_head {
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 3bd73a01f3..72184fd608 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,9 @@ enum mxc_clock {
void enable_ocotp_clk(unsigned char enable);
unsigned int mxc_get_clock(enum mxc_clock clk);
u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+#endif
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 9fce49ddc6..0c9ed52933 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -200,6 +200,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18)
#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
index c7da2b8a5e..03e3cecb95 100644
--- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -10,6 +10,8 @@
#ifndef __ASM_ARCH_VF610_DDRMC_H
#define __ASM_ARCH_VF610_DDRMC_H
+#include <asm/arch/iomux-vf610.h>
+
struct ddr3_jedec_timings {
u8 tinit;
u32 trst_pwron;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 5d1f63c98b..ae0a187c4d 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -289,6 +289,8 @@
#define SRC_SRSR_WDOG_M4 (0x1 << 4)
#define SRC_SRSR_WDOG_A5 (0x1 << 3)
#define SRC_SRSR_POR_RST (0x1 << 0)
+#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6)
+#define SRC_SBMR1_BOOTCFG1_MMC BIT(4)
#define SRC_SBMR2_BMOD_MASK (0x3 << 24)
#define SRC_SBMR2_BMOD_SHIFT 24
#define SRC_SBMR2_BMOD_FUSES 0x0
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 01bc2998b8..8ba03e5a17 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -132,10 +132,14 @@ enum {
VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD0__UART2_TX = IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL),
VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD1__UART2_RX = IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL),
VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD2__GPIO_81 = IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
- VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+ VF610_PAD_PTD3__GPIO_82 = IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+ VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 3039e66bf9..992a84152c 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,5 +1,6 @@
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
- !defined(CONFIG_ARCH_K3)
+ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
+ !defined(CONFIG_ARCH_BCM63158)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 12bc7fbe06..e6d27b69f9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -123,6 +123,27 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+ __raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl(c)); __r; })
+#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
+ __raw_readq(c)); __r; })
+
+#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
+ cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
+ cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
+ cpu_to_le64(v), (c)))
+
+/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h
index 812e6f85e4..d1a14ad7d3 100644
--- a/arch/arm/include/asm/mach-imx/video.h
+++ b/arch/arm/include/asm/mach-imx/video.h
@@ -26,4 +26,5 @@ extern size_t display_count;
#endif
int ipu_set_ldb_clock(int rate);
+int ipu_displays_init(void);
#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index d23044a1c3..50582c972b 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,6 +6,37 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
+#ifndef __ASSEMBLY__
+
+typedef struct secure_svc_tbl {
+ u32 id;
+#ifdef CONFIG_ARMV8_PSCI
+ u8 pad[4];
+#endif
+ void *func;
+} secure_svc_tbl_t;
+
+/*
+ * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section
+ */
+#define DECLARE_SECURE_SVC(_name, _id, _fn) \
+ static const secure_svc_tbl_t __secure_svc_ ## _name \
+ __attribute__((used, section("._secure_svc_tbl_entries"))) \
+ = { \
+ .id = _id, \
+ .func = _fn }
+
+#else
+
+#ifdef CONFIG_ARMV8_PSCI
+#define SECURE_SVC_TBL_OFFSET 16
+#else
+#define SECURE_SVC_TBL_OFFSET 8
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
generated by cgit (git 2.34.1) at 2024-12-27 18:59:15 +0000