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-rw-r--r--arch/arm/include/asm/arch-am33xx/clk_synthesizer.h43
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h15
-rw-r--r--arch/arm/include/asm/arch-meson/gxbb.h52
-rw-r--r--arch/arm/include/asm/arch-meson/sm.h12
-rw-r--r--arch/arm/include/asm/arch-omap3/cpu.h7
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3288.h17
-rw-r--r--arch/arm/include/asm/arch-rockchip/grf_rk3288.h53
-rw-r--r--arch/arm/include/asm/omap_common.h11
-rw-r--r--arch/arm/include/asm/psci.h17
-rw-r--r--arch/arm/include/asm/system.h2
10 files changed, 222 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
new file mode 100644
index 0000000000..a5af0120d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -0,0 +1,43 @@
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG 0x0
+#define CLK_SYNTHESIZER_XCSEL 0x05
+#define CLK_SYNTHESIZER_MUX_REG 0x14
+#define CLK_SYNTHESIZER_PDIV2_REG 0x16
+#define CLK_SYNTHESIZER_PDIV3_REG 0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE 0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ * for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+ u32 id;
+ u32 capacitor;
+ u32 mux;
+ u32 pdiv2;
+ u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 97bbfe2e65..43e122e261 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -54,6 +54,21 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz 0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
+#define MT41J128MJT125_RD_DQS_400MHz 0x3A
+#define MT41J128MJT125_WR_DQS_400MHz 0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
+
/* Micron MT41K128M16JT-187E */
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
new file mode 100644
index 0000000000..f90f632daf
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GXBB_H__
+#define __GXBB_H__
+
+#define GXBB_PERIPHS_BASE 0xc8834400
+#define GXBB_HIU_BASE 0xc883c000
+#define GXBB_ETH_BASE 0xc9410000
+
+/* Peripherals registers */
+#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
+#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
+#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
+
+/* Pinmux registers 0 to 12 */
+#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n))
+
+#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
+#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define GXBB_ETH_REG_0_CLK_EN BIT(12)
+
+/* HIU registers */
+#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
+
+#define GXBB_GCLK_MPEG_1_ETH BIT(3)
+
+#endif /* __GXBB_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
new file mode 100644
index 0000000000..225438d6dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 53cc2b098a..e8aa786d2b 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -59,13 +59,8 @@ struct ctrl_id {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-/* device type */
-#define DEVICE_MASK (0x7 << 8)
+/* boot pin mask */
#define SYSBOOT_MASK 0x1F
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
/* device speed */
#define SKUID_CLK_MASK 0xf
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d2690c7788..8a8ca9c9aa 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@ enum {
SDIO0_DIV_MASK = 0x3f,
};
+/* CRU_CLKSEL21_CON */
+enum {
+ MAC_DIV_CON_SHIFT = 0xf,
+ MAC_DIV_CON_MASK = 0x1f,
+
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK = 1,
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+ EMAC_PLL_SHIFT = 0,
+ EMAC_PLL_MASK = 0x3,
+ EMAC_PLL_SELECT_NEW = 0x0,
+ EMAC_PLL_SELECT_CODEC = 0x1,
+ EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 0117a179c9..aaffd19dea 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -718,6 +718,40 @@ enum {
MSCH0_MAINPARTIALPOP_MASK = 1,
};
+/* GRF_SOC_CON1 */
+enum {
+ RMII_MODE_SHIFT = 0xe,
+ RMII_MODE_MASK = 1,
+ RMII_MODE = 1,
+
+ GMAC_CLK_SEL_SHIFT = 0xc,
+ GMAC_CLK_SEL_MASK = 3,
+ GMAC_CLK_SEL_125M = 0,
+ GMAC_CLK_SEL_25M = 0x3,
+ GMAC_CLK_SEL_2_5M = 0x2,
+
+ RMII_CLK_SEL_SHIFT = 0xb,
+ RMII_CLK_SEL_MASK = 1,
+ RMII_CLK_SEL_2_5M = 0,
+ RMII_CLK_SEL_25M,
+
+ GMAC_SPEED_SHIFT = 0xa,
+ GMAC_SPEED_MASK = 1,
+ GMAC_SPEED_10M = 0,
+ GMAC_SPEED_100M,
+
+ GMAC_FLOWCTRL_SHIFT = 0x9,
+ GMAC_FLOWCTRL_MASK = 1,
+
+ GMAC_PHY_INTF_SEL_SHIFT = 0x6,
+ GMAC_PHY_INTF_SEL_MASK = 0x7,
+ GMAC_PHY_INTF_SEL_RGMII = 0x1,
+ GMAC_PHY_INTF_SEL_RMII = 0x4,
+
+ HOST_REMAP_SHIFT = 0x5,
+ HOST_REMAP_MASK = 1
+};
+
/* GRF_SOC_CON2 */
enum {
UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
@@ -765,4 +799,23 @@ enum {
PWM_PWM = 0,
};
+/* GRF_SOC_CON3 */
+enum {
+ RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+ RXCLK_DLY_ENA_GMAC_MASK = 1,
+ RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RXCLK_DLY_ENA_GMAC_ENABLE,
+
+ TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+ TXCLK_DLY_ENA_GMAC_MASK = 1,
+ TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ TXCLK_DLY_ENA_GMAC_ENABLE,
+
+ CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ CLK_RX_DL_CFG_GMAC_MASK = 0x7f,
+
+ CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ CLK_TX_DL_CFG_GMAC_MASK = 0x7f,
+};
+
#endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8fb05e18b9..ac34b0e72f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -717,6 +717,17 @@ static inline u8 is_dra72x(void)
#define DRA722_ES2_0 0x07220200
/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+
+/*
* SRAM scratch space entries
*/
#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606444..3704f077b0 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,7 +18,7 @@
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
-/* PSCI interface */
+/* PSCI 0.1 interface */
#define ARM_PSCI_FN_BASE 0x95c1ba5e
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
@@ -32,6 +32,21 @@
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE 0x84000000
+#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9ae890a830..2bdc0bec82 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -128,6 +128,8 @@ void hvc_call(struct pt_regs *args);
*/
void smc_call(struct pt_regs *args);
+void __noreturn psci_system_reset(bool smc);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
generated by cgit (git 2.34.1) at 2025-02-21 23:42:30 +0000