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-rw-r--r--arch/arm/include/asm/arch-am33xx/clock.h7
-rw-r--r--arch/arm/include/asm/arch-am33xx/clocks_am33xx.h2
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware.h13
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware_am43xx.h13
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h1
5 files changed, 23 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index acf3fd55a8..19ccf5c8db 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -12,6 +12,7 @@
#define _CLOCKS_H_
#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/hardware.h>
#ifdef CONFIG_TI81XX
#include <asm/arch/clock_ti81xx.h>
@@ -103,6 +104,12 @@ extern const struct dpll_regs dpll_mpu_regs;
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
+extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
extern struct cm_wkuppll *const cmwkup;
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index dfdb6c7e1b..653ec1b239 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -26,6 +26,8 @@
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
#define CM_DLL_READYST 0x4
+#define NUM_OPPS 6
+
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index dd950e5ac4..3437e6116d 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,5 +61,18 @@
/* CPSW Config space */
#define CPSW_BASE 0x4A100000
+/* Control status register */
+#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
+#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
+#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
+#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
+#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
+#define CTRL_SYSBOOT_15_14_SHIFT 22
+
+#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
+#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
+
+#define NUM_CRYSTAL_FREQ 0x4
+
int clk_get(int clk);
#endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index a7da6b5cfd..af69ac6f2c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -85,19 +85,6 @@
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
-/* Control status register */
-#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
-#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
-#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
-#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
-#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
-#define CTRL_SYSBOOT_15_14_SHIFT 22
-
-#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
-#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
-
-#define NUM_CRYSTAL_FREQ 0x4
-
/* EDMA3 Base Address */
#define EDMA3_BASE 0x49000000
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 903398fe8f..4e78aafb0b 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -46,3 +46,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
void do_board_detect(void);
+u32 get_sys_clk_index(void);