diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/pmu_rk3399.h | 72 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sdram.h | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sdram_common.h | 90 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 65 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/timer.h | 3 |
7 files changed, 191 insertions, 74 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file mode 100644 index 0000000000..f1096dccce --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ +#define __SOC_ROCKCHIP_RK3399_PMU_H__ + +struct rk3399_pmu_regs { + u32 pmu_wakeup_cfg[5]; + u32 pmu_pwrdn_con; + u32 pmu_pwrdn_st; + u32 pmu_pll_con; + u32 pmu_pwrmode_con; + u32 pmu_sft_con; + u32 pmu_int_con; + u32 pmu_int_st; + u32 pmu_gpio0_pos_int_con; + u32 pmu_gpio0_net_int_con; + u32 pmu_gpio1_pos_int_con; + u32 pmu_gpio1_net_int_con; + u32 pmu_gpio0_pos_int_st; + u32 pmu_gpio0_net_int_st; + u32 pmu_gpio1_pos_int_st; + u32 pmu_gpio1_net_int_st; + u32 pmu_pwrdn_inten; + u32 pmu_pwrdn_status; + u32 pmu_wakeup_status; + u32 pmu_bus_clr; + u32 pmu_bus_idle_req; + u32 pmu_bus_idle_st; + u32 pmu_bus_idle_ack; + u32 pmu_cci500_con; + u32 pmu_adb400_con; + u32 pmu_adb400_st; + u32 pmu_power_st; + u32 pmu_core_pwr_st; + u32 pmu_osc_cnt; + u32 pmu_plllock_cnt; + u32 pmu_pllrst_cnt; + u32 pmu_stable_cnt; + u32 pmu_ddrio_pwron_cnt; + u32 pmu_wakeup_rst_clr_cnt; + u32 pmu_ddr_sref_st; + u32 pmu_scu_l_pwrdn_cnt; + u32 pmu_scu_l_pwrup_cnt; + u32 pmu_scu_b_pwrdn_cnt; + u32 pmu_scu_b_pwrup_cnt; + u32 pmu_gpu_pwrdn_cnt; + u32 pmu_gpu_pwrup_cnt; + u32 pmu_center_pwrdn_cnt; + u32 pmu_center_pwrup_cnt; + u32 pmu_timeout_cnt; + u32 pmu_cpu0apm_con; + u32 pmu_cpu1apm_con; + u32 pmu_cpu2apm_con; + u32 pmu_cpu3apm_con; + u32 pmu_cpu0bpm_con; + u32 pmu_cpu1bpm_con; + u32 pmu_noc_auto_ena; + u32 pmu_pwrdn_con1; + u32 reserved0[0x4]; + u32 pmu_sys_reg_reg0; + u32 pmu_sys_reg_reg1; + u32 pmu_sys_reg_reg2; + u32 pmu_sys_reg_reg3; +}; + +check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); + +#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index bbe425deb9..9220763fa7 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -8,12 +8,6 @@ #ifndef _ASM_ARCH_RK3288_SDRAM_H__ #define _ASM_ARCH_RK3288_SDRAM_H__ -enum { - DDR3 = 3, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk3288_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 671c318d50..8027b53636 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -5,6 +5,44 @@ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H + +enum { + DDR4 = 0, + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF +}; + +struct sdram_cap_info { + unsigned int rank; + /* dram column number, 0 means this channel is invalid */ + unsigned int col; + /* dram bank number, 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + /* + * row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int ddrconfig; +}; + +struct sdram_base_params { + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int num_channels; + unsigned int stride; + unsigned int odt; +}; + /* * sys_reg bitfield struct * [31] row_3_4_ch1 @@ -28,30 +66,82 @@ * [1:0] dbw_ch0 */ #define SYS_REG_DDRTYPE_SHIFT 13 +#define DDR_SYS_REG_VERSION 2 #define SYS_REG_DDRTYPE_MASK 7 #define SYS_REG_NUM_CH_SHIFT 12 #define SYS_REG_NUM_CH_MASK 1 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) #define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) +#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ + SYS_REG_NUM_CH_SHIFT) #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) #define SYS_REG_RANK_MASK 1 +#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \ + SYS_REG_RANK_SHIFT(ch)) #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) #define SYS_REG_COL_MASK 3 +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch)) #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) #define SYS_REG_BK_MASK 1 +#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ + SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) #define SYS_REG_BW_MASK 3 +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) #define SYS_REG_DBW_MASK 3 +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) + +#define SYS_REG_ENC_VERSION(n) ((n) << 28) +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ + (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ + (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (4 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) +#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); /* Called by U-Boot board_init_r for Rockchip SoCs */ int dram_init(void); + +#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) +inline void sdram_print_dram_type(unsigned char dramtype) +{ +} + +inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ +} + +inline void sdram_print_stride(unsigned int stride) +{ +} +#else +void sdram_print_dram_type(unsigned char dramtype); +void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base); +void sdram_print_stride(unsigned int stride); +#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ + #endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h index d0091a7aaf..336c5d7e8c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -7,13 +7,6 @@ #include <common.h> -enum { - DDR3 = 3, - LPDDR2 = 5, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk322x_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index c6a260bad8..dc65ae7924 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -6,14 +6,6 @@ #ifndef _ASM_ARCH_SDRAM_RK3399_H #define _ASM_ARCH_SDRAM_RK3399_H -enum { - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, - UNUSED = 0xFF -}; - struct rk3399_ddr_pctl_regs { u32 denali_ctl[332]; }; @@ -26,6 +18,31 @@ struct rk3399_ddr_pi_regs { u32 denali_pi[200]; }; +union noc_ddrtimingc0 { + u32 d32; + struct { + unsigned burstpenalty : 4; + unsigned reserved0 : 4; + unsigned wrtomwr : 6; + unsigned reserved1 : 18; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + struct rk3399_msch_regs { u32 coreid; u32 revisionid; @@ -44,9 +61,9 @@ struct rk3399_msch_regs { struct rk3399_msch_timings { u32 ddrtiminga0; u32 ddrtimingb0; - u32 ddrtimingc0; + union noc_ddrtimingc0 ddrtimingc0; u32 devtodev0; - u32 ddrmode; + union noc_ddrmode ddrmode; u32 agingx0; }; @@ -72,37 +89,13 @@ struct rk3399_ddr_cic_regs { #define MEM_RST_VALID 1 struct rk3399_sdram_channel { - unsigned int rank; - /* dram column number, 0 means this channel is invalid */ - unsigned int col; - /* dram bank number, 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - /* - * row_3_4 = 1: 6Gb or 12Gb die - * row_3_4 = 0: normal die, power of 2 - */ - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; + struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; -struct rk3399_base_params { - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int num_channels; - unsigned int stride; - unsigned int odt; -}; - struct rk3399_sdram_params { struct rk3399_sdram_channel ch[2]; - struct rk3399_base_params base; + struct sdram_base_params base; struct rk3399_ddr_pctl_regs pctl_regs; struct rk3399_ddr_pi_regs pi_regs; struct rk3399_ddr_publ_regs phy_regs; diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 928e4f258b..905c774c15 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -6,28 +6,6 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H -#ifdef CONFIG_ROCKCHIP_RK3288 -#include <asm/armv7.h> - -static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} -#endif /* CONFIG_ROCKCHIP_RK3288 */ /* provided to defeat compiler optimisation in board_init_f() */ void gru_dummy_function(int i); diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index a8379be912..77b5422044 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -15,7 +15,4 @@ struct rk_timer { u32 timer_int_status; }; -void rockchip_timer_init(void); -void rockchip_udelay(unsigned int usec); - #endif |