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-rw-r--r--arch/arm/include/asm/arch-at91/at91_shdwn.h35
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h9
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h59
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h12
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h19
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h6
-rw-r--r--arch/arm/include/asm/arch-sunxi/mmc.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/timer.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/watchdog.h2
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h5
11 files changed, 88 insertions, 67 deletions
diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h
deleted file mode 100644
index 18d9ea690e..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_shdwn.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
- u32 cr; /* Control Rer. WO */
- u32 mr; /* Mode Register RW 0x00000003 */
- u32 sr; /* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY 0xa5000000
-#define AT91_SHDW_CR_SHDW 0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN 0x00010000
-#define AT91_SHDW_MR_CPTWK0 0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
-
-#define AT91_SHDW_SR_RTTWK 0x00010000
-#define AT91_SHDW_SR_WAKEUP0 0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ba717146f5..78aceef17b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,8 @@
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
@@ -70,7 +72,14 @@
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index ad2ece64f4..02287decc2 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00, /* 256 0x100 */
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
EXYNOS4_GPIO_Z3,
@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
};
enum exynos4X12_gpio_pin {
- /* GPIO_PART1_STARTS */
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
EXYNOS4X12_GPIO_A00, /* 0 */
EXYNOS4X12_GPIO_A01,
EXYNOS4X12_GPIO_A02,
@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00, /* 56 0x38 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00, /* 88 0x58 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_J16,
EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00, /* 256 0x100 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X36,
EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
EXYNOS4X12_GPIO_Z3,
@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Z6,
EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */
+ /* EXYNOS4X12_GPIO_PART4 starts here */
EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
@@ -1339,17 +1353,22 @@ struct gpio_info {
unsigned int max_gpio; /* Maximum GPIO in this part */
};
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index e67b5b9e7d..39f3c0707b 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -89,7 +89,7 @@ struct mxc_ccm_reg {
u32 analog_pll_video_tog;
u32 analog_pll_video_num; /* 0x40b0 */
u32 analog_reserved6[3];
- u32 analog_pll_vedio_denon; /* 0x40c0 */
+ u32 analog_pll_video_denom; /* 0x40c0 */
u32 analog_reserved7[7];
u32 analog_pll_enet; /* 0x40e0 */
u32 analog_pll_enet_set;
@@ -228,6 +228,8 @@ struct mxc_ccm_reg {
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
@@ -931,10 +933,10 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4512..d9db58c9a3 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -14,12 +14,31 @@ enum {
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index c562f621c2..42382a8ae2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,7 @@
#define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
#include <asm/arch/clock_sun6i.h>
#else
#include <asm/arch/clock_sun4i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7bb649950a..437dd35b68 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -155,7 +155,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPF2_SDC0 2
-#ifdef CONFIG_SUN8I
+#ifdef CONFIG_MACH_SUN8I
#define SUNXI_GPF2_UART0_TX 3
#define SUNXI_GPF4_UART0_RX 3
#else
@@ -180,7 +180,9 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 8a216740a7..537f145564 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,7 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
u32 res2[64];
#endif
u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 03a0684c79..9a5e488a38 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
@@ -77,7 +77,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#else /* CONFIG_SUN6I || CONFIG_SUN8I || ... */
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
index ccc8fa32c4..8108be97ba 100644
--- a/arch/arm/include/asm/arch-sunxi/watchdog.h
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -13,7 +13,7 @@
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index a8ca49c343..e0a49be4ff 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -182,6 +182,11 @@ typedef u64 iomux_v3_cfg_t;
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)
generated by cgit (git 2.34.1) at 2024-12-28 22:05:34 +0000