19 files changed, 154 insertions, 711 deletions

diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h
deleted file mode 100644
index c8ef8f528a..0000000000
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2012 Vikram Narayananan
- * <vikram186@gmail.com>
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BCM2835_GPIO_H_
-#define _BCM2835_GPIO_H_
-
-#ifdef CONFIG_BCM2836
-#define BCM2835_GPIO_BASE		0x3f200000
-#else
-#define BCM2835_GPIO_BASE		0x20200000
-#endif
-#define BCM2835_GPIO_COUNT		54
-
-#define BCM2835_GPIO_FSEL_MASK		0x7
-#define BCM2835_GPIO_INPUT		0x0
-#define BCM2835_GPIO_OUTPUT		0x1
-#define BCM2835_GPIO_ALT0		0x4
-#define BCM2835_GPIO_ALT1		0x5
-#define BCM2835_GPIO_ALT2		0x6
-#define BCM2835_GPIO_ALT3		0x7
-#define BCM2835_GPIO_ALT4		0x3
-#define BCM2835_GPIO_ALT5		0x2
-
-#define BCM2835_GPIO_COMMON_BANK(gpio)	((gpio < 32) ? 0 : 1)
-#define BCM2835_GPIO_COMMON_SHIFT(gpio)	(gpio & 0x1f)
-
-#define BCM2835_GPIO_FSEL_BANK(gpio)	(gpio / 10)
-#define BCM2835_GPIO_FSEL_SHIFT(gpio)	((gpio % 10) * 3)
-
-struct bcm2835_gpio_regs {
-	u32 gpfsel[6];
-	u32 reserved1;
-	u32 gpset[2];
-	u32 reserved2;
-	u32 gpclr[2];
-	u32 reserved3;
-	u32 gplev[2];
-	u32 reserved4;
-	u32 gpeds[2];
-	u32 reserved5;
-	u32 gpren[2];
-	u32 reserved6;
-	u32 gpfen[2];
-	u32 reserved7;
-	u32 gphen[2];
-	u32 reserved8;
-	u32 gplen[2];
-	u32 reserved9;
-	u32 gparen[2];
-	u32 reserved10;
-	u32 gppud;
-	u32 gppudclk[2];
-};
-
-/**
- * struct bcm2835_gpio_platdata - GPIO platform description
- *
- * @base: Base address of GPIO controller
- */
-struct bcm2835_gpio_platdata {
-	unsigned long base;
-};
-
-#endif /* _BCM2835_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
deleted file mode 100644
index 04bf480a54..0000000000
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BCM2835_MBOX_H
-#define _BCM2835_MBOX_H
-
-#include <linux/compiler.h>
-
-/*
- * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
- * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
- * However, the VideoCore actually controls the initial SoC boot, and hides
- * much of the hardware behind a protocol. This protocol is transported
- * using the SoC's mailbox hardware module.
- *
- * The mailbox hardware supports passing 32-bit values back and forth.
- * Presumably by software convention of the firmware, the bottom 4 bits of the
- * value are used to indicate a logical channel, and the upper 28 bits are the
- * actual payload. Various channels exist using these simple raw messages. See
- * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
- * example, the messages on the power management channel are a bitmask of
- * devices whose power should be enabled.
- *
- * The property mailbox channel passes messages that contain the (16-byte
- * aligned) ARM physical address of a memory buffer. This buffer is passed to
- * the VC for processing, is modified in-place by the VC, and the address then
- * passed back to the ARM CPU as the response mailbox message to indicate
- * request completion. The buffers have a generic and extensible format; each
- * buffer contains a standard header, a list of "tags", and a terminating zero
- * entry. Each tag contains an ID indicating its type, and length fields for
- * generic parsing. With some limitations, an arbitrary set of tags may be
- * combined together into a single message buffer. This file defines structs
- * representing the header and many individual tag layouts and IDs.
- */
-
-/* Raw mailbox HW */
-
-#ifdef CONFIG_BCM2836
-#define BCM2835_MBOX_PHYSADDR	0x3f00b880
-#else
-#define BCM2835_MBOX_PHYSADDR	0x2000b880
-#endif
-
-struct bcm2835_mbox_regs {
-	u32 read;
-	u32 rsvd0[5];
-	u32 status;
-	u32 config;
-	u32 write;
-};
-
-#define BCM2835_MBOX_STATUS_WR_FULL	0x80000000
-#define BCM2835_MBOX_STATUS_RD_EMPTY	0x40000000
-
-/* Lower 4-bits are channel ID */
-#define BCM2835_CHAN_MASK		0xf
-#define BCM2835_MBOX_PACK(chan, data)	(((data) & (~BCM2835_CHAN_MASK)) | \
-					 (chan & BCM2835_CHAN_MASK))
-#define BCM2835_MBOX_UNPACK_CHAN(val)	((val) & BCM2835_CHAN_MASK)
-#define BCM2835_MBOX_UNPACK_DATA(val)	((val) & (~BCM2835_CHAN_MASK))
-
-/* Property mailbox buffer structures */
-
-#define BCM2835_MBOX_PROP_CHAN		8
-
-/* All message buffers must start with this header */
-struct bcm2835_mbox_hdr {
-	u32 buf_size;
-	u32 code;
-};
-
-#define BCM2835_MBOX_REQ_CODE		0
-#define BCM2835_MBOX_RESP_CODE_SUCCESS	0x80000000
-
-#define BCM2835_MBOX_INIT_HDR(_m_) { \
-		memset((_m_), 0, sizeof(*(_m_))); \
-		(_m_)->hdr.buf_size = sizeof(*(_m_)); \
-		(_m_)->hdr.code = 0; \
-		(_m_)->end_tag = 0; \
-	}
-
-/*
- * A message buffer contains a list of tags. Each tag must also start with
- * a standardized header.
- */
-struct bcm2835_mbox_tag_hdr {
-	u32 tag;
-	u32 val_buf_size;
-	u32 val_len;
-};
-
-#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
-		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
-		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
-		(_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
-	}
-
-#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
-		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
-		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
-		(_t_)->tag_hdr.val_len = 0; \
-	}
-
-/* When responding, the VC sets this bit in val_len to indicate a response */
-#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE	0x80000000
-
-/*
- * Below we define the ID and struct for many possible tags. This header only
- * defines individual tag structs, not entire message structs, since in
- * general an arbitrary set of tags may be combined into a single message.
- * Clients of the mbox API are expected to define their own overall message
- * structures by combining the header, a set of tags, and a terminating
- * entry. For example,
- *
- * struct msg {
- *     struct bcm2835_mbox_hdr hdr;
- *     struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
- *     ... perhaps other tags here ...
- *     u32 end_tag;
- * };
- */
-
-#define BCM2835_MBOX_TAG_GET_BOARD_REV	0x00010002
-
-#ifdef CONFIG_BCM2836
-#define BCM2836_BOARD_REV_2_B		0x4
-#else
-/*
- * 0x2..0xf from:
- * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
- * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
- * 0x10, 0x11 from swarren's testing
- */
-#define BCM2835_BOARD_REV_B_I2C0_2	0x2
-#define BCM2835_BOARD_REV_B_I2C0_3	0x3
-#define BCM2835_BOARD_REV_B_I2C1_4	0x4
-#define BCM2835_BOARD_REV_B_I2C1_5	0x5
-#define BCM2835_BOARD_REV_B_I2C1_6	0x6
-#define BCM2835_BOARD_REV_A_7		0x7
-#define BCM2835_BOARD_REV_A_8		0x8
-#define BCM2835_BOARD_REV_A_9		0x9
-#define BCM2835_BOARD_REV_B_REV2_d	0xd
-#define BCM2835_BOARD_REV_B_REV2_e	0xe
-#define BCM2835_BOARD_REV_B_REV2_f	0xf
-#define BCM2835_BOARD_REV_B_PLUS	0x10
-#define BCM2835_BOARD_REV_CM		0x11
-#define BCM2835_BOARD_REV_A_PLUS	0x12
-#endif
-
-struct bcm2835_mbox_tag_get_board_rev {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 rev;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS	0x00010003
-
-struct bcm2835_mbox_tag_get_mac_address {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u8 mac[6];
-			u8 pad[2];
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_ARM_MEMORY		0x00010005
-
-struct bcm2835_mbox_tag_get_arm_mem {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 mem_base;
-			u32 mem_size;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_POWER_DEVID_SDHCI		0
-#define BCM2835_MBOX_POWER_DEVID_UART0		1
-#define BCM2835_MBOX_POWER_DEVID_UART1		2
-#define BCM2835_MBOX_POWER_DEVID_USB_HCD	3
-#define BCM2835_MBOX_POWER_DEVID_I2C0		4
-#define BCM2835_MBOX_POWER_DEVID_I2C1		5
-#define BCM2835_MBOX_POWER_DEVID_I2C2		6
-#define BCM2835_MBOX_POWER_DEVID_SPI		7
-#define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
-
-#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 0)
-/* Device doesn't exist */
-#define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
-
-#define BCM2835_MBOX_TAG_GET_POWER_STATE	0x00020001
-
-struct bcm2835_mbox_tag_get_power_state {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 device_id;
-		} req;
-		struct {
-			u32 device_id;
-			u32 state;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_SET_POWER_STATE	0x00028001
-
-#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON	(1 << 0)
-#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT	(1 << 1)
-
-struct bcm2835_mbox_tag_set_power_state {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 device_id;
-			u32 state;
-		} req;
-		struct {
-			u32 device_id;
-			u32 state;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
-
-#define BCM2835_MBOX_CLOCK_ID_EMMC	1
-#define BCM2835_MBOX_CLOCK_ID_UART	2
-#define BCM2835_MBOX_CLOCK_ID_ARM	3
-#define BCM2835_MBOX_CLOCK_ID_CORE	4
-#define BCM2835_MBOX_CLOCK_ID_V3D	5
-#define BCM2835_MBOX_CLOCK_ID_H264	6
-#define BCM2835_MBOX_CLOCK_ID_ISP	7
-#define BCM2835_MBOX_CLOCK_ID_SDRAM	8
-#define BCM2835_MBOX_CLOCK_ID_PIXEL	9
-#define BCM2835_MBOX_CLOCK_ID_PWM	10
-
-struct bcm2835_mbox_tag_get_clock_rate {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 clock_id;
-		} req;
-		struct {
-			u32 clock_id;
-			u32 rate_hz;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER	0x00040001
-
-struct bcm2835_mbox_tag_allocate_buffer {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 alignment;
-		} req;
-		struct {
-			u32 fb_address;
-			u32 fb_size;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_RELEASE_BUFFER		0x00048001
-
-struct bcm2835_mbox_tag_release_buffer {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_BLANK_SCREEN		0x00040002
-
-struct bcm2835_mbox_tag_blank_screen {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			/* bit 0 means on, other bots reserved */
-			u32 state;
-		} req;
-		struct {
-			u32 state;
-		} resp;
-	} body;
-};
-
-/* Physical means output signal */
-#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H	0x00040003
-#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H	0x00044003
-#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H	0x00048003
-
-struct bcm2835_mbox_tag_physical_w_h {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 width;
-			u32 height;
-		} req;
-		struct {
-			u32 width;
-			u32 height;
-		} resp;
-	} body;
-};
-
-/* Virtual means display buffer */
-#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H	0x00040004
-#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H	0x00044004
-#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H	0x00048004
-
-struct bcm2835_mbox_tag_virtual_w_h {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 width;
-			u32 height;
-		} req;
-		struct {
-			u32 width;
-			u32 height;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_DEPTH		0x00040005
-#define BCM2835_MBOX_TAG_TEST_DEPTH		0x00044005
-#define BCM2835_MBOX_TAG_SET_DEPTH		0x00048005
-
-struct bcm2835_mbox_tag_depth {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 bpp;
-		} req;
-		struct {
-			u32 bpp;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER	0x00040006
-#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER	0x00044005
-#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER	0x00048006
-
-#define BCM2835_MBOX_PIXEL_ORDER_BGR		0
-#define BCM2835_MBOX_PIXEL_ORDER_RGB		1
-
-struct bcm2835_mbox_tag_pixel_order {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 order;
-		} req;
-		struct {
-			u32 order;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_ALPHA_MODE		0x00040007
-#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE	0x00044007
-#define BCM2835_MBOX_TAG_SET_ALPHA_MODE		0x00048007
-
-#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE	0
-#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT	1
-#define BCM2835_MBOX_ALPHA_MODE_IGNORED		2
-
-struct bcm2835_mbox_tag_alpha_mode {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 alpha;
-		} req;
-		struct {
-			u32 alpha;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PITCH		0x00040008
-
-struct bcm2835_mbox_tag_pitch {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 pitch;
-		} resp;
-	} body;
-};
-
-/* Offset of display window within buffer */
-#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET	0x00040009
-#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET	0x00044009
-#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET	0x00048009
-
-struct bcm2835_mbox_tag_virtual_offset {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 x;
-			u32 y;
-		} req;
-		struct {
-			u32 x;
-			u32 y;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_OVERSCAN		0x0004000a
-#define BCM2835_MBOX_TAG_TEST_OVERSCAN		0x0004400a
-#define BCM2835_MBOX_TAG_SET_OVERSCAN		0x0004800a
-
-struct bcm2835_mbox_tag_overscan {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		/* req not used for get */
-		struct {
-			u32 top;
-			u32 bottom;
-			u32 left;
-			u32 right;
-		} req;
-		struct {
-			u32 top;
-			u32 bottom;
-			u32 left;
-			u32 right;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_GET_PALETTE		0x0004000b
-
-struct bcm2835_mbox_tag_get_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-		} req;
-		struct {
-			u32 data[1024];
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_TEST_PALETTE		0x0004400b
-
-struct bcm2835_mbox_tag_test_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 offset;
-			u32 num_entries;
-			u32 data[256];
-		} req;
-		struct {
-			u32 is_invalid;
-		} resp;
-	} body;
-};
-
-#define BCM2835_MBOX_TAG_SET_PALETTE		0x0004800b
-
-struct bcm2835_mbox_tag_set_palette {
-	struct bcm2835_mbox_tag_hdr tag_hdr;
-	union {
-		struct {
-			u32 offset;
-			u32 num_entries;
-			u32 data[256];
-		} req;
-		struct {
-			u32 is_invalid;
-		} resp;
-	} body;
-};
-
-/*
- * Pass a raw u32 message to the VC, and receive a raw u32 back.
- *
- * Returns 0 for success, any other value for error.
- */
-int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
-
-/*
- * Pass a complete property-style buffer to the VC, and wait until it has
- * been processed.
- *
- * This function expects a pointer to the mbox_hdr structure in an attempt
- * to ensure some degree of type safety. However, some number of tags and
- * a termination value are expected to immediately follow the header in
- * memory, as required by the property protocol.
- *
- * Returns 0 for success, any other value for error.
- */
-int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h
deleted file mode 100644
index 2a21ccbf66..0000000000
--- a/arch/arm/include/asm/arch-bcm2835/sdhci.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _BCM2835_SDHCI_H_
-#define _BCM2835_SDHCI_H_
-
-#ifdef CONFIG_BCM2836
-#define BCM2835_SDHCI_BASE 0x3f300000
-#else
-#define BCM2835_SDHCI_BASE 0x20300000
-#endif
-
-int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h
deleted file mode 100644
index fc7aec7b7c..0000000000
--- a/arch/arm/include/asm/arch-bcm2835/timer.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _BCM2835_TIMER_H
-#define _BCM2835_TIMER_H
-
-#ifdef CONFIG_BCM2836
-#define BCM2835_TIMER_PHYSADDR	0x3f003000
-#else
-#define BCM2835_TIMER_PHYSADDR	0x20003000
-#endif
-
-struct bcm2835_timer_regs {
-	u32 cs;
-	u32 clo;
-	u32 chi;
-	u32 c0;
-	u32 c1;
-	u32 c2;
-	u32 c3;
-};
-
-#define BCM2835_TIMER_CS_M3	(1 << 3)
-#define BCM2835_TIMER_CS_M2	(1 << 2)
-#define BCM2835_TIMER_CS_M1	(1 << 1)
-#define BCM2835_TIMER_CS_M0	(1 << 0)
-
-extern ulong get_timer_us(ulong base);
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h
deleted file mode 100644
index beb6a08206..0000000000
--- a/arch/arm/include/asm/arch-bcm2835/wdog.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _BCM2835_TIMER_H
-#define _BCM2835_TIMER_H
-
-#ifdef CONFIG_BCM2836
-#define BCM2835_WDOG_PHYSADDR			0x3f100000
-#else
-#define BCM2835_WDOG_PHYSADDR			0x20100000
-#endif
-
-struct bcm2835_wdog_regs {
-	u32 unknown0[7];
-	u32 rstc;
-	u32 unknown1;
-	u32 wdog;
-};
-
-#define BCM2835_WDOG_PASSWORD			0x5a000000
-
-#define BCM2835_WDOG_RSTC_WRCFG_MASK		0x00000030
-#define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET	0x00000020
-
-#define BCM2835_WDOG_WDOG_TIMEOUT_MASK		0x0000ffff
-
-#endif
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 2a17dfc6de..d20b7d2ae3 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,9 @@
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9
+#define IPLL	10
 
 #define MASK_PRE_RATIO(x)	(0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)		(0xf << (x << 4))
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15f20..94498695a0 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -71,6 +71,7 @@ struct clk_pm_regs {
 };
 
 /* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_MASK		(0x3 << 7)
 #define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
 #define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
 #define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
@@ -123,6 +124,10 @@ struct clk_pm_regs {
 #define CLK_MAC_SLAVE			(1 << 1)
 #define CLK_MAC_REG			(1 << 0)
 
+/* I2C Clock Control Register bits	*/
+#define CLK_I2C2_ENABLE			(1 << 1)
+#define CLK_I2C1_ENABLE			(1 << 0)
+
 /* Timer Clock Control1 Register bits */
 #define CLK_TIMCLK_MOTOR		(1 << 6)
 #define CLK_TIMCLK_TIMER3		(1 << 5)
@@ -147,11 +152,22 @@ struct clk_pm_regs {
 /* DMA Clock Control Register bits */
 #define CLK_DMA_ENABLE			(1 << 0)
 
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_MLC_INT		(1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK		(1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL		(1 << 1)
+
 unsigned int get_sys_clk_rate(void);
 unsigned int get_hclk_pll_rate(void);
 unsigned int get_hclk_clk_div(void);
 unsigned int get_hclk_clk_rate(void);
 unsigned int get_periph_clk_div(void);
 unsigned int get_periph_clk_rate(void);
+unsigned int get_sdram_clk_rate(void);
 
 #endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441cbfa..d57bc4877e 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
 
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
 /* NOR Flash */
 #if defined(CONFIG_SYS_FLASH_CFI)
 #define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a026b..0b5dca11b8 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -27,6 +27,7 @@
 #define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
 #define RTC_BASE	0x40024000	/* RTC registers base               */
 #define GPIO_BASE	0x40028000	/* GPIO registers base              */
+#define MUX_BASE	0x40028100	/* MUX registers base               */
 #define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
 #define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
 #define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
@@ -37,6 +38,8 @@
 #define UART4_BASE	0x40088000	/* UART 4 registers base            */
 #define UART5_BASE	0x40090000	/* UART 5 registers base            */
 #define UART6_BASE	0x40098000	/* UART 6 registers base            */
+#define I2C1_BASE	0x400A0000	/* I2C  1 registers base            */
+#define I2C2_BASE	0x400A8000	/* I2C  2 registers base            */
 
 /* External SDRAM Memory Bank base addresses */
 #define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
index 82d9bcce50..1a2bab251f 100644
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ b/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -76,4 +76,25 @@ struct emc_regs {
 #define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
 #define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
 
+/* EMC settings for DRAM */
+struct emc_dram_settings {
+	u32	cmddelay;
+	u32	config0;
+	u32	rascas0;
+	u32	rdconfig;
+	u32	trp;
+	u32	tras;
+	u32	tsrex;
+	u32	twr;
+	u32	trc;
+	u32	trfc;
+	u32	txsr;
+	u32	trrd;
+	u32	tmrd;
+	u32	tcdlr;
+	u32	refresh;
+	u32	mode;
+	u32	emode;
+};
+
 #endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 0000000000..3bd94e31a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+	u32 p3_inp_state;
+	u32 p3_outp_set;
+	u32 p3_outp_clr;
+	u32 p3_outp_state;
+	/* Watch out! the following are shared between p2 and p3 */
+	u32 p2_p3_dir_set;
+	u32 p2_p3_dir_clr;
+	u32 p2_p3_dir_state;
+	/* Now back to 'one register for one port' */
+	u32 p2_inp_state;
+	u32 p2_outp_set;
+	u32 p2_outp_clr;
+	u32 reserved1[6];
+	u32 p0_inp_state;
+	u32 p0_outp_set;
+	u32 p0_outp_clr;
+	u32 p0_outp_state;
+	u32 p0_dir_set;
+	u32 p0_dir_clr;
+	u32 p0_dir_state;
+	u32 reserved2;
+	u32 p1_inp_state;
+	u32 p1_outp_set;
+	u32 p1_outp_clr;
+	u32 p1_outp_state;
+	u32 p1_dir_set;
+	u32 p1_dir_clr;
+	u32 p1_dir_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
new file mode 100644
index 0000000000..dc1b5bcdfd
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/mux.h
@@ -0,0 +1,18 @@
+/*
+ * LPC32xx MUX interface
+ *
+ * (C) Copyright 2015  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * MUX register map for LPC32xx
+ */
+
+struct mux_regs {
+	u32 p_mux_set;
+	u32 p_mux_clr;
+	u32 p_mux_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be3cb..c3d890dde4 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -7,6 +7,14 @@
 #ifndef _LPC32XX_SYS_PROTO_H
 #define _LPC32XX_SYS_PROTO_H
 
-void lpc32xx_uart_init(unsigned int uart_id);
+#include <asm/arch/emc.h>
 
+void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
+#if defined(CONFIG_SPL_BUILD)
+void ddr_init(const struct emc_dram_settings *dram);
+#endif
 #endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
index cb538cdc7d..133073321b 100644
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -20,3 +20,4 @@ void sunxi_usbc_enable(int index);
 void sunxi_usbc_disable(int index);
 void sunxi_usbc_vbus_enable(int index);
 void sunxi_usbc_vbus_disable(int index);
+void sunxi_usbc_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 4212e57699..3cc52dd773 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 				int len);
 
+struct pmux_pingrp_desc {
+	u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+	u8 ctl_id;
+	u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN	0
@@ -219,14 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 
 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
-struct pmux_pingrp_desc {
-	u8 funcs[4];
-#if defined(CONFIG_TEGRA20)
-	u8 ctl_id;
-	u8 pull_id;
-#endif /* CONFIG_TEGRA20 */
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+	u32 grp:16;	/* pin group PMUX_MIPIPADCTRLGRP_x   */
+	u32 func:8;	/* function to assign PMUX_FUNC_... */
 };
 
-extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+void pinmux_config_mipipadctrlgrp_table(
+	const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+	u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
 
 #endif /* _TEGRA_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 78bc9e6f17..9fcbb0f80b 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -246,6 +246,11 @@ enum pmux_drvgrp {
 	PMUX_DRVGRP_COUNT,
 };
 
+enum pmux_mipipadctrlgrp {
+	PMUX_MIPIPADCTRLGRP_DSI_B,
+	PMUX_MIPIPADCTRLGRP_COUNT,
+};
+
 enum pmux_func {
 	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_BLINK,
@@ -255,6 +260,7 @@ enum pmux_func {
 	PMUX_FUNC_CLK,
 	PMUX_FUNC_CLK12,
 	PMUX_FUNC_CPU,
+	PMUX_FUNC_CSI,
 	PMUX_FUNC_DAP,
 	PMUX_FUNC_DAP1,
 	PMUX_FUNC_DAP2,
@@ -263,6 +269,7 @@ enum pmux_func {
 	PMUX_FUNC_DISPLAYA_ALT,
 	PMUX_FUNC_DISPLAYB,
 	PMUX_FUNC_DP,
+	PMUX_FUNC_DSI_B,
 	PMUX_FUNC_DTV,
 	PMUX_FUNC_EXTPERIPH1,
 	PMUX_FUNC_EXTPERIPH2,
@@ -336,8 +343,10 @@ enum pmux_func {
 };
 
 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD
 #define TEGRA_PMX_GRPS_HAVE_SCHMT
 #define TEGRA_PMX_GRPS_HAVE_HSM
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index be80434dee..7a34a0186c 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -7,10 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#ifdef __aarch64__
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#endif
-
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index d4a447b2b8..c424a22442 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_CWME9210             3320
 #define MACH_TYPE_CWME9210JS           3321
 #define MACH_TYPE_PGS_SITARA           3322
-#define MACH_TYPE_COLIBRI_TEGRA2       3323
+#define MACH_TYPE_COLIBRI_T20          3323
 #define MACH_TYPE_W21                  3324
 #define MACH_TYPE_POLYSAT1             3325
 #define MACH_TYPE_DATAWAY              3326
@@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type;
 # define machine_is_pgs_v1()	(0)
 #endif
 
-#ifdef CONFIG_MACH_COLIBRI_TEGRA2
+#ifdef CONFIG_MACH_COLIBRI_T20
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_COLIBRI_TEGRA2
+#  define machine_arch_type	MACH_TYPE_COLIBRI_T20
 # endif
-# define machine_is_colibri_tegra2()	(machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
+# define machine_is_colibri_t20()	(machine_arch_type == MACH_TYPE_COLIBRI_T20)
 #else
-# define machine_is_colibri_tegra2()	(0)
+# define machine_is_colibri_t20()	(0)
 #endif
 
 #ifdef CONFIG_MACH_W21
diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h
deleted file mode 100644
index 835ca7e4b6..0000000000
--- a/arch/arm/include/asm/semihosting.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2014 Broadcom Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SEMIHOSTING_H__
-#define __SEMIHOSTING_H__
-
-/*
- * ARM semihosting functions for loading images to memory. See the source
- * code for more information.
- */
-int smh_load(const char *fname, void *memp, int avail, int verbose);
-long smh_len(const char *fname);
-
-#endif /* __SEMIHOSTING_H__ */