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-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h3
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun9i.h6
-rw-r--r--arch/arm/include/asm/arch-sunxi/dma.h16
-rw-r--r--arch/arm/include/asm/arch-sunxi/dma_sun4i.h68
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h3
-rw-r--r--arch/arm/include/asm/arch-sunxi/nand.h67
7 files changed, 164 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 63c33190b8..58aff1687a 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
u32 apb0_gate; /* 0x68 apb0 module clock gating */
u32 apb1_gate; /* 0x6c apb1 module clock gating */
u8 res4[0x10];
- u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
+ u32 nand0_clk_cfg; /* 0x80 nand sub clock control */
u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
@@ -177,7 +177,7 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_ACE 16
#define AHB_GATE_OFFSET_DLL 15
#define AHB_GATE_OFFSET_SDRAM 14
-#define AHB_GATE_OFFSET_NAND 13
+#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MS 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 6465f215e8..8a26b9fc51 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -215,11 +215,14 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB0 24
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_NAND0 13
+#define AHB_GATE_OFFSET_NAND1 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA 6
#define AHB_GATE_OFFSET_SS 5
/* ahb_gate1 offsets */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index c506b0a98f..a61934fb36 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -42,7 +42,7 @@ struct sunxi_ccm_reg {
u32 clk_output_b; /* 0x184 clk_output_a */
u8 reserved5[0x278]; /* 0x188 */
- u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */
+ u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
u8 reserved6[0x08]; /* 0x408 */
u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
@@ -113,8 +113,12 @@ struct sunxi_ccm_reg {
/* ahb_gate0 fields */
/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MMC(x) 8
+/* ahb gate1 field */
+#define AHB_GATE_OFFSET_DMA 24
+
/* apb1_gate fields */
#define APB1_GATE_UART_SHIFT 16
#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
diff --git a/arch/arm/include/asm/arch-sunxi/dma.h b/arch/arm/include/asm/arch-sunxi/dma.h
new file mode 100644
index 0000000000..e54a2ba5eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_H
+#define _SUNXI_DMA_H
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#include <asm/arch/dma_sun4i.h>
+#else
+#error "DMA definition not available for this architecture"
+#endif
+
+#endif /* _SUNXI_DMA_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
new file mode 100644
index 0000000000..778a04bf9e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DMA_SUN4I_H
+#define _SUNXI_DMA_SUN4I_H
+
+struct sunxi_dma_cfg
+{
+ u32 ctl; /* 0x00 Control */
+ u32 src_addr; /* 0x04 Source address */
+ u32 dst_addr; /* 0x08 Destination address */
+ u32 bc; /* 0x0C Byte counter */
+ u32 res0[2];
+ u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */
+ u32 res1;
+};
+
+struct sunxi_dma
+{
+ u32 irq_en; /* 0x000 IRQ enable */
+ u32 irq_pend; /* 0x004 IRQ pending */
+ u32 auto_gate; /* 0x008 auto gating */
+ u32 res0[61];
+ struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */
+ u32 res1[64];
+ struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */
+};
+
+enum ddma_drq_type {
+ DDMA_DST_DRQ_SRAM = 0,
+ DDMA_SRC_DRQ_SRAM = 0,
+ DDMA_DST_DRQ_SDRAM = 1,
+ DDMA_SRC_DRQ_SDRAM = 1,
+ DDMA_DST_DRQ_PATA = 2,
+ DDMA_SRC_DRQ_PATA = 2,
+ DDMA_DST_DRQ_NAND = 3,
+ DDMA_SRC_DRQ_NAND = 3,
+ DDMA_DST_DRQ_USB0 = 4,
+ DDMA_SRC_DRQ_USB0 = 4,
+ DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
+ DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
+ DDMA_DST_DRQ_SPI1_TX = 8,
+ DDMA_SRC_DRQ_SPI1_RX = 9,
+ DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
+ DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
+ DDMA_DST_DRQ_TCON0 = 14,
+ DDMA_DST_DRQ_TCON1 = 15,
+ DDMA_DST_DRQ_MSC = 23,
+ DDMA_SRC_DRQ_MSC = 23,
+ DDMA_DST_DRQ_SPI0_TX = 26,
+ DDMA_SRC_DRQ_SPI0_RX = 27,
+ DDMA_DST_DRQ_SPI2_TX = 28,
+ DDMA_SRC_DRQ_SPI2_RX = 29,
+ DDMA_DST_DRQ_SPI3_TX = 30,
+ DDMA_SRC_DRQ_SPI3_RX = 31,
+};
+
+#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f)
+#define SUNXI_DMA_CTL_MODE_IO (1 << 5)
+#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9)
+#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16)
+#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25)
+#define SUNXI_DMA_CTL_TRIGGER (1 << 31)
+
+#endif /* _SUNXI_DMA_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 148123a87f..b628fee3ea 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -157,6 +157,8 @@ enum sunxi_gpio_number {
#define SUN5I_GPB_UART0 2
#define SUN8I_GPB_UART2 2
+#define SUNXI_GPC_NAND 2
+
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
@@ -185,6 +187,7 @@ enum sunxi_gpio_number {
#define SUN8I_GPH_TWI1 2
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
+#define SUN9I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
diff --git a/arch/arm/include/asm/arch-sunxi/nand.h b/arch/arm/include/asm/arch-sunxi/nand.h
new file mode 100644
index 0000000000..22844d84b8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/nand.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_NAND_H
+#define _SUNXI_NAND_H
+
+#include <linux/types.h>
+
+struct sunxi_nand
+{
+ u32 ctl; /* 0x000 Configure and control */
+ u32 st; /* 0x004 Status information */
+ u32 intr; /* 0x008 Interrupt control */
+ u32 timing_ctl; /* 0x00C Timing control */
+ u32 timing_cfg; /* 0x010 Timing configure */
+ u32 addr_low; /* 0x014 Low word address */
+ u32 addr_high; /* 0x018 High word address */
+ u32 block_num; /* 0x01C Data block number */
+ u32 data_cnt; /* 0x020 Data counter for transfer */
+ u32 cmd; /* 0x024 NDFC commands */
+ u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
+ u32 wcmd_set; /* 0x02C Write command set */
+ u32 io_data; /* 0x030 IO data */
+ u32 ecc_ctl; /* 0x034 ECC configure and control */
+ u32 ecc_st; /* 0x038 ECC status and operation info */
+ u32 efr; /* 0x03C Enhanced feature */
+ u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
+ u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
+ u32 user_data[16]; /* 0x050[16] User data field */
+ u32 efnand_st; /* 0x090 EFNAND status */
+ u32 res0[3];
+ u32 spare_area; /* 0x0A0 Spare area configure */
+ u32 pat_id; /* 0x0A4 Pattern ID register */
+ u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
+ u32 rdata_sta_0; /* 0x0AC Read data status 0 */
+ u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
+ u32 res1[3];
+ u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
+ u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
+};
+
+#define SUNXI_NAND_CTL_EN (1 << 0)
+#define SUNXI_NAND_CTL_RST (1 << 1)
+#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
+#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
+
+#define SUNXI_NAND_ST_CMD_INT (1 << 1)
+#define SUNXI_NAND_ST_DMA_INT (1 << 2)
+#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
+
+#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
+#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
+#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
+#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
+#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
+
+#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
+#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
+#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
+#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
+#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
+#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
+
+#endif /* _SUNXI_NAND_H */
generated by cgit (git 2.34.1) at 2024-12-28 05:52:50 +0000