3 files changed, 58 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 0b5dca11b8..0de894bf97 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -27,7 +27,7 @@
 #define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
 #define RTC_BASE	0x40024000	/* RTC registers base               */
 #define GPIO_BASE	0x40028000	/* GPIO registers base              */
-#define MUX_BASE	0x40028100	/* MUX registers base               */
+#define MUX_BASE	0x40028000	/* MUX registers base               */
 #define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
 #define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
 #define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
new file mode 100644
index 0000000000..c9cf9df7cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
@@ -0,0 +1,40 @@
+/*
+ * LPC32xx GPIO interface macro for pin mapping.
+ *
+ * (C) Copyright 2015  DENX Software Engineering GmbH
+ * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_GPIO_GRP_H
+#define _LPC32XX_GPIO_GRP_H
+
+/*
+ * Macro to map the pin for the lpc32xx_gpio driver.
+ * Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127;
+ *         mapping is done per register, as group of 32.
+ *         (see drivers/gpio/lpc32xx_gpio.c for details).
+ *       - macros can be use with the following pins:
+ *         P0.0 - P0.7
+ *         P1.0 - P1.23
+ *         P2.0 - P2.12
+ *         P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
+ *         P3 GPO_0 - GPO_23
+ *         P3 GPIO_0 - GPIO_5 (output register only)
+ */
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP 32
+#define LPC32XX_GPIO_P2_GRP 64
+#define LPC32XX_GPI_P3_GRP  96
+#define LPC32XX_GPO_P3_GRP  96
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
index dc1b5bcdfd..665ea3fcc2 100644
--- a/arch/arm/include/asm/arch-lpc32xx/mux.h
+++ b/arch/arm/include/asm/arch-lpc32xx/mux.h
@@ -12,7 +12,24 @@
  */
 
 struct mux_regs {
+	u32 reserved1[10];
+	u32 p2_mux_set;
+	u32 p2_mux_clr;
+	u32 p2_mux_state;
+	u32 reserved2[51];
 	u32 p_mux_set;
 	u32 p_mux_clr;
 	u32 p_mux_state;
+	u32 reserved3;
+	u32 p3_mux_set;
+	u32 p3_mux_clr;
+	u32 p3_mux_state;
+	u32 reserved4;
+	u32 p0_mux_set;
+	u32 p0_mux_clr;
+	u32 p0_mux_state;
+	u32 reserved5;
+	u32 p1_mux_set;
+	u32 p1_mux_clr;
+	u32 p1_mux_state;
 };