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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h82
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h3
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h9
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h5
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h2
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h9
-rw-r--r--arch/arm/include/asm/fsl_secure_boot.h68
-rw-r--r--arch/arm/include/asm/psci.h21
9 files changed, 137 insertions, 64 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 44fe0c0095..b0ad4b4626 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -149,43 +149,43 @@
#define CONFIG_ARM_ERRATA_833471
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#elif defined(CONFIG_LS1043A)
-#define CONFIG_MAX_CPUS 4
+#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 7
-#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
-#define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
+#define CONFIG_SYS_FSL_SEC_BE
+
+#define CONFIG_SYS_FSL_SRDS_1
+/* SoC related */
+#ifdef CONFIG_LS1043A
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define SRDS_MAX_LANES 4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-
+#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
@@ -205,32 +205,40 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1012A)
#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
-
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#elif defined(CONFIG_LS1046A)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
-#define SRDS_MAX_LANES 4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_SEC_BE
+/* SMMU Defintions */
+#define SMMU_BASE 0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x01410000
+#define GICC_BASE 0x01420000
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
+#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 5fd5e87ea8..e2d96a1b78 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 487cba8080..e1b3f44d85 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
enum srds {
FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
};
#endif
@@ -150,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c15bd..95a42935ca 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -31,9 +31,9 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
@@ -94,6 +94,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
@@ -227,6 +228,8 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
#define RCW_SB_EN_REG_INDEX 7
#define RCW_SB_EN_MASK 0x00200000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb371..93e26c1d7f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -52,8 +52,8 @@
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@@ -156,6 +156,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 39e8c7a17c..8d4a7adb1d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -44,6 +44,8 @@ struct cpu_type {
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
+#define SVR_LS1046A 0x870700
+#define SVR_LS1026A 0x870708
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 04abec467c..d408fe4056 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define OCRAM_BASE_ADDR 0x10000000
-#define OCRAM_SIZE 0x00020000
+#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
@@ -32,16 +32,15 @@
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS102XA_USB1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
-#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 53cd7550a0..b35c271bba 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -17,8 +17,6 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_CMD_BLOB
-#define CONFIG_CMD_HASH
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SHA_PROG_HW_ACCEL
@@ -28,6 +26,28 @@
#define CONFIG_FSL_CAAM
#endif
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_DM 1
+#define CONFIG_SPL_CRYPTO_SUPPORT
+#define CONFIG_SPL_HASH_SUPPORT
+#define CONFIG_SPL_RSA
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_BLOB
+#define CONFIG_CMD_HASH
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
@@ -58,39 +78,55 @@
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#else
#define CONFIG_EXTRA_ENV \
- "setenv fdt_high 0xcfffffff;" \
- "setenv initrd_high 0xcfffffff;" \
+ "setenv fdt_high 0xffffffff;" \
+ "setenv initrd_high 0xffffffff;" \
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#endif
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
* Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
+ defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTSCRIPT_COPY_RAM
#endif
-/* The address needs to be modified according to NOR and DDR memory map */
+/* The address needs to be modified according to NOR, NAND, SD and
+ * DDR memory map
+ */
#ifdef CONFIG_LS2080A
-#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
-#define CONFIG_BS_ADDR_FLASH 0x583900000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000
+#define CONFIG_BS_ADDR_DEVICE 0x583900000
#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
#define CONFIG_BS_ADDR_RAM 0xa3900000
+#define CONFIG_BS_HDR_SIZE 0x00002000
+#define CONFIG_BS_SIZE 0x00001000
+#else
+#ifdef CONFIG_SD_BOOT
+/* For SD boot address and size are assigned in terms of sector
+ * offset and no. of sectors respectively.
+ */
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800
+#define CONFIG_BS_ADDR_DEVICE 0x00000840
+#define CONFIG_BS_HDR_SIZE 0x00000010
+#define CONFIG_BS_SIZE 0x00000008
#else
-#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
-#define CONFIG_BS_ADDR_FLASH 0x60060000
-#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
-#define CONFIG_BS_ADDR_RAM 0xa0060000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
+#define CONFIG_BS_ADDR_DEVICE 0x60060000
+#define CONFIG_BS_HDR_SIZE 0x00002000
+#define CONFIG_BS_SIZE 0x00001000
+#endif /* #ifdef CONFIG_SD_BOOT */
+#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
+#define CONFIG_BS_ADDR_RAM 0x81020000
#endif
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
-#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
-#define CONFIG_BS_SIZE 0x00001000
#else
-#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
-/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
+/* BOOTSCRIPT_ADDR is not required */
#endif
#include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index e76ecb27a7..8aefaa7708 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -31,6 +31,12 @@
#define ARM_PSCI_RET_NI (-1)
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+#define ARM_PSCI_RET_ALREADY_ON (-4)
+#define ARM_PSCI_RET_ON_PENDING (-5)
+#define ARM_PSCI_RET_INTERNAL_FAILURE (-6)
+#define ARM_PSCI_RET_NOT_PRESENT (-7)
+#define ARM_PSCI_RET_DISABLED (-8)
+#define ARM_PSCI_RET_INVALID_ADDRESS (-9)
/* PSCI 0.2 interface */
#define ARM_PSCI_0_2_FN_BASE 0x84000000
@@ -47,10 +53,25 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+/* PSCI 1.0 interface */
+#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
+#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
+#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12)
+#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13)
+#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14)
+#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15)
+#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
+#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
+/* PSCI affinity level state returned by AFFINITY_INFO */
+#define PSCI_AFFINITY_LEVEL_ON 0
+#define PSCI_AFFINITY_LEVEL_OFF 1
+#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
+
#ifndef __ASSEMBLY__
#include <asm/types.h>
generated by cgit (git 2.34.1) at 2024-12-25 16:22:39 +0000