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-rw-r--r--arch/arm/include/asm/arch-bcm2835/gpio.h9
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h87
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/gpio.h7
-rw-r--r--arch/arm/include/asm/arch-tegra114/tegra114_spi.h41
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra20_sflash.h41
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra20_slink.h41
-rw-r--r--arch/arm/include/asm/imx-common/mxc_i2c.h4
7 files changed, 53 insertions, 177 deletions
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h
index 9a49b6e05e..db42896201 100644
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ b/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -52,4 +52,13 @@ struct bcm2835_gpio_regs {
u32 gppudclk[2];
};
+/**
+ * struct bcm2835_gpio_platdata - GPIO platform description
+ *
+ * @base: Base address of GPIO controller
+ */
+struct bcm2835_gpio_platdata {
+ unsigned long base;
+};
+
#endif /* _BCM2835_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 8fb5c2321e..ad2ece64f4 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,7 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */
+ EXYNOS4_GPIO_X00, /* 256 0x100 */
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
@@ -292,7 +292,7 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X05,
EXYNOS4_GPIO_X06,
EXYNOS4_GPIO_X07,
- EXYNOS4_GPIO_X10, /* 904 0x388 */
+ EXYNOS4_GPIO_X10, /* 264 0x108 */
EXYNOS4_GPIO_X11,
EXYNOS4_GPIO_X12,
EXYNOS4_GPIO_X13,
@@ -300,7 +300,7 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X15,
EXYNOS4_GPIO_X16,
EXYNOS4_GPIO_X17,
- EXYNOS4_GPIO_X20, /* 912 0x390 */
+ EXYNOS4_GPIO_X20, /* 272 0x110 */
EXYNOS4_GPIO_X21,
EXYNOS4_GPIO_X22,
EXYNOS4_GPIO_X23,
@@ -308,7 +308,7 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X25,
EXYNOS4_GPIO_X26,
EXYNOS4_GPIO_X27,
- EXYNOS4_GPIO_X30, /* 920 0x398 */
+ EXYNOS4_GPIO_X30, /* 280 0x118 */
EXYNOS4_GPIO_X31,
EXYNOS4_GPIO_X32,
EXYNOS4_GPIO_X33,
@@ -318,7 +318,7 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */
+ EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
@@ -389,7 +389,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */
+ EXYNOS4X12_GPIO_F00, /* 56 0x38 */
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
@@ -397,7 +397,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F05,
EXYNOS4X12_GPIO_F06,
EXYNOS4X12_GPIO_F07,
- EXYNOS4X12_GPIO_F10, /* 104 0x68 */
+ EXYNOS4X12_GPIO_F10, /* 64 0x40 */
EXYNOS4X12_GPIO_F11,
EXYNOS4X12_GPIO_F12,
EXYNOS4X12_GPIO_F13,
@@ -405,7 +405,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F15,
EXYNOS4X12_GPIO_F16,
EXYNOS4X12_GPIO_F17,
- EXYNOS4X12_GPIO_F20, /* 112 0x70 */
+ EXYNOS4X12_GPIO_F20, /* 72 0x48 */
EXYNOS4X12_GPIO_F21,
EXYNOS4X12_GPIO_F22,
EXYNOS4X12_GPIO_F23,
@@ -413,7 +413,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F25,
EXYNOS4X12_GPIO_F26,
EXYNOS4X12_GPIO_F27,
- EXYNOS4X12_GPIO_F30, /* 120 0x78 */
+ EXYNOS4X12_GPIO_F30, /* 80 0x50 */
EXYNOS4X12_GPIO_F31,
EXYNOS4X12_GPIO_F32,
EXYNOS4X12_GPIO_F33,
@@ -421,7 +421,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */
+ EXYNOS4X12_GPIO_J00, /* 88 0x58 */
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
@@ -429,7 +429,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_J05,
EXYNOS4X12_GPIO_J06,
EXYNOS4X12_GPIO_J07,
- EXYNOS4X12_GPIO_J10, /* 152 0x98 */
+ EXYNOS4X12_GPIO_J10, /* 96 0x60 */
EXYNOS4X12_GPIO_J11,
EXYNOS4X12_GPIO_J12,
EXYNOS4X12_GPIO_J13,
@@ -439,8 +439,8 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_J17,
/* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */
- EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
@@ -448,7 +448,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_K05,
EXYNOS4X12_GPIO_K06,
EXYNOS4X12_GPIO_K07,
- EXYNOS4X12_GPIO_K10, /* 184 0xB8 */
+ EXYNOS4X12_GPIO_K10, /* 112 0x70 */
EXYNOS4X12_GPIO_K11,
EXYNOS4X12_GPIO_K12,
EXYNOS4X12_GPIO_K13,
@@ -456,7 +456,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_K15,
EXYNOS4X12_GPIO_K16,
EXYNOS4X12_GPIO_K17,
- EXYNOS4X12_GPIO_K20, /* 192 0xC0 */
+ EXYNOS4X12_GPIO_K20, /* 120 0x78 */
EXYNOS4X12_GPIO_K21,
EXYNOS4X12_GPIO_K22,
EXYNOS4X12_GPIO_K23,
@@ -464,7 +464,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_K25,
EXYNOS4X12_GPIO_K26,
EXYNOS4X12_GPIO_K27,
- EXYNOS4X12_GPIO_K30, /* 200 0xC8 */
+ EXYNOS4X12_GPIO_K30, /* 128 0x80 */
EXYNOS4X12_GPIO_K31,
EXYNOS4X12_GPIO_K32,
EXYNOS4X12_GPIO_K33,
@@ -472,7 +472,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_K35,
EXYNOS4X12_GPIO_K36,
EXYNOS4X12_GPIO_K37,
- EXYNOS4X12_GPIO_L00, /* 208 0xD0 */
+ EXYNOS4X12_GPIO_L00, /* 136 0x88 */
EXYNOS4X12_GPIO_L01,
EXYNOS4X12_GPIO_L02,
EXYNOS4X12_GPIO_L03,
@@ -480,7 +480,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_L05,
EXYNOS4X12_GPIO_L06,
EXYNOS4X12_GPIO_L07,
- EXYNOS4X12_GPIO_L10, /* 216 0xD8 */
+ EXYNOS4X12_GPIO_L10, /* 144 0x90 */
EXYNOS4X12_GPIO_L11,
EXYNOS4X12_GPIO_L12,
EXYNOS4X12_GPIO_L13,
@@ -488,7 +488,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_L15,
EXYNOS4X12_GPIO_L16,
EXYNOS4X12_GPIO_L17,
- EXYNOS4X12_GPIO_L20, /* 224 0xE0 */
+ EXYNOS4X12_GPIO_L20, /* 152 0x98 */
EXYNOS4X12_GPIO_L21,
EXYNOS4X12_GPIO_L22,
EXYNOS4X12_GPIO_L23,
@@ -496,7 +496,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_L25,
EXYNOS4X12_GPIO_L26,
EXYNOS4X12_GPIO_L27,
- EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */
+ EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */
EXYNOS4X12_GPIO_Y01,
EXYNOS4X12_GPIO_Y02,
EXYNOS4X12_GPIO_Y03,
@@ -504,7 +504,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y05,
EXYNOS4X12_GPIO_Y06,
EXYNOS4X12_GPIO_Y07,
- EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */
+ EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */
EXYNOS4X12_GPIO_Y11,
EXYNOS4X12_GPIO_Y12,
EXYNOS4X12_GPIO_Y13,
@@ -512,7 +512,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y15,
EXYNOS4X12_GPIO_Y16,
EXYNOS4X12_GPIO_Y17,
- EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */
+ EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */
EXYNOS4X12_GPIO_Y21,
EXYNOS4X12_GPIO_Y22,
EXYNOS4X12_GPIO_Y23,
@@ -520,7 +520,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y25,
EXYNOS4X12_GPIO_Y26,
EXYNOS4X12_GPIO_Y27,
- EXYNOS4X12_GPIO_Y30, /* 256 0x100 */
+ EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */
EXYNOS4X12_GPIO_Y31,
EXYNOS4X12_GPIO_Y32,
EXYNOS4X12_GPIO_Y33,
@@ -528,7 +528,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y35,
EXYNOS4X12_GPIO_Y36,
EXYNOS4X12_GPIO_Y37,
- EXYNOS4X12_GPIO_Y40, /* 264 0x108 */
+ EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */
EXYNOS4X12_GPIO_Y41,
EXYNOS4X12_GPIO_Y42,
EXYNOS4X12_GPIO_Y43,
@@ -536,7 +536,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y45,
EXYNOS4X12_GPIO_Y46,
EXYNOS4X12_GPIO_Y47,
- EXYNOS4X12_GPIO_Y50, /* 272 0x110 */
+ EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */
EXYNOS4X12_GPIO_Y51,
EXYNOS4X12_GPIO_Y52,
EXYNOS4X12_GPIO_Y53,
@@ -544,7 +544,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y55,
EXYNOS4X12_GPIO_Y56,
EXYNOS4X12_GPIO_Y57,
- EXYNOS4X12_GPIO_Y60, /* 280 0x118 */
+ EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */
EXYNOS4X12_GPIO_Y61,
EXYNOS4X12_GPIO_Y62,
EXYNOS4X12_GPIO_Y63,
@@ -552,7 +552,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */
+ EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
@@ -560,7 +560,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M05,
EXYNOS4X12_GPIO_M06,
EXYNOS4X12_GPIO_M07,
- EXYNOS4X12_GPIO_M10, /* 320 0xF8 */
+ EXYNOS4X12_GPIO_M10, /* 224 0xe0 */
EXYNOS4X12_GPIO_M11,
EXYNOS4X12_GPIO_M12,
EXYNOS4X12_GPIO_M13,
@@ -568,7 +568,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M15,
EXYNOS4X12_GPIO_M16,
EXYNOS4X12_GPIO_M17,
- EXYNOS4X12_GPIO_M20, /* 328 0x100 */
+ EXYNOS4X12_GPIO_M20, /* 232 0xe8 */
EXYNOS4X12_GPIO_M21,
EXYNOS4X12_GPIO_M22,
EXYNOS4X12_GPIO_M23,
@@ -576,7 +576,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M25,
EXYNOS4X12_GPIO_M26,
EXYNOS4X12_GPIO_M27,
- EXYNOS4X12_GPIO_M30, /* 336 0x108 */
+ EXYNOS4X12_GPIO_M30, /* 240 0xf0 */
EXYNOS4X12_GPIO_M31,
EXYNOS4X12_GPIO_M32,
EXYNOS4X12_GPIO_M33,
@@ -584,7 +584,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M35,
EXYNOS4X12_GPIO_M36,
EXYNOS4X12_GPIO_M37,
- EXYNOS4X12_GPIO_M40, /* 344 0x110 */
+ EXYNOS4X12_GPIO_M40, /* 248 0xf8 */
EXYNOS4X12_GPIO_M41,
EXYNOS4X12_GPIO_M42,
EXYNOS4X12_GPIO_M43,
@@ -592,7 +592,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */
+ EXYNOS4X12_GPIO_X00, /* 256 0x100 */
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
@@ -600,7 +600,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X05,
EXYNOS4X12_GPIO_X06,
EXYNOS4X12_GPIO_X07,
- EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */
+ EXYNOS4X12_GPIO_X10, /* 264 0x108 */
EXYNOS4X12_GPIO_X11,
EXYNOS4X12_GPIO_X12,
EXYNOS4X12_GPIO_X13,
@@ -608,7 +608,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X15,
EXYNOS4X12_GPIO_X16,
EXYNOS4X12_GPIO_X17,
- EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */
+ EXYNOS4X12_GPIO_X20, /* 272 0x110 */
EXYNOS4X12_GPIO_X21,
EXYNOS4X12_GPIO_X22,
EXYNOS4X12_GPIO_X23,
@@ -616,7 +616,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X25,
EXYNOS4X12_GPIO_X26,
EXYNOS4X12_GPIO_X27,
- EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */
+ EXYNOS4X12_GPIO_X30, /* 280 0x118 */
EXYNOS4X12_GPIO_X31,
EXYNOS4X12_GPIO_X32,
EXYNOS4X12_GPIO_X33,
@@ -626,7 +626,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
@@ -637,7 +637,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Z7,
/* GPIO_PART4_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
EXYNOS4X12_GPIO_V02,
@@ -646,7 +646,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_V05,
EXYNOS4X12_GPIO_V06,
EXYNOS4X12_GPIO_V07,
- EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */
+ EXYNOS4X12_GPIO_V10, /* 304 0x130 */
EXYNOS4X12_GPIO_V11,
EXYNOS4X12_GPIO_V12,
EXYNOS4X12_GPIO_V13,
@@ -654,7 +654,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_V15,
EXYNOS4X12_GPIO_V16,
EXYNOS4X12_GPIO_V17,
- EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */
+ EXYNOS4X12_GPIO_V20, /* 312 0x138 */
EXYNOS4X12_GPIO_V21,
EXYNOS4X12_GPIO_V22,
EXYNOS4X12_GPIO_V23,
@@ -662,7 +662,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_V25,
EXYNOS4X12_GPIO_V26,
EXYNOS4X12_GPIO_V27,
- EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */
+ EXYNOS4X12_GPIO_V30, /* 320 0x140 */
EXYNOS4X12_GPIO_V31,
EXYNOS4X12_GPIO_V32,
EXYNOS4X12_GPIO_V33,
@@ -670,7 +670,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_V35,
EXYNOS4X12_GPIO_V36,
EXYNOS4X12_GPIO_V37,
- EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */
+ EXYNOS4X12_GPIO_V40, /* 328 0x148 */
EXYNOS4X12_GPIO_V41,
EXYNOS4X12_GPIO_V42,
EXYNOS4X12_GPIO_V43,
@@ -1504,12 +1504,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
void gpio_set_rate(int gpio, int mode);
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
int s5p_gpio_get_pin(unsigned gpio);
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index d5dbc22c18..2de205e74b 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -682,8 +682,7 @@ enum s5pc110_gpio_pin {
S5PC110_GPIO_MP285,
S5PC110_GPIO_MP286,
S5PC110_GPIO_MP287,
- S5PC110_GPIO_RES,
- S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
+ S5PC110_GPIO_H00,
S5PC110_GPIO_H01,
S5PC110_GPIO_H02,
S5PC110_GPIO_H03,
@@ -815,11 +814,7 @@ static const struct gpio_name_num_table s5pc110_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
void gpio_set_rate(int gpio, int mode);
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
int s5p_gpio_get_pin(unsigned gpio);
/* GPIO pins per bank */
diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
deleted file mode 100644
index 48197bc27f..0000000000
--- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra SPI controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_SPI_H_
-#define _TEGRA114_SPI_H_
-
-#include <asm/types.h>
-
-int tegra114_spi_init(int *node_list, int count);
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra114_spi_free_slave(struct spi_slave *slave);
-int tegra114_spi_claim_bus(struct spi_slave *slave);
-void tegra114_spi_cs_activate(struct spi_slave *slave);
-void tegra114_spi_cs_deactivate(struct spi_slave *slave);
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA114_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
deleted file mode 100644
index e8cc68c6ea..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra20 SPI-FLASH controller
- *
- * Copyright 2010-2012 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_SPI_H_
-#define _TEGRA20_SPI_H_
-
-#include <asm/types.h>
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra20_spi_free_slave(struct spi_slave *slave);
-int tegra20_spi_init(int *node_list, int count);
-int tegra20_spi_claim_bus(struct spi_slave *slave);
-void tegra20_spi_cs_activate(struct spi_slave *slave);
-void tegra20_spi_cs_deactivate(struct spi_slave *slave);
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
deleted file mode 100644
index 5aa74ddd6d..0000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA30_SPI_H_
-#define _TEGRA30_SPI_H_
-
-#include <asm/types.h>
-
-int tegra30_spi_init(int *node_list, int count);
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra30_spi_free_slave(struct spi_slave *slave);
-int tegra30_spi_claim_bus(struct spi_slave *slave);
-void tegra30_spi_cs_activate(struct spi_slave *slave);
-void tegra30_spi_cs_deactivate(struct spi_slave *slave);
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA30_SPI_H_ */
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h
index 182c2f397f..af86163535 100644
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -52,8 +52,8 @@ struct i2c_pads_info {
&mx6q_##name : &mx6s_##name
#endif
-void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
- struct i2c_pads_info *p);
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+ struct i2c_pads_info *p);
void bus_i2c_init(void *base, int speed, int slave_addr,
int (*idle_bus_fn)(void *p), void *p);
int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
generated by cgit (git 2.34.1) at 2025-01-30 18:53:51 +0000