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-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h3
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h7
-rw-r--r--arch/arm/include/asm/omap_mmc.h59
4 files changed, 65 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index ee2e78b99b..3d718c02df 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -135,7 +135,7 @@
/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
index c997004039..a8780eeef8 100644
--- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
+++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
@@ -83,6 +83,9 @@
void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
struct iodelay_cfg_entry const *iodelay,
int niodelays);
+void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays);
int __recalibrate_iodelay_start(void);
void __recalibrate_iodelay_end(int ret);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index a6b3557b50..d43cd7f2e7 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -35,6 +35,12 @@ struct pad_conf_entry {
u32 val;
};
+struct mmc_platform_fixups {
+ const char *hw_rev;
+ u32 unsupported_caps;
+ u32 max_freq;
+};
+
struct omap_sysinfo {
char *board_string;
};
@@ -71,6 +77,7 @@ void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
void setup_warmreset_time(void);
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
static inline u32 div_round_up(u32 num, u32 den)
{
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index bf9de9b211..3d70148882 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -39,7 +39,9 @@ struct hsmmc {
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
+ unsigned int pwcnt; /* 0x30 */
+ unsigned int dll; /* 0x34 */
+ unsigned char res3[0xcc];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
@@ -53,9 +55,11 @@ struct hsmmc {
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
+ unsigned char res4[0x4];
+ unsigned int ac12; /* 0x13C */
unsigned int capa; /* 0x140 */
- unsigned char res5[0x10];
+ unsigned int capa2; /* 0x144 */
+ unsigned char res5[0xc];
unsigned int admaes; /* 0x154 */
unsigned int admasal; /* 0x158 */
};
@@ -65,6 +69,8 @@ struct omap_hsmmc_plat {
struct hsmmc *base_addr;
struct mmc mmc;
bool cd_inverted;
+ u32 controller_flags;
+ const char *hw_rev;
};
/*
@@ -87,6 +93,7 @@ struct omap_hsmmc_plat {
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
+#define DDR (0x1 << 19)
#define DMA_MASTER (0x1 << 20)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
@@ -124,8 +131,10 @@ struct omap_hsmmc_plat {
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
+#define SDVS_MASK (0x7 << 9)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
+#define SDVS_3V3 (0x7 << 9)
#define DMA_SELECT (0x2 << 3)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
@@ -159,8 +168,20 @@ struct omap_hsmmc_plat {
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
+#define VS33_3V3SUP BIT(24)
+#define VS30_3V0SUP BIT(25)
+#define VS18_1V8SUP BIT(26)
+
+#define AC12_ET BIT(22)
+#define AC12_V1V8_SIGEN BIT(19)
+#define AC12_SCLK_SEL BIT(23)
+#define AC12_UHSMC_MASK (7 << 16)
+#define AC12_UHSMC_DDR50 (4 << 16)
+#define AC12_UHSMC_SDR104 (3 << 16)
+#define AC12_UHSMC_SDR50 (2 << 16)
+#define AC12_UHSMC_SDR25 (1 << 16)
+#define AC12_UHSMC_SDR12 (0 << 16)
+#define AC12_UHSMC_RES (0x7 << 16)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
@@ -172,15 +193,43 @@ struct omap_hsmmc_plat {
#define CLK_400KHZ 1
#define CLK_MISC 2
+#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
+
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE 192 /* MHz */
+#else
#define MMC_CLOCK_REFERENCE 96 /* MHz */
+#endif
+
+/* DLL */
+#define DLL_SWT BIT(20)
+#define DLL_FORCE_SR_C_SHIFT 13
+#define DLL_FORCE_SR_C_MASK 0x7f
+#define DLL_FORCE_VALUE BIT(12)
+#define DLL_CALIB BIT(1)
+
+#define MAX_PHASE_DELAY 0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50 BIT(13)
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
+ IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
+ IE_BRR | IE_BWR | IE_TC | IE_CC)
+
+#define CON_CLKEXTFREE BIT(16)
+#define CON_PADEN BIT(15)
+#define PSTATE_CLEV BIT(24)
+#define PSTATE_DLEV (0xF << 20)
+#define PSTATE_DLEV_DAT0 (0x1 << 20)
+
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);