diff options
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-meson/gpio.h | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/fmc.h | 74 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/rcc.h | 24 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32.h | 13 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 15 |
5 files changed, 13 insertions, 124 deletions
diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h new file mode 100644 index 0000000000..7079ab32ce --- /dev/null +++ b/arch/arm/include/asm/arch-meson/gpio.h @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h deleted file mode 100644 index 4741e5a0a3..0000000000 --- a/arch/arm/include/asm/arch-stm32f7/fmc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2013 - * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_FMC_H_ -#define _MACH_FMC_H_ - -struct stm32_fmc_regs { - u32 sdcr1; /* Control register 1 */ - u32 sdcr2; /* Control register 2 */ - u32 sdtr1; /* Timing register 1 */ - u32 sdtr2; /* Timing register 2 */ - u32 sdcmr; /* Mode register */ - u32 sdrtr; /* Refresh timing register */ - u32 sdsr; /* Status register */ -}; - -/* - * FMC registers base - */ -#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE) - -/* Control register SDCR */ -#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ -#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ -#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ -#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ -#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ -#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ -#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ -#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ -#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ - -/* Timings register SDTR */ -#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ -#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ -#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ -#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ -#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ -#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ -#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ - - -#define FMC_SDCMR_NRFS_SHIFT 5 - -#define FMC_SDCMR_MODE_NORMAL 0 -#define FMC_SDCMR_MODE_START_CLOCK 1 -#define FMC_SDCMR_MODE_PRECHARGE 2 -#define FMC_SDCMR_MODE_AUTOREFRESH 3 -#define FMC_SDCMR_MODE_WRITE_MODE 4 -#define FMC_SDCMR_MODE_SELFREFRESH 5 -#define FMC_SDCMR_MODE_POWERDOWN 6 - -#define FMC_SDCMR_BANK_1 BIT(4) -#define FMC_SDCMR_BANK_2 BIT(3) - -#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 - -#define FMC_SDSR_BUSY BIT(5) - -#define FMC_BUSY_WAIT() do { \ - __asm__ __volatile__ ("dsb" : : : "memory"); \ - while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ - ; \ - } while (0) - - -#endif /* _MACH_FMC_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h index 0f8d50b4c6..a33f8cf9bc 100644 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -8,44 +8,24 @@ #ifndef _STM32_RCC_H #define _STM32_RCC_H +#include <dt-bindings/mfd/stm32f7-rcc.h> + /* * RCC AHB1ENR specific definitions */ -#define RCC_AHB1ENR_GPIO_A_EN BIT(0) -#define RCC_AHB1ENR_GPIO_B_EN BIT(1) -#define RCC_AHB1ENR_GPIO_C_EN BIT(2) -#define RCC_AHB1ENR_GPIO_D_EN BIT(3) -#define RCC_AHB1ENR_GPIO_E_EN BIT(4) -#define RCC_AHB1ENR_GPIO_F_EN BIT(5) -#define RCC_AHB1ENR_GPIO_G_EN BIT(6) -#define RCC_AHB1ENR_GPIO_H_EN BIT(7) -#define RCC_AHB1ENR_GPIO_I_EN BIT(8) -#define RCC_AHB1ENR_GPIO_J_EN BIT(9) -#define RCC_AHB1ENR_GPIO_K_EN BIT(10) #define RCC_AHB1ENR_ETHMAC_EN BIT(25) #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) -#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28) - -/* - * RCC AHB3ENR specific definitions - */ -#define RCC_AHB3ENR_FMC_EN BIT(0) -#define RCC_AHB3ENR_QSPI_EN BIT(1) /* * RCC APB1ENR specific definitions */ #define RCC_APB1ENR_TIM2EN BIT(0) -#define RCC_APB1ENR_USART2EN BIT(17) -#define RCC_APB1ENR_USART3EN BIT(18) #define RCC_APB1ENR_PWREN BIT(28) /* * RCC APB2ENR specific definitions */ -#define RCC_APB2ENR_USART1EN BIT(4) -#define RCC_APB2ENR_USART6EN BIT(5) #define RCC_APB2ENR_SYSCFGEN BIT(14) #endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 14e3398768..87aee6057b 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -57,12 +57,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [5 ... 7] = 256 * 1024 }; -enum clock { - CLOCK_CORE, - CLOCK_AHB, - CLOCK_APB1, - CLOCK_APB2 -}; #define STM32_BUS_MASK GENMASK(31, 16) struct stm32_rcc_regs { @@ -101,11 +95,6 @@ struct stm32_rcc_regs { }; #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) -struct stm32_rcc_ext_f7_regs { - u32 dckcfgr2; /* dedicated clocks configuration register */ -}; -#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs))) - struct stm32_pwr_regs { u32 cr1; /* power control register 1 */ u32 csr1; /* power control/status register 2 */ @@ -114,8 +103,6 @@ struct stm32_pwr_regs { }; #define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) -int configure_clocks(void); -unsigned long clock_get(enum clock clck); void stm32_flash_latency_cfg(int latency); #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 3c5604ae29..9c1ec02233 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -21,24 +21,9 @@ enum periph_id { }; enum periph_clock { - USART1_CLOCK_CFG = 0, - USART2_CLOCK_CFG, - GPIO_A_CLOCK_CFG, - GPIO_B_CLOCK_CFG, - GPIO_C_CLOCK_CFG, - GPIO_D_CLOCK_CFG, - GPIO_E_CLOCK_CFG, - GPIO_F_CLOCK_CFG, - GPIO_G_CLOCK_CFG, - GPIO_H_CLOCK_CFG, - GPIO_I_CLOCK_CFG, - GPIO_J_CLOCK_CFG, - GPIO_K_CLOCK_CFG, SYSCFG_CLOCK_CFG, TIMER2_CLOCK_CFG, - FMC_CLOCK_CFG, STMMAC_CLOCK_CFG, - QSPI_CLOCK_CFG, }; #endif /* __ASM_ARM_ARCH_PERIPH_H */ |