diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_common.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_sfr.h (renamed from arch/arm/mach-at91/include/mach/sama5_sfr.h) | 52 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 23 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/hardware.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sam9x60.h | 169 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d2.h | 4 |
6 files changed, 248 insertions, 5 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index df7d0e7051..e929b5e1d2 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -35,6 +35,9 @@ void at91_disable_wdt(void); void matrix_init(void); void redirect_int_from_saic_to_aic(void); void configure_2nd_sram_as_l2_cache(void); +#ifdef CONFIG_ATMEL_SFR +void configure_ddrcfg_input_buffers(bool open); +#endif int at91_set_ethaddr(int offset); int at91_video_show_board_info(void); diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h index f9c412f998..0300c336dd 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/at91_sfr.h @@ -6,12 +6,15 @@ * Bo Shen <voice.shen@atmel.com> */ -#ifndef __SAMA5_SFR_H -#define __SAMA5_SFR_H +#ifndef __AT91_SFR_H +#define __AT91_SFR_H struct atmel_sfr { u32 reserved1; /* 0x00 */ - u32 ddrcfg; /* 0x04: DDR Configuration Register */ + union { + u32 ddrcfg; /* 0x04: DDR Configuration Register */ + u32 ebicsa; /* 0x04: EBI Chip Select Register */ + }; u32 reserved2; /* 0x08 */ u32 reserved3; /* 0x0c */ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ @@ -28,7 +31,16 @@ struct atmel_sfr { }; /* Register Mapping*/ +#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ +#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ +/* 0x08 ~ 0x0c: Reserved */ +#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ +#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ +#define AT91_SFR_LS 0x7c /* Light Sleep Register */ +#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ +#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */ /* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 @@ -58,9 +70,39 @@ struct atmel_sfr { #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) -#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) - /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 +/* Bit field in DDRCFG */ +#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 +#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 + +#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) +#define AT91_SFR_CCFG_EBI_DBPUC BIT(8) +#define AT91_SFR_CCFG_EBI_DBPDC BIT(9) +#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16) +#define AT91_SFR_CCFG_EBI_DRIVE BIT(17) +#define AT91_SFR_CCFG_DQIEN_F BIT(20) +#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) +#define AT91_SFR_CCFG_DDR_MP_EN BIT(25) + +#define AT91_SFR_OHCIICR_RES(x) BIT(x) +#define AT91_SFR_OHCIICR_ARIE BIT(4) +#define AT91_SFR_OHCIICR_APPSTART BIT(5) +#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) +#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define AT91_SFR_OHCIISR_RIS(x) BIT(x) + +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) + +#define AT91_SFR_UTMISWAP_PORT(x) BIT(x) + +#define AT91_SFR_LS_VALUE(x) BIT(x) +#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) + +#define AT91_SFR_WPMR_WPEN BIT(0) +#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 45a76a60fa..40ec87e2ff 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -18,6 +18,9 @@ struct atmel_mpddrc_config { u32 tpr1; u32 tpr2; u32 md; + u32 lpddr23_lpr; + u32 cal_mr4; + u32 tim_cal; }; /* @@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); +int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value); + int ddr3_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); @@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 +#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8) + +/* Bit field in refresh timer register */ +#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16) +#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20) /* Bit field in configuration register */ #define ATMEL_MPDDRC_CR_NC_MASK 0x3 @@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) @@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 +/* Bit field in LPDDR2 - LPDDR3 Low Power Register */ +#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24) + +/* Bit field in CAL_MR4 Calibration and MR4 Register */ +#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0) +#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16) + +/* Bit field in TIM_CAL Timing Calibration Register */ +#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0) + #endif diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 3a7752b999..88acca8549 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -22,6 +22,8 @@ # include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) # include <asm/arch/at91sam9x5.h> +#elif defined(CONFIG_SAM9X60) +# include <asm/arch/sam9x60.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h new file mode 100644 index 0000000000..0f00a9ae87 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAM9X60 SoC. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + */ + +#ifndef __SAM9X60_H__ +#define __SAM9X60_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_FLEXCOM0 5 /* FLEXCOM 0 */ +#define ATMEL_ID_FLEXCOM1 6 /* FLEXCOM 1 */ +#define ATMEL_ID_FLEXCOM2 7 /* FLEXCOM 2 */ +#define ATMEL_ID_FLEXCOM3 8 /* FLEXCOM 3 */ +#define ATMEL_ID_FLEXCOM6 9 /* FLEXCOM 6 */ +#define ATMEL_ID_FLEXCOM7 10 /* FLEXCOM 7 */ +#define ATMEL_ID_FLEXCOM8 11 /* FLEXCOM 8 */ +#define ATMEL_ID_SDMMC0 12 /* SDMMC 0 */ +#define ATMEL_ID_FLEXCOM4 13 /* FLEXCOM 4 */ +#define ATMEL_ID_FLEXCOM5 14 /* FLEXCOM 5 */ +#define ATMEL_ID_FLEXCOM9 15 /* FLEXCOM 9 */ +#define ATMEL_ID_FLEXCOM10 16 /* FLEXCOM 10 */ +#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 19 /* ADC Controller */ +#define ATMEL_ID_XDMAC0 20 /* XDMA Controller 0 */ +#define ATMEL_ID_MATRIX 21 /* BUS Matrix */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ +#define ATMEL_ID_EMAC0 24 /* Ethernet MAC 0 */ +#define ATMEL_ID_LCDC 25 /* LCD Controller */ +#define ATMEL_ID_SDMMC1 26 /* SDMMC 1 */ +#define ATMEL_ID_EMAC1 27 /* Ethernet MAC `1 */ +#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ +#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ +#define ATMEL_ID_TRNG 38 /* True Random Number Generator */ +#define ATMEL_ID_PIOD 44 /* Parallel I/O Controller D */ +#define ATMEL_ID_DBGU 47 /* Debug unit */ + +/* + * User Peripheral physical base addresses. + */ +#define ATMEL_BASE_FLEXCOM4 0xf0000000 +#define ATMEL_BASE_FLEXCOM5 0xf0004000 +#define ATMEL_BASE_XDMA0 0xf0008000 +#define ATMEL_BASE_SSC 0xf0010000 +#define ATMEL_BASE_QSPI 0xf0014000 +#define ATMEL_BASE_CAN0 0xf8000000 +#define ATMEL_BASE_CAN1 0xf8004000 +#define ATMEL_BASE_TC0 0xf8008000 +#define ATMEL_BASE_TC1 0xf8008040 +#define ATMEL_BASE_TC2 0xf8008080 +#define ATMEL_BASE_TC3 0xf800c000 +#define ATMEL_BASE_TC4 0xf800c040 +#define ATMEL_BASE_TC5 0xf800c080 +#define ATMEL_BASE_FLEXCOM6 0xf8010000 +#define ATMEL_BASE_FLEXCOM7 0xf8014000 +#define ATMEL_BASE_FLEXCOM8 0xf8018000 +#define ATMEL_BASE_FLEXCOM0 0xf801c000 +#define ATMEL_BASE_FLEXCOM1 0xf8020000 +#define ATMEL_BASE_FLEXCOM2 0xf8024000 +#define ATMEL_BASE_FLEXCOM3 0xf8028000 +#define ATMEL_BASE_EMAC0 0xf802c000 +#define ATMEL_BASE_EMAC1 0xf8030000 +#define ATMEL_BASE_PWM 0xf8034000 +#define ATMEL_BASE_LCDC 0xf8038000 +#define ATMEL_BASE_UDPHS 0xf803c000 +#define ATMEL_BASE_FLEXCOM9 0xf8040000 +#define ATMEL_BASE_FLEXCOM10 0xf8044000 +#define ATMEL_BASE_ISI 0xf8048000 +#define ATMEL_BASE_ADC 0xf804c000 +#define ATMEL_BASE_SFR 0xf8050000 +#define ATMEL_BASE_SYS 0xffffc000 + +/* + * System Peripherals + */ +#define ATMEL_BASE_MATRIX 0xffffde00 +#define ATMEL_BASE_PMECC 0xffffe000 +#define ATMEL_BASE_PMERRLOC 0xffffe600 +#define ATMEL_BASE_MPDDRC 0xffffe800 +#define ATMEL_BASE_SMC 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffec00 +#define ATMEL_BASE_AIC 0xfffff100 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffe00 +#define ATMEL_BASE_SHDWC 0xfffffe10 +#define ATMEL_BASE_PIT 0xfffffe40 +#define ATMEL_BASE_GPBR 0xfffffe60 +#define ATMEL_BASE_RTC 0xfffffea8 +#define ATMEL_BASE_WDT 0xffffff80 + +/* + * Internal Memory. + */ +#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ + +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_SDMMC0 0x80000000 +#define ATMEL_BASE_SDMMC1 0x90000000 + +/* 9x60 series chip id definitions */ +#define ARCH_ID_SAM9X60 0x819b35a0 +#define ARCH_ID_VERSION_MASK 0x1f +#define ARCH_EXID_SAM9X60 0x00000000 + +#define cpu_is_sam9x60() (get_chip_id() == ARCH_ID_SAM9X60) + +/* + * Cpu Name + */ +#define ATMEL_CPU_NAME get_cpu_name() + +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_NO_PLLB +#define PLL_ID_PLLA 0 +#define PLL_ID_UPLL 1 + +/* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 + +/* + * SAM9X60 specific prototypes + */ +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_emac1(void); +unsigned int has_emac0(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index c7d9bb5ad3..d1b2e01cdd 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -220,7 +220,11 @@ #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 #define ARCH_EXID_SAMA5D27C_D5M 0x00000032 #define ARCH_EXID_SAMA5D27C_D1G 0x00000033 +#define ARCH_EXID_SAMA5D27C_LD1G 0x00000061 +#define ARCH_EXID_SAMA5D27C_LD2G 0x00000062 #define ARCH_EXID_SAMA5D28C_D1G 0x00000013 +#define ARCH_EXID_SAMA5D28C_LD1G 0x00000071 +#define ARCH_EXID_SAMA5D28C_LD2G 0x00000072 /* Checked if defined in ethernet driver macb */ #define cpu_is_sama5d2 _cpu_is_sama5d2 |