diff options
Diffstat (limited to 'arch/arm/mach-exynos/clock.c')
| -rw-r--r-- | arch/arm/mach-exynos/clock.c | 31 |
1 files changed, 24 insertions, 7 deletions
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 6a3cd44b5d..73aa4cdad3 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -345,7 +345,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) int i; struct clk_bit_info *info; - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) info = exynos542x_bit_info; else info = exynos5_bit_info; @@ -557,7 +557,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral) unsigned long clock_get_periph_rate(int peripheral) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos542x_get_periph_rate(peripheral); return exynos5_get_periph_rate(peripheral); } else { @@ -1317,6 +1317,19 @@ int exynos5_set_epll_clk(unsigned long rate) return 0; } +static int exynos5420_set_i2s_clk_source(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + + setbits_le32(&clk->src_top6, EXYNOS5420_CLK_SRC_MOUT_EPLL); + clrsetbits_le32(&clk->src_mau, EXYNOS5420_AUDIO0_SEL_MASK, + (EXYNOS5420_CLK_SRC_SCLK_EPLL)); + setbits_le32(EXYNOS5_AUDIOSS_BASE, 1 << 0); + + return 0; +} + int exynos5_set_i2s_clk_source(unsigned int i2s_id) { struct exynos5_clock *clk = @@ -1575,7 +1588,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else if (cpu_is_exynos4()) { @@ -1691,7 +1704,7 @@ void set_mmc_clk(int dev_index, unsigned int div) div -= 1; if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1739,7 +1752,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } @@ -1758,8 +1771,12 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, int set_i2s_clk_source(unsigned int i2s_id) { - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_source(i2s_id); + if (cpu_is_exynos5()) { + if (proid_is_exynos542x()) + return exynos5420_set_i2s_clk_source(); + else + return exynos5_set_i2s_clk_source(i2s_id); + } return 0; } |