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-rw-r--r--arch/arm/mach-exynos/include/mach/system.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 3ffb296a57..2c94a6bea0 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -38,16 +38,6 @@ struct exynos5_sysreg {
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
/*
- * Data Synchronization Barrier acts as a special kind of memory barrier.
- * No instruction in program order after this instruction executes until
- * this instruction completes. This instruction completes when:
- * - All explicit memory accesses before this instruction complete.
- * - All Cache, Branch predictor and TLB maintenance operations before
- * this instruction complete.
- */
-#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
-
-/*
* This instruction causes an event to be signaled to all cores
* within a multiprocessor system. If SEV is implemented,
* WFE must also be implemented.