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-rw-r--r--arch/arm/mach-imx/mx6/Kconfig23
-rw-r--r--arch/arm/mach-imx/mx6/clock.c2
-rw-r--r--arch/arm/mach-imx/mx6/opos6ul.c2
-rw-r--r--arch/arm/mach-imx/mx6/soc.c55
4 files changed, 56 insertions, 26 deletions
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 9bae748c67..a1aa36bc22 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -1,24 +1,32 @@
if ARCH_MX6
+config MX6_SMP
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_761320
+ select ARM_ERRATA_794072
+ select ARM_ERRATA_845369
+ bool
+
config MX6
+ select ARM_ERRATA_743622 if !MX6UL
bool
default y
- select ARM_ERRATA_743622 if !MX6UL
- select ARM_ERRATA_751472 if !MX6UL
- select ARM_ERRATA_761320 if !MX6UL
- select ARM_ERRATA_794072 if !MX6UL
imply CMD_FUSE
config MX6D
+ select MX6_SMP
bool
config MX6DL
+ select MX6_SMP
bool
config MX6Q
+ select MX6_SMP
bool
config MX6QDL
+ select MX6_SMP
bool
config MX6S
@@ -30,7 +38,6 @@ config MX6SL
config MX6SX
select ROM_UNIFIED_SECTIONS
bool
- imply ENV_IS_IN_MMC
config MX6SLL
select ROM_UNIFIED_SECTIONS
@@ -332,6 +339,11 @@ config TARGET_PCM058
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_PFLA02
+ bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
config TARGET_SECOMX6
bool "secomx6 boards"
@@ -429,6 +441,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
+source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 1f2739e864..0e019c4262 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -19,7 +19,7 @@ enum pll_clocks {
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
PLL_AUDIO, /* AUDIO PLL */
- PLL_VIDEO, /* AUDIO PLL */
+ PLL_VIDEO, /* VIDEO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index 22b244079b..f8d7e8ee68 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -132,7 +132,7 @@ int board_late_init(void)
/* In bootstrap don't use the env vars */
if (((reg & 0x3000000) >> 24) == 0x1) {
set_default_env(NULL);
- setenv("preboot", "");
+ env_set("preboot", "");
}
return opos6ul_board_late_init();
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index af316735ee..9ede1f5435 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -114,6 +114,12 @@ u32 get_cpu_rev(void)
#define OCOTP_CFG3_SPEED_528MHZ 1
#define OCOTP_CFG3_SPEED_696MHZ 2
+/*
+ * For i.MX6ULL
+ */
+#define OCOTP_CFG3_SPEED_792MHZ 2
+#define OCOTP_CFG3_SPEED_900MHZ 3
+
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,11 +132,22 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
- if (is_mx6ul() || is_mx6ull()) {
+ if (is_mx6ul()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
- return 69600000;
+ return 696000000;
+ else
+ return 0;
+ }
+
+ if (is_mx6ull()) {
+ if (val == OCOTP_CFG3_SPEED_528MHZ)
+ return 528000000;
+ else if (val == OCOTP_CFG3_SPEED_792MHZ)
+ return 792000000;
+ else if (val == OCOTP_CFG3_SPEED_900MHZ)
+ return 900000000;
else
return 0;
}
@@ -234,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
+ /* No LDO_SOC/PU/ARM */
+ if (is_mx6sll())
+ return 0;
+
if (mv < 725)
val = 0x00; /* Power gated off */
else if (mv > 1450)
@@ -293,7 +314,7 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -344,20 +365,10 @@ static void init_bandgap(void)
}
}
-#ifdef CONFIG_MX6SL
-static void set_preclk_from_osc(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg;
-
- reg = readl(&mxc_ccm->cscmr1);
- reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
- writel(reg, &mxc_ccm->cscmr1);
-}
-#endif
-
int arch_cpu_init(void)
{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
init_aips();
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
@@ -421,12 +432,14 @@ int arch_cpu_init(void)
}
/* Set perclk to source from OSC 24MHz */
-#if defined(CONFIG_MX6SL)
- set_preclk_from_osc();
-#endif
+ if (is_mx6sl())
+ setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+ if (is_mx6sx())
+ setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
+
init_src();
return 0;
@@ -495,6 +508,10 @@ uint mmc_get_env_part(struct mmc *mmc)
int board_postclk_init(void)
{
+ /* NO LDO SOC on i.MX6SLL */
+ if (is_mx6sll())
+ return 0;
+
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
return 0;
@@ -576,7 +593,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
- if (is_mx6sx() || is_mx6ul() || is_mx6ull())
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
generated by cgit (git 2.34.1) at 2025-01-31 05:39:12 +0000