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-rw-r--r--arch/arm/mach-imx/mx7/Makefile2
-rw-r--r--arch/arm/mach-imx/mx7/snvs.c22
-rw-r--r--arch/arm/mach-imx/mx7/soc.c24
3 files changed, 47 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile
index ce289c1415..e6bef6acee 100644
--- a/arch/arm/mach-imx/mx7/Makefile
+++ b/arch/arm/mach-imx/mx7/Makefile
@@ -5,7 +5,7 @@
#
#
-obj-y := soc.o clock.o clock_slice.o ddr.o
+obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o
ifdef CONFIG_ARMV7_PSCI
obj-y += psci-mx7.o psci.o
diff --git a/arch/arm/mach-imx/mx7/snvs.c b/arch/arm/mach-imx/mx7/snvs.c
new file mode 100644
index 0000000000..7e649b8513
--- /dev/null
+++ b/arch/arm/mach-imx/mx7/snvs.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2018 Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/bitops.h>
+
+#define SNVS_HPCOMR 0x04
+#define SNVS_HPCOMR_NPSWA_EN BIT(31)
+
+void init_snvs(void)
+{
+ u32 val;
+
+ /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
+ val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR);
+ val |= SNVS_HPCOMR_NPSWA_EN;
+ writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR);
+}
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index d349676b81..3ceeeffd99 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -18,6 +18,7 @@
#include <dm.h>
#include <imx_thermal.h>
#include <fsl_sec.h>
+#include <asm/setup.h>
#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
@@ -179,6 +180,8 @@ int arch_cpu_init(void)
isolate_resource();
#endif
+ init_snvs();
+
return 0;
}
@@ -201,6 +204,27 @@ int arch_misc_init(void)
#endif
#ifdef CONFIG_SERIAL_TAG
+/*
+ * OCOTP_TESTER
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * OCOTP_TESTER describes a unique ID based on silicon wafer
+ * and die X/Y position
+ *
+ * OCOTOP_TESTER offset 0x410
+ * 31:0 fuse 0
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ *
+ * OCOTP_TESTER1 offset 0x420
+ * 31:24 fuse 1
+ * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 23:16 fuse 1
+ * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 15:11 fuse 1
+ * The wafer number of the wafer on which the device was fabricated/SJC
+ * CHALLENGE/ Unique ID
+ * 10:0 fuse 1
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ */
void get_board_serial(struct tag_serialnr *serialnr)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;