diff options
Diffstat (limited to 'arch/arm/mach-keystone/ddr3.c')
| -rw-r--r-- | arch/arm/mach-keystone/ddr3.c | 35 |
1 files changed, 28 insertions, 7 deletions
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index ee8e12e878..4cad6a2d81 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -52,8 +52,7 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); - if (!cpu_is_k2g()) - __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); @@ -66,11 +65,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; if (cpu_is_k2g()) { - setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); - clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); + clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET, + phy_cfg->datx8_2_mask, + phy_cfg->datx8_2_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET, + phy_cfg->datx8_3_mask, + phy_cfg->datx8_3_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, + phy_cfg->datx8_4_mask, + phy_cfg->datx8_4_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, + phy_cfg->datx8_5_mask, + phy_cfg->datx8_5_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, + phy_cfg->datx8_6_mask, + phy_cfg->datx8_6_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, + phy_cfg->datx8_7_mask, + phy_cfg->datx8_7_val); + + clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, + phy_cfg->datx8_8_mask, + phy_cfg->datx8_8_val); } __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); |