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-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2e.h3
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2l.h3
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware.h50
-rw-r--r--arch/arm/mach-keystone/include/mach/psc_defs.h51
4 files changed, 72 insertions, 35 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h
index df499957e5..e6bc77caaf 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h
@@ -34,9 +34,6 @@
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 13
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
index a59e071359..92c17d7dd5 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
@@ -53,9 +53,6 @@
#define KS2_LPSC_FFTC_B 49
#define KS2_LPSC_IQN_AIL 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 14
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 8ca19bbcdb..38d019056a 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -215,16 +215,46 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#define KS2_MSMC_DATA_BASE 0x0c000000
-#ifndef CONFIG_SOC_K2G
-#define KS2_MSMC_SEGMENT_TETRIS 8
-#define KS2_MSMC_SEGMENT_NETCP 9
-#define KS2_MSMC_SEGMENT_QM_PDSP 10
-#define KS2_MSMC_SEGMENT_PCIE0 11
-#else
-#define KS2_MSMC_SEGMENT_TETRIS 1
-#define KS2_MSMC_SEGMENT_NETCP 4
-#define KS2_MSMC_SEGMENT_PCIE0 5
-#endif
+
+/* KS2 Generic Privilege ID Settings for MSMC2 */
+#define KS2_MSMC_SEGMENT_C6X_0 0
+#define KS2_MSMC_SEGMENT_C6X_1 1
+#define KS2_MSMC_SEGMENT_C6X_2 2
+#define KS2_MSMC_SEGMENT_C6X_3 3
+#define KS2_MSMC_SEGMENT_C6X_4 4
+#define KS2_MSMC_SEGMENT_C6X_5 5
+#define KS2_MSMC_SEGMENT_C6X_6 6
+#define KS2_MSMC_SEGMENT_C6X_7 7
+
+#define KS2_MSMC_SEGMENT_DEBUG 12
+
+/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
+#define K2HKLE_MSMC_SEGMENT_ARM 8
+#define K2HKLE_MSMC_SEGMENT_NETCP 9
+#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
+#define K2HKLE_MSMC_SEGMENT_PCIE0 11
+
+/* K2HK specific Privilege ID Settings */
+#define K2HKE_MSMC_SEGMENT_HYPERLINK 14
+
+/* K2L specific Privilege ID Settings */
+#define K2L_MSMC_SEGMENT_PCIE1 14
+
+/* K2E specific Privilege ID Settings */
+#define K2E_MSMC_SEGMENT_PCIE1 13
+#define K2E_MSMC_SEGMENT_TSIP 15
+
+/* K2G specific Privilege ID Settings */
+#define K2G_MSMC_SEGMENT_ARM 1
+#define K2G_MSMC_SEGMENT_ICSS0 2
+#define K2G_MSMC_SEGMENT_ICSS1 3
+#define K2G_MSMC_SEGMENT_NSS 4
+#define K2G_MSMC_SEGMENT_PCIE 5
+#define K2G_MSMC_SEGMENT_USB 6
+#define K2G_MSMC_SEGMENT_MLB 8
+#define K2G_MSMC_SEGMENT_PMMC 9
+#define K2G_MSMC_SEGMENT_DSS 10
+#define K2G_MSMC_SEGMENT_MMC 11
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h
index 6e6e7fd433..18499386a3 100644
--- a/arch/arm/mach-keystone/include/mach/psc_defs.h
+++ b/arch/arm/mach-keystone/include/mach/psc_defs.h
@@ -27,37 +27,50 @@
#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
-#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
- (u32)1)) << ((u32)y)))
-#define BOOT_READ_BITFIELD(z, x, y) ((((u32)z) & BOOTBITMASK(x, y)) >> (y))
-#define BOOT_SET_BITFIELD(z, f, x, y) ((((u32)z) & ~BOOTBITMASK(x, y)) | \
- ((((u32)f) << (y)) & BOOTBITMASK(x, y)))
+static inline u32 _boot_bit_mask(u32 x, u32 y)
+{
+ u32 val = (1 << (x - y + 1)) - 1;
+ return val << y;
+}
+
+static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y)
+{
+ u32 val = z & _boot_bit_mask(x, y);
+ return val >> y;
+}
+
+static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y)
+{
+ u32 mask = _boot_bit_mask(x, y);
+
+ return (z & ~mask) | ((f << y) & mask);
+}
/* PDCTL */
-#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
-#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
+#define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12)
/* PDSTAT */
-#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
+#define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0)
/* MDCFG */
-#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
-#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
+#define PSC_REG_MDCFG_GET_PD(x) boot_read_bitfield((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14)
/* MDCTL */
-#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
-#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
-#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
+#define PSC_REG_MDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y) boot_set_bitfield((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) boot_set_bitfield((x), (y), \
12, 12)
/* MDSTAT */
-#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
-#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
-#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10)
-#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11)
+#define PSC_REG_MDSTAT_GET_STATUS(x) boot_read_bitfield((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x) boot_read_bitfield((x), 9, 9)
+#define PSC_REG_MDSTAT_GET_MRSTZ(x) boot_read_bitfield((x), 10, 10)
+#define PSC_REG_MDSTAT_GET_MRSTDONE(x) boot_read_bitfield((x), 11, 11)
/* PDCTL states */
#define PSC_REG_VAL_PDCTL_NEXT_ON 1
generated by cgit (git 2.34.1) at 2025-01-13 07:55:59 +0000