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-rw-r--r--arch/arm/mach-keystone/Kconfig4
-rw-r--r--arch/arm/mach-keystone/Makefile1
-rw-r--r--arch/arm/mach-keystone/cmd_ddr3.c249
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-keystone/include/mach/mmc_host_def.h4
-rw-r--r--arch/arm/mach-keystone/init.c17
6 files changed, 25 insertions, 254 deletions
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index cababdba52..d24596eccb 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -7,16 +7,19 @@ choice
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
select SPL_BOARD_INIT if SPL
+ select CMD_DDR3
imply DM_I2C
config TARGET_K2G_EVM
@@ -24,6 +27,7 @@ config TARGET_K2G_EVM
select BOARD_LATE_INIT
select SPL_BOARD_INIT if SPL
select TI_I2C_BOARD_DETECT
+ select CMD_DDR3
imply DM_I2C
endchoice
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index 8253a3bcc1..3e076e12ec 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -13,7 +13,6 @@ ifndef CONFIG_SPL_BUILD
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += cmd_poweroff.o
-obj-y += cmd_ddr3.o
endif
obj-y += msmc.o
obj-y += ddr3.o
diff --git a/arch/arm/mach-keystone/cmd_ddr3.c b/arch/arm/mach-keystone/cmd_ddr3.c
deleted file mode 100644
index d3eab0711c..0000000000
--- a/arch/arm/mach-keystone/cmd_ddr3.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Keystone2: DDR3 test commands
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
-#define STACKSIZE (512 << 10) /* 512 KiB */
-
-#define DDR_REMAP_ADDR 0x80000000
-#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-
-#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
- STACKSIZE) >> 17) - 2)
-
-#define DDR_TEST_BURST_SIZE 1024
-
-static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
-{
- u32 index_start, value, index;
-
- index_start = start_address;
-
- while (1) {
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel(index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- if (quick)
- continue;
-
- /* Write a pattern for complementary values */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel((u32)~index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != ~index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2)
- __raw_writew((u16)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2) {
- value = __raw_readw(index);
- if (value != (u16)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readw(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1)
- __raw_writeb((u8)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1) {
- value = __raw_readb(index);
- if (value != (u8)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readb(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
- }
-
- puts("ddr memory test PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
-{
- u32 index, value, index2, value2;
-
- for (index = address1, index2 = address2;
- index < address1 + size;
- index += 4, index2 += 4) {
- value = __raw_readl(index);
- value2 = __raw_readl(index2);
-
- if (value != value2) {
- printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
- index, value, index2, value2);
-
- return -1;
- }
- }
-
- puts("ddr memory compare PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
-{
- u32 value1, value2, value3;
-
- puts("Disabling DDR ECC ...\n");
- ddr3_disable_ecc(base);
-
- value1 = __raw_readl(address);
- value2 = value1 ^ ecc_err;
- __raw_writel(value2, address);
-
- value3 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- address, value1, value2, ecc_err, value3);
-
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
- base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- puts("Enabling DDR ECC ...\n");
- ddr3_enable_ecc(base, 1);
-
- value1 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
-
- ddr3_check_ecc_int(base);
- return 0;
-}
-
-static int do_ddr_test(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- u32 start_addr, end_addr, size, ecc_err;
-
- if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
- if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
- puts("ECC RMW isn't supported for this SOC\n");
- return 1;
- }
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- ecc_err = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1))) {
- puts("Invalid address!\n");
- return cmd_usage(cmdtp);
- }
-
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
- start_addr, ecc_err);
- return 0;
- }
-
- if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
- ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
- return cmd_usage(cmdtp);
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- end_addr = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
- puts("Invalid start or end address!\n");
- return cmd_usage(cmdtp);
- }
-
- puts("Please wait ...\n");
- if (argc == 5) {
- size = simple_strtoul(argv[4], NULL, 16);
- ddr_memory_compare(start_addr, end_addr, size);
- } else {
- ddr_memory_test(start_addr, end_addr, 0);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
- "DDR3 test",
- "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
- " address to end address\n"
- "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
- " compare DDR data of (size) bytes from start address to end\n"
- " address\n"
- "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
- " in DDR data at <addr>, the command will read a 32-bit data\n"
- " from <addr>, and write (data ^ bit_err) back to <addr>\n"
-);
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 1969a10ab3..5d08418eb9 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -78,6 +78,7 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
#define KS2_DDR3A_DDRPHYC 0x02329000
+#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
@@ -326,6 +327,9 @@ typedef volatile unsigned int *dv_reg_p;
#define CPU_66AK2Lx 0xb9a7
#define CPU_66AK2Gx 0xbb06
+/* Variant definitions */
+#define CPU_66AK2G1x 0x08
+
/* DEVSPEED register */
#define DEVSPEED_DEVSPEED_SHIFT 16
#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
index a5050ac0f1..b8eed7d29b 100644
--- a/arch/arm/mach-keystone/include/mach/mmc_host_def.h
+++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
@@ -16,7 +16,7 @@
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x23000100
-#define OMAP_HSMMC2_BASE 0x23100100
+#define OMAP_HSMMC1_BASE 0x23000000
+#define OMAP_HSMMC2_BASE 0x23100000
#endif /* K2G_MMC_HOST_DEF_H */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 6e5a1e1af1..f9c03f1dd1 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -229,7 +229,19 @@ int print_cpuinfo(void)
puts("66AK2Ex SR");
break;
case CPU_66AK2Gx:
- puts("66AK2Gx SR");
+ puts("66AK2Gx");
+#ifdef CONFIG_SOC_K2G
+ {
+ int speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ puts("-100 ");
+ else if (speed == SPD600)
+ puts("-60 ");
+ else
+ puts("-xx ");
+ }
+#endif
+ puts("SR");
break;
default:
puts("Unknown\n");
@@ -241,7 +253,8 @@ int print_cpuinfo(void)
puts("1.1\n");
else if (rev == 0)
puts("1.0\n");
-
+ else if (rev == 8)
+ puts("1.0\n");
return 0;
}
#endif
generated by cgit (git 2.34.1) at 2025-01-16 10:03:35 +0000