1 files changed, 116 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index ea0cabad97..e1d4ddb44b 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -147,6 +147,16 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
+/*
+ * RTC only with DDR in self-refresh mode magic value, checked against during
+ * boot to see if we have a valid config. This should be in sync with the value
+ * that will be in drivers/soc/ti/pm33xx.c.
+ */
+#define RTC_MAGIC_VAL		0x8cd0
+
+/* Board type field bit shift for RTC only with DDR in self-refresh mode */
+#define RTC_BOARD_TYPE_SHIFT	16
+
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
@@ -252,6 +262,48 @@ int arch_misc_init(void)
 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
+static void rtc32k_unlock(struct davinci_rtc *rtc)
+{
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+/*
+ * Write contents of the RTC_SCRATCH1 register based on board type
+ * Two things are passed
+ * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
+ * control gets to kernel, kernel reads the scratchpad register and gets to
+ * know that bootloader has rtc_only support.
+ *
+ * Second important thing is the board type  (16:31). This is needed in the
+ * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
+ * identify the board type and we go ahead and copy the board strings to
+ * am43xx_board_name.
+ */
+void update_rtc_magic(void)
+{
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+	u32 magic = RTC_MAGIC_VAL;
+
+	magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
+
+	rtc32k_unlock(rtc);
+
+	/* write magic */
+	writel(magic, &rtc->scratch1);
+}
+#endif
+
 /*
  * In the case of non-SPL based booting we'll want to call these
  * functions a tiny bit later as it will require gd to be set and cleared
@@ -261,7 +313,9 @@ int board_early_init_f(void)
 {
 	prcm_init();
 	set_mux_conf_regs();
-
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+	update_rtc_magic();
+#endif
 	return 0;
 }
 
@@ -278,13 +332,7 @@ static void rtc32k_enable(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(RTC_KICK0R_WE, &rtc->kick0r);
-	writel(RTC_KICK1R_WE, &rtc->kick1r);
+	rtc32k_unlock(rtc);
 
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
@@ -321,8 +369,68 @@ static void watchdog_disable(void)
 		;
 }
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+/*
+ * Check if we are executing rtc-only + DDR mode, and resume from it if needed
+ */
+static void rtc_only(void)
+{
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+	struct prm_device_inst *prm_device =
+				(struct prm_device_inst *)PRM_DEVICE_INST;
+
+	u32 scratch1;
+	void (*resume_func)(void);
+
+	scratch1 = readl(&rtc->scratch1);
+
+	/*
+	 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
+	 * written to this register when we want to wake up from RTC only
+	 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
+	 * bits 0-15:  RTC_MAGIC_VAL
+	 * bits 16-31: board type (needed for sdram_init)
+	 */
+	if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
+		return;
+
+	rtc32k_unlock(rtc);
+
+	/* Clear RTC magic */
+	writel(0, &rtc->scratch1);
+
+	/*
+	 * Update board type based on value stored on RTC_SCRATCH1, this
+	 * is done so that we don't need to read the board type from eeprom
+	 * over i2c bus which is expensive
+	 */
+	rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
+
+	/*
+	 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
+	 * are resuming from self-refresh. This avoids an unnecessary re-init
+	 * of the DDR. The re-init takes time and we would need to wait for
+	 * it to complete before accessing DDR to avoid L3 NOC errors.
+	 */
+	writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
+
+	rtc_only_prcm_init();
+	sdram_init();
+
+	/* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
+	writel(0, &prm_device->emif_ctrl);
+
+	resume_func = (void *)readl(&rtc->scratch0);
+	if (resume_func)
+		resume_func();
+}
+#endif
+
 void s_init(void)
 {
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+	rtc_only();
+#endif
 }
 
 void early_system_init(void)