diff options
Diffstat (limited to 'arch/arm/mach-rockchip/rk3368')
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/Kconfig | 32 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/Makefile | 8 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/rk3368.c | 86 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 24 |
5 files changed, 182 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig new file mode 100644 index 0000000000..6d32068920 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -0,0 +1,32 @@ +if ROCKCHIP_RK3368 + +choice + prompt "RK3368 board" + +config TARGET_SHEEP + bool "Sheep board" + help + Sheep board is designed by Rockchip as a EVB board + for rk3368. + +config TARGET_GEEKBOX + bool "GeekBox" + +config TARGET_EVB_PX5 + bool "Evb-PX5" + help + PX5 EVB is designed by Rockchip for automotive field + with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS + HDMI video input/output interface, audio codec ES8396, + WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity + sensor STK3410. +endchoice + +config SYS_SOC + default "rockchip" + +source "board/rockchip/sheep_rk3368/Kconfig" +source "board/geekbuying/geekbox/Kconfig" +source "board/rockchip/evb_px5/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile new file mode 100644 index 0000000000..46798c2e93 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2016 Andreas Färber +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += clk_rk3368.o +obj-y += rk3368.o +obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c new file mode 100644 index 0000000000..2f98165e08 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.org> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3368_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3368_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c new file mode 100644 index 0000000000..fb829a4a37 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <syscon.h> + +#define IMEM_BASE 0xFF8C0000 + +/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ +#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) +#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) +/* exsram may using by mcu to accessing dram(0x0-0x20000000) */ +#define MCU_EXSRAM_BASE (0) +#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) +/* experi no used, reserved value = 0 */ +#define MCU_EXPERI_BASE (0) +#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) + +static struct mm_region rk3368_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3368_mem_map; + +#ifdef CONFIG_ARCH_EARLY_INIT_R +static int mcu_init(void) +{ + struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3368_cru *cru = rockchip_get_cru(); + + rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, + MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, + MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, + MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, + MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, + MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, + MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); + + rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, + (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | + (5 << MCU_CLK_DIV_SHIFT)); + + /* mcu dereset, for start running */ + rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); + + return 0; +} + +int arch_early_init_r(void) +{ + return mcu_init(); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c new file mode 100644 index 0000000000..03e97eb629 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3368_syscon_ids[] = { + { .compatible = "rockchip,rk3368-grf", + .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3368-pmugrf", + .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3368) = { + .name = "rk3368_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, +}; |