diff options
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 21 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3288-board.c | 39 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/Kconfig | 32 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/Makefile | 8 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/rk3368.c | 86 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 24 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3399-board-spl.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 19 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rv1108/Kconfig | 28 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rv1108/Makefile | 11 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rv1108/clk_rv1108.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rv1108/rv1108.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rv1108/syscon_rv1108.c | 21 |
15 files changed, 367 insertions, 11 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6be2ab5025..9b2ef2957d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -51,6 +51,18 @@ config ROCKCHIP_RK3328 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3368 + bool "Support Rockchip RK3368" + select ARM64 + select SYS_NS16550 + help + The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53. + including NEON and GPU, 512KB L2 cache for big cluster and 256 KB + L2 cache for little cluser, PowerVR G6110 based graphics, one video + output processor supporting LVDS、HDMI、eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 @@ -67,6 +79,13 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RV1108 + bool "Support Rockchip RV1108" + select CPU_V7 + help + The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 + and a DSP. + config ROCKCHIP_SPL_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 @@ -94,5 +113,7 @@ source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" +source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rv1108/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 327b26705d..87d201995e 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -31,4 +31,6 @@ endif obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9894a25e08..a354d992da 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -86,8 +86,10 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) + if (ret) { + debug("Cannot set regulator name\n"); return ret; + } /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); @@ -307,3 +309,38 @@ U_BOOT_CMD( "display information about clocks", "" ); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig new file mode 100644 index 0000000000..6d32068920 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -0,0 +1,32 @@ +if ROCKCHIP_RK3368 + +choice + prompt "RK3368 board" + +config TARGET_SHEEP + bool "Sheep board" + help + Sheep board is designed by Rockchip as a EVB board + for rk3368. + +config TARGET_GEEKBOX + bool "GeekBox" + +config TARGET_EVB_PX5 + bool "Evb-PX5" + help + PX5 EVB is designed by Rockchip for automotive field + with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS + HDMI video input/output interface, audio codec ES8396, + WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity + sensor STK3410. +endchoice + +config SYS_SOC + default "rockchip" + +source "board/rockchip/sheep_rk3368/Kconfig" +source "board/geekbuying/geekbox/Kconfig" +source "board/rockchip/evb_px5/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile new file mode 100644 index 0000000000..46798c2e93 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2016 Andreas Färber +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += clk_rk3368.o +obj-y += rk3368.o +obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c new file mode 100644 index 0000000000..2f98165e08 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.org> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3368_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3368_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c new file mode 100644 index 0000000000..fb829a4a37 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <syscon.h> + +#define IMEM_BASE 0xFF8C0000 + +/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ +#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) +#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) +/* exsram may using by mcu to accessing dram(0x0-0x20000000) */ +#define MCU_EXSRAM_BASE (0) +#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) +/* experi no used, reserved value = 0 */ +#define MCU_EXPERI_BASE (0) +#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) + +static struct mm_region rk3368_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3368_mem_map; + +#ifdef CONFIG_ARCH_EARLY_INIT_R +static int mcu_init(void) +{ + struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3368_cru *cru = rockchip_get_cru(); + + rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, + MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, + MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, + MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, + MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, + MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, + MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); + + rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, + (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | + (5 << MCU_CLK_DIV_SHIFT)); + + /* mcu dereset, for start running */ + rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); + + return 0; +} + +int arch_early_init_r(void) +{ + return mcu_init(); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c new file mode 100644 index 0000000000..03e97eb629 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3368_syscon_ids[] = { + { .compatible = "rockchip,rk3368-grf", + .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3368-pmugrf", + .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3368) = { + .name = "rk3368_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 050f5e167e..e050affac0 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -156,8 +156,6 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -#define SGRF_DDR_RGN_CON16 0xff330040 - void board_debug_uart_init(void) { #include <asm/arch/grf_rk3399.h> @@ -188,6 +186,8 @@ void board_debug_uart_init(void) } #define GRF_EMMCCORE_CON11 0xff77f02c +#define SGRF_DDR_RGN_CON16 0xff330040 +#define SGRF_SLV_SECURE_CON4 0xff33e3d0 void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -207,6 +207,7 @@ void board_init_f(ulong dummy) debug_uart_init(); printascii("U-Boot SPL board init"); #endif + /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); @@ -217,7 +218,7 @@ void board_init_f(ulong dummy) } /* - * Disable DDR security regions. + * Disable DDR and SRAM security regions. * * As we are entered from the BootROM, the region from * 0x0 through 0xfffff (i.e. the first MB of memory) will @@ -226,6 +227,7 @@ void board_init_f(ulong dummy) * located in this range. */ rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0); + rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000); secure_timer_init(); diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index a3ae8bd4f0..1b91bb1cdc 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -5,6 +5,7 @@ * * Adapted from coreboot. */ + #include <common.h> #include <clk.h> #include <dm.h> @@ -19,6 +20,7 @@ #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <linux/err.h> +#include <time.h> DECLARE_GLOBAL_DATA_PTR; struct chan_info { @@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; + const ulong timeout_ms = 200; /* * work around controller bug: @@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* Wating for PHY and DRAM init complete */ - tmp = 0; - while (!(readl(&denali_ctl[203]) & (1 << 3))) { - mdelay(10); - tmp++; - if (tmp > 10) + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("DRAM (%s): phy failed to lock within %ld ms\n", + __func__, timeout_ms); return -ETIME; - } + } + } while (!(readl(&denali_ctl[203]) & (1 << 3))); + debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit); @@ -1082,7 +1087,7 @@ static int sdram_init(struct dram_info *dram, debug("Starting SDRAM initialization...\n"); - if ((dramtype == DDR3 && ddr_freq > 800) || + if ((dramtype == DDR3 && ddr_freq > 933) || (dramtype == LPDDR3 && ddr_freq > 933) || (dramtype == LPDDR4 && ddr_freq > 800)) { debug("SDRAM frequency is to high!"); diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig new file mode 100644 index 0000000000..e6cba66578 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -0,0 +1,28 @@ +if ROCKCHIP_RV1108 + +config TARGET_EVB_RV1108 + bool "EVB_RV1108" + help + RV1108 EVB is a evaluation board for Rockchp RV1108. + + Key features of the board include: + * one macro USB OTG port + * one USB HOST port + * one RS232 to USB port route to UART2 as debug port + * MIPI screen with resolution 720 x 1280 + * 128M DDR3 + * 64M SPI Nor Flash + * macro SD card interface + * HDMI output + * 10/100 Mbps Ethernet + * camera interface compatible with imx323 / ov2710 / ov4689 + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +source board/rockchip/evb_rv1108/Kconfig + +endif diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile new file mode 100644 index 0000000000..9035a1a892 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += syscon_rv1108.o +endif +obj-y += rv1108.o +obj-y += clk_rv1108.o diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c new file mode 100644 index 0000000000..968c356447 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rv1108.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(clk_rv1108), devp); +} + +void *rockchip_get_cru(void) +{ + struct rv1108_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c new file mode 100644 index 0000000000..868cdd5a63 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c new file mode 100644 index 0000000000..8bb0ab89b8 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rv1108_syscon_ids[] = { + { .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rv1108) = { + .name = "rv1108_syscon", + .id = UCLASS_SYSCON, + .of_match = rv1108_syscon_ids, +}; |