diff options
Diffstat (limited to 'arch/arm/mach-rockchip')
26 files changed, 736 insertions, 269 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d9b25d5de4..967290f9a5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,14 +11,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3128 + bool "Support Rockchip RK3128" + select CPU_V7 + help + The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 select SPL_BOARD_INIT if SPL select SUPPORT_SPL - select SUPPORT_TPL select SPL - select TPL + select SPL_CLK + select SPL_PINCTRL + select SPL_REGMAP + select SPL_SYSCON + select SPL_RAM + select SPL_DRIVERS_MISC_SUPPORT + select SPL_ROCKCHIP_EARLYRETURN_TO_BROM select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -74,7 +88,6 @@ config ROCKCHIP_RK3368 imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT - select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT select SYS_NS16550 help @@ -112,8 +125,9 @@ config ROCKCHIP_RK3399 select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT - select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT + select BOARD_LATE_INIT + select ROCKCHIP_BROM_HELPER help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -149,9 +163,23 @@ config TPL_ROCKCHIP_BACK_TO_BROM SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_BOOT_MODE_REG + hex "Rockchip boot mode flag register address" + default 0x200081c8 if ROCKCHIP_RK3036 + default 0x20004040 if ROCKCHIP_RK3188 + default 0x110005c8 if ROCKCHIP_RK322X + default 0xff730094 if ROCKCHIP_RK3288 + default 0xff738200 if ROCKCHIP_RK3368 + default 0xff320300 if ROCKCHIP_RK3399 + default 0x10300580 if ROCKCHIP_RV1108 + default 0 + help + The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) + according to the value from this register. + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" - default 0x4000 + default 0 help SPL may need reserve memory for firmware loaded by SPL, whose load address is in IRAM and may overlay with SPL text area if not @@ -160,10 +188,39 @@ config ROCKCHIP_SPL_RESERVE_IRAM config ROCKCHIP_BROM_HELPER bool +config SPL_ROCKCHIP_EARLYRETURN_TO_BROM + bool "SPL requires early-return (for RK3188-style BROM) to BROM" + depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK + help + Some Rockchip BROM variants (e.g. on the RK3188) load the + first stage in segments and enter multiple times. E.g. on + the RK3188, the first 1KB of the first stage are loaded + first and entered; after returning to the BROM, the + remainder of the first stage is loaded, but the BROM + re-enters at the same address/to the same code as previously. + + This enables support code in the BOOT0 hook for the SPL stage + to allow multiple entries. + +config TPL_ROCKCHIP_EARLYRETURN_TO_BROM + bool "TPL requires early-return (for RK3188-style BROM) to BROM" + depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK + help + Some Rockchip BROM variants (e.g. on the RK3188) load the + first stage in segments and enter multiple times. E.g. on + the RK3188, the first 1KB of the first stage are loaded + first and entered; after returning to the BROM, the + remainder of the first stage is loaded, but the BROM + re-enters at the same address/to the same code as previously. + + This enables support code in the BOOT0 hook for the TPL stage + to allow multiple entries. + config SPL_MMC_SUPPORT default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index daafc8de6a..e1b0519b1f 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -8,10 +8,9 @@ # this may have entered from ATF with the stack-pointer pointing to # inaccessible/protected memory (and the bootrom-helper assumes that # the stack-pointer is valid before switching to the U-Boot stack). -obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o -obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o @@ -23,10 +22,19 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) + +# Always include boot_mode.o, as we bypass it (i.e. turn it off) +# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, +# we can have the preprocessor correctly recognise both 0x0 and 0 +# meaning "turn it off". +obj-y += boot_mode.o + obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o +obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o @@ -36,6 +44,7 @@ obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c new file mode 100644 index 0000000000..d7dd425aae --- /dev/null +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <adc.h> +#include <asm/io.h> +#include <asm/arch/boot_mode.h> + +#if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0) + +int setup_boot_mode(void) +{ + return 0; +} + +#else + +void set_back_to_bootrom_dnl_flag(void) +{ + writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); +} + +/* + * detect download key status by adc, most rockchip + * based boards use adc sample the download key status, + * but there are also some use gpio. So it's better to + * make this a weak function that can be override by + * some special boards. + */ +#define KEY_DOWN_MIN_VAL 0 +#define KEY_DOWN_MAX_VAL 30 + +__weak int rockchip_dnl_key_pressed(void) +{ + unsigned int val; + + if (adc_channel_single_shot("saradc", 1, &val)) { + pr_err("%s: adc_channel_single_shot fail!\n", __func__); + return false; + } + + if ((val >= KEY_DOWN_MIN_VAL) && (val <= KEY_DOWN_MAX_VAL)) + return true; + else + return false; +} + +void rockchip_dnl_mode_check(void) +{ + if (rockchip_dnl_key_pressed()) { + printf("download key pressed, entering download mode..."); + set_back_to_bootrom_dnl_flag(); + do_reset(NULL, 0, 0, NULL); + } +} + +int setup_boot_mode(void) +{ + void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG; + int boot_mode = readl(reg); + + rockchip_dnl_mode_check(); + + boot_mode = readl(reg); + debug("%s: boot mode 0x%08x\n", __func__, boot_mode); + + /* Clear boot mode */ + writel(BOOT_NORMAL, reg); + + switch (boot_mode) { + case BOOT_FASTBOOT: + debug("%s: enter fastboot!\n", __func__); + env_set("preboot", "setenv preboot; fastboot usb0"); + break; + case BOOT_UMS: + debug("%s: enter UMS!\n", __func__); + env_set("preboot", "setenv preboot; ums mmc 0"); + break; + } + + return 0; +} + +#endif diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 8380e4e006..bef2a90d1f 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -6,11 +6,104 @@ #include <common.h> #include <asm/arch/bootrom.h> +#include <asm/arch/boot_mode.h> +#include <asm/io.h> +#include <asm/setjmp.h> +#include <asm/system.h> -void back_to_bootrom(void) +/* + * Force the jmp_buf to the data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static jmp_buf brom_ctx __section(".data"); + +static void _back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd) +{ + longjmp(brom_ctx, brom_cmd); +} + +void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd) { #if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) puts("Returning to boot ROM...\n"); #endif - _back_to_bootrom_s(); + _back_to_bootrom(brom_cmd); +} + +/* + * we back to bootrom download mode if get a + * BOOT_BROM_DOWNLOAD flag in boot mode register + * + * note: the boot mode register is configured by + * application(next stage bootloader, kernel, etc), + * and the bootrom never check this register, so we need + * to check it and back to bootrom at very early bootstage(before + * some basic configurations(such as interrupts) been + * changed by TPL/SPL, as the bootrom download operation + * relys on many default settings(such as interrupts) by + * it's self. + */ +static bool check_back_to_brom_dnl_flag(void) +{ + u32 boot_mode; + + if (CONFIG_ROCKCHIP_BOOT_MODE_REG) { + boot_mode = readl(CONFIG_ROCKCHIP_BOOT_MODE_REG); + if (boot_mode == BOOT_BROM_DOWNLOAD) { + writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); + return true; + } + } + + return false; +} + +/* + * All Rockchip BROM implementations enter with a valid stack-pointer, + * so this can safely be implemented in C (providing a single + * implementation both for ARMv7 and AArch64). + */ +int save_boot_params(void) +{ + int ret = setjmp(brom_ctx); + + switch (ret) { + case 0: + if (check_back_to_brom_dnl_flag()) + _back_to_bootrom(BROM_BOOT_ENTER_DNL); + /* + * This is the initial pass through this function + * (i.e. saving the context), setjmp just setup up the + * brom_ctx: transfer back into the startup-code at + * 'save_boot_params_ret' and let the compiler know + * that this will not return. + */ + save_boot_params_ret(); + while (true) + /* does not return */; + break; + + case BROM_BOOT_NEXTSTAGE: + /* + * To instruct the BROM to boot the next stage, we + * need to return 0 to it: i.e. we need to rewrite + * the return code once more. + */ + ret = 0; + break; + case BROM_BOOT_ENTER_DNL: + /* + * A non-zero return value will instruct the BROM enter + * download mode. + */ + ret = 1; + break; + default: +#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) + puts("FATAL: unexpected command to back_to_bootrom()\n"); +#endif + hang(); + }; + + return ret; } diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py new file mode 100755 index 0000000000..7c6dd57678 --- /dev/null +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -0,0 +1,221 @@ +#!/usr/bin/env python2 +""" +A script to generate FIT image source for rockchip boards +with ARM Trusted Firmware +and multiple device trees (given on the command line) + +usage: $0 <dt_name> [<dt_name> [<dt_name] ...] +""" + +import os +import sys +import getopt + +# pip install pyelftools +from elftools.elf.elffile import ELFFile +from elftools.elf.sections import SymbolTableSection +from elftools.elf.segments import Segment, InterpSegment, NoteSegment + +ELF_SEG_P_TYPE='p_type' +ELF_SEG_P_PADDR='p_paddr' +ELF_SEG_P_VADDR='p_vaddr' +ELF_SEG_P_OFFSET='p_offset' +ELF_SEG_P_FILESZ='p_filesz' +ELF_SEG_P_MEMSZ='p_memsz' + +DT_HEADER="""/* + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * Minimal dts for a SPL FIT image payload. + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <0x%08x>; + }; +""" + +DT_IMAGES_NODE_END=""" + }; +""" + +DT_END=""" +}; +""" + +def append_atf_node(file, atf_index, phy_addr): + """ + Append ATF DT node to input FIT dts file. + """ + data = 'bl31_0x%08x.bin' % phy_addr + print >> file, '\t\tatf@%d {' % atf_index + print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";' + print >> file, '\t\t\tdata = /incbin/("%s");' % data + print >> file, '\t\t\ttype = "firmware";' + print >> file, '\t\t\tarch = "arm64";' + print >> file, '\t\t\tos = "arm-trusted-firmware";' + print >> file, '\t\t\tcompression = "none";' + print >> file, '\t\t\tload = <0x%08x>;' % phy_addr + if atf_index == 1: + print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr + print >> file, '\t\t};' + print >> file, '' + +def append_fdt_node(file, dtbs): + """ + Append FDT nodes. + """ + cnt = 1 + for dtb in dtbs: + dtname = os.path.basename(dtb) + print >> file, '\t\tfdt@%d {' % cnt + print >> file, '\t\t\tdescription = "%s";' % dtname + print >> file, '\t\t\tdata = /incbin/("%s");' % dtb + print >> file, '\t\t\ttype = "flat_dt";' + print >> file, '\t\t\tcompression = "none";' + print >> file, '\t\t};' + print >> file, '' + cnt = cnt + 1 + +def append_conf_section(file, cnt, dtname, atf_cnt): + print >> file, '\t\tconfig@%d {' % cnt + print >> file, '\t\t\tdescription = "%s";' % dtname + print >> file, '\t\t\tfirmware = "atf@1";' + print >> file, '\t\t\tloadables = "uboot@1",', + for i in range(1, atf_cnt): + print >> file, '"atf@%d"' % (i+1), + if i != (atf_cnt - 1): + print >> file, ',', + else: + print >> file, ';' + print >> file, '\t\t\tfdt = "fdt@1";' + print >> file, '\t\t};' + print >> file, '' + +def append_conf_node(file, dtbs, atf_cnt): + """ + Append configeration nodes. + """ + cnt = 1 + print >> file, '\tconfigurations {' + print >> file, '\t\tdefault = "config@1";' + for dtb in dtbs: + dtname = os.path.basename(dtb) + append_conf_section(file, cnt, dtname, atf_cnt) + cnt = cnt + 1 + print >> file, '\t};' + print >> file, '' + +def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name): + """ + Generate FIT script for ATF image. + """ + if fit_file_name != sys.stdout: + fit_file = open(fit_file_name, "wb") + else: + fit_file = sys.stdout + + num_load_seg = 0 + p_paddr = 0xFFFFFFFF + with open(uboot_file_name) as uboot_file: + uboot = ELFFile(uboot_file) + for i in range(uboot.num_segments()): + seg = uboot.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + p_paddr = seg.__getitem__(ELF_SEG_P_PADDR) + num_load_seg = num_load_seg + 1 + + assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1) + + print >> fit_file, DT_HEADER % p_paddr + + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + for i in range(bl31.num_segments()): + seg = bl31.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + paddr = seg.__getitem__(ELF_SEG_P_PADDR) + p= seg.__getitem__(ELF_SEG_P_PADDR) + append_atf_node(fit_file, i+1, paddr) + atf_cnt = i+1 + append_fdt_node(fit_file, dtbs_file_name) + print >> fit_file, '%s' % DT_IMAGES_NODE_END + append_conf_node(fit_file, dtbs_file_name, atf_cnt) + print >> fit_file, '%s' % DT_END + + if fit_file_name != sys.stdout: + fit_file.close() + +def generate_atf_binary(bl31_file_name): + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + + num = bl31.num_segments() + for i in range(num): + seg = bl31.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + paddr = seg.__getitem__(ELF_SEG_P_PADDR) + file_name = 'bl31_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(seg.data()); + +def get_bl31_segments_info(bl31_file_name): + """ + Get load offset, physical offset, file size + from bl31 elf file program headers. + """ + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + + num = bl31.num_segments() + print 'Number of Segments : %d' % bl31.num_segments() + for i in range(num): + print 'Segment %d' % i + seg = bl31.get_segment(i) + ptype = seg[ELF_SEG_P_TYPE] + poffset = seg[ELF_SEG_P_OFFSET] + pmemsz = seg[ELF_SEG_P_MEMSZ] + pfilesz = seg[ELF_SEG_P_FILESZ] + print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset) + paddr = seg[ELF_SEG_P_PADDR] + print 'paddr: %08x' % paddr + +def main(): + uboot_elf="./u-boot" + bl31_elf="./bl31.elf" + FIT_ITS=sys.stdout + + opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") + for opt, val in opts: + if opt == "-o": + FIT_ITS=val + elif opt == "-u": + uboot_elf=val + elif opt == "-b": + bl31_elf=val + elif opt == "-h": + print __doc__ + sys.exit(2) + + dtbs = args + #get_bl31_segments_info("u-boot") + #get_bl31_segments_info("bl31.elf") + + generate_atf_fit_dts(FIT_ITS, bl31_elf, uboot_elf, dtbs) + generate_atf_binary(bl31_elf); + +if __name__ == "__main__": + main() diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 9458201bd3..550e3a1521 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -40,7 +40,7 @@ void board_init_f(ulong dummy) sdram_init(); /* return to maskrom */ - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); } /* Place Holders */ diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index a3457f3914..a5d257168f 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -19,30 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define GRF_BASE 0x20008000 - -static void setup_boot_mode(void) -{ - struct rk3036_grf *const grf = (void *)GRF_BASE; - int boot_mode = readl(&grf->os_reg[4]); - - debug("boot mode %x.\n", boot_mode); - - /* Clear boot mode */ - writel(BOOT_NORMAL, &grf->os_reg[4]); - - switch (boot_mode) { - case BOOT_FASTBOOT: - printf("enter fastboot!\n"); - env_set("preboot", "setenv preboot; fastboot usb0"); - break; - case BOOT_UMS: - printf("enter UMS!\n"); - env_set("preboot", "setenv preboot; ums mmc 0"); - break; - } -} - __weak int rk_board_late_init(void) { return 0; diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 460dd6074e..e5393ec50a 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -34,10 +34,11 @@ struct rk3036_sdram_priv { struct rk3036_ddr_config ddr_config; }; -/* use integer mode, 396MHz dpll setting +/* + * use integer mode, dpll output 792MHz and ddr get 396MHz * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; +const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c, @@ -329,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) struct rk3036_pll *pll = &priv->cru->pll[1]; /* pll enter slow-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); /* use integer mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | dpll_init_cfg.fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | - dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) rockchip_udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORM << DPLL_MODE_SHIFT); } diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c new file mode 100644 index 0000000000..2e8393d70a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/grf_rk3128.h> +#include <asm/arch/boot_mode.h> +#include <asm/arch/timer.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return rk_board_late_init(); +} + +int board_init(void) +{ + int ret = 0; + + rockchip_timer_init(); + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0xe00000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + gd->ram_size - gd->bd->bi_dram[1].start; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3128_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3128-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3128-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3128_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) +int fb_set_reboot_flag(void) +{ + struct rk3128_grf *grf; + + printf("Setting reboot to fastboot flag ...\n"); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, &grf->os_reg[0]); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig new file mode 100644 index 0000000000..40655a22b5 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -0,0 +1,24 @@ +if ROCKCHIP_RK3128 + +choice + prompt "RK3128 board select" + +config TARGET_EVB_RK3128 + bool "RK3128 evaluation board" + select BOARD_LATE_INIT + help + RK3128evb is a evaluation board for Rockchip rk3128, + with full function and phisical connectors support like + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3128/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile new file mode 100644 index 0000000000..50e1117542 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3128.o +obj-y += syscon_rk3128.o +obj-y += clk_rk3128.o diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c new file mode 100644 index 0000000000..7ca5fd3484 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3128.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3128_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3128_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c new file mode 100644 index 0000000000..9d6e3b1ee1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c new file mode 100644 index 0000000000..0b636390ac --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3128_syscon_ids[] = { + { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3128) = { + .name = "rk3128_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3128_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 406207ed21..8e3b8ae3ba 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -101,7 +101,6 @@ static int setup_arm_clock(void) void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; - struct rk3188_pmu *pmu; int ret; /* Example code showing how to enable the debug UART on RK3188 */ @@ -145,15 +144,6 @@ void board_init_f(ulong dummy) return; } - /* - * Recover the bootrom's stackpointer. - * For whatever reason needs to run after rockchip_get_clk. - */ - pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - if (IS_ERR(pmu)) - pr_err("pmu syscon returned %ld\n", PTR_ERR(pmu)); - SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); @@ -168,7 +158,7 @@ void board_init_f(ulong dummy) setup_arm_clock(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif } @@ -229,7 +219,7 @@ void spl_board_init(void) preloader_console_init(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif return; diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c deleted file mode 100644 index b458ef6ea8..0000000000 --- a/arch/arm/mach-rockchip/rk3188-board-tpl.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <debug_uart.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/pmu_rk3188.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* track how often we were entered */ -static int rk3188_num_entries __attribute__ ((section(".data"))); - -#define PMU_BASE 0x20004000 -#define SPL_ENTRY 0x10080C00 - -static void jump_to_spl(void) -{ - typedef void __noreturn (*image_entry_noargs_t)(void); - - struct rk3188_pmu * const pmu = (void *)PMU_BASE; - image_entry_noargs_t tpl_entry = - (image_entry_noargs_t)(unsigned long)SPL_ENTRY; - - /* Store the SAVE_SP_ADDR in a location shared with SPL. */ - writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); - tpl_entry(); -} - -void board_init_f(ulong dummy) -{ - /* Example code showing how to enable the debug UART on RK3188 */ -#ifdef EARLY_UART -#include <asm/arch/grf_rk3188.h> - /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - - printch('t'); - printch('p'); - printch('l'); - printch('-'); - printch(rk3188_num_entries + 1 + '0'); - printch('\n'); -#endif - - rk3188_num_entries++; - - if (rk3188_num_entries == 1) { - /* - * The original loader did some very basic integrity - * checking at this point, but the remaining few bytes - * could be used for any improvement making sense - * really early on. - */ - - back_to_bootrom(); - } else { - /* - * TPL part of the loader should now wait for us - * at offset 0xC00 in the sram. Should never return - * from there. - */ - jump_to_spl(); - } -} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 96859a5b4b..916d18fc32 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -24,6 +24,7 @@ int board_late_init(void) { struct rk3188_grf *grf; + setup_boot_mode(); grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(grf)) { pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 4ddb8ba065..35f4f978c4 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -76,6 +76,6 @@ void board_init_f(ulong dummy) /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif } diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index d44311457a..e71847de87 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -16,30 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define GRF_BASE 0x11000000 - -static void setup_boot_mode(void) -{ - struct rk322x_grf *const grf = (void *)GRF_BASE; - int boot_mode = readl(&grf->os_reg[0]); - - debug("boot mode %x.\n", boot_mode); - - /* Clear boot mode */ - writel(BOOT_NORMAL, &grf->os_reg[0]); - - switch (boot_mode) { - case BOOT_FASTBOOT: - printf("enter fastboot!\n"); - env_set("preboot", "setenv preboot; fastboot usb0"); - break; - case BOOT_UMS: - printf("enter UMS!\n"); - env_set("preboot", "setenv preboot; ums mmc 0"); - break; - } -} - __weak int rk_board_late_init(void) { return 0; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 7b7fd5a6f1..f64a54843f 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -216,7 +216,7 @@ void board_init_f(ulong dummy) #endif #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif } @@ -283,7 +283,7 @@ void spl_board_init(void) preloader_console_init(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif return; err: diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c index 3d08b5b6d8..150beea02e 100644 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -69,7 +69,7 @@ void board_init_f(ulong dummy) void board_return_to_bootrom(void) { - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); } u32 spl_boot_device(void) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 278bb406f0..1c53ccabac 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -23,31 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define PMU_BASE 0xff730000 - -static void setup_boot_mode(void) -{ - struct rk3288_pmu *const pmu = (void *)PMU_BASE; - int boot_mode = readl(&pmu->sys_reg[0]); - - debug("boot mode %x.\n", boot_mode); - - /* Clear boot mode */ - writel(BOOT_NORMAL, &pmu->sys_reg[0]); - - switch (boot_mode) { - case BOOT_FASTBOOT: - printf("enter fastboot!\n"); - env_set("preboot", "setenv preboot; fastboot usb0"); - break; - case BOOT_UMS: - printf("enter UMS!\n"); - env_set("preboot", "setenv preboot; if mmc dev 0;" - "then ums mmc 0; else ums mmc 1;fi"); - break; - } -} - __weak int rk_board_late_init(void) { return 0; diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index b3e6ffa781..60d5aeade9 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -148,7 +148,7 @@ void board_init_f(ulong dummy) void board_return_to_bootrom(void) { - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); } u32 spl_boot_device(void) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 9c20f56dc9..b96903e70f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_return_to_bootrom(void) { - back_to_bootrom(); + back_to_bootrom(BROM_BOOT_NEXTSTAGE); } static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c new file mode 100644 index 0000000000..9293843538 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/boot_mode.h> + +int board_late_init(void) +{ + setup_boot_mode(); + return 0; +} diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S deleted file mode 100644 index 50fce207a5..0000000000 --- a/arch/arm/mach-rockchip/save_boot_param.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/linkage.h> - -#if defined(CONFIG_ARM64) -.globl SAVE_SP_ADDR -SAVE_SP_ADDR: - .quad 0 - -ENTRY(save_boot_params) - sub sp, sp, #0x60 - stp x29, x30, [sp, #0x50] - stp x27, x28, [sp, #0x40] - stp x25, x26, [sp, #0x30] - stp x23, x24, [sp, #0x20] - stp x21, x22, [sp, #0x10] - stp x19, x20, [sp, #0] - ldr x8, =SAVE_SP_ADDR - mov x9, sp - str x9, [x8] - b save_boot_params_ret /* back to my caller */ -ENDPROC(save_boot_params) - -.globl _back_to_bootrom_s -ENTRY(_back_to_bootrom_s) - ldr x0, =SAVE_SP_ADDR - ldr x0, [x0] - mov sp, x0 - ldp x29, x30, [sp, #0x50] - ldp x27, x28, [sp, #0x40] - ldp x25, x26, [sp, #0x30] - ldp x23, x24, [sp, #0x20] - ldp x21, x22, [sp, #0x10] - ldp x19, x20, [sp] - add sp, sp, #0x60 - mov x0, xzr - ret -ENDPROC(_back_to_bootrom_s) -#else -.globl SAVE_SP_ADDR -SAVE_SP_ADDR: - .word 0 - -/* - * void save_boot_params - * - * Save sp, lr, r1~r12 - */ -ENTRY(save_boot_params) - push {r1-r12, lr} - ldr r0, =SAVE_SP_ADDR - str sp, [r0] - b save_boot_params_ret @ back to my caller -ENDPROC(save_boot_params) - - -.globl _back_to_bootrom_s -ENTRY(_back_to_bootrom_s) - ldr r0, =SAVE_SP_ADDR - ldr sp, [r0] - mov r0, #0 - pop {r1-r12, pc} -ENDPROC(_back_to_bootrom_s) -#endif |