diff options
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager_gen5.c')
-rw-r--r-- | arch/arm/mach-socfpga/clock_manager_gen5.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 31fd51097a..4e5b6d1693 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h> #include <wait_bit.h> @@ -32,20 +33,18 @@ static void cm_write_ctrl(u32 val) } /* function to write a clock register that has phase information */ -static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) +static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask) { int ret; /* poll until phase is zero */ - ret = wait_for_bit(__func__, (const u32 *)reg_address, mask, - false, 20000, false); + ret = wait_for_bit_le32(reg_address, mask, false, 20000, false); if (ret) return ret; writel(value, reg_address); - return wait_for_bit(__func__, (const u32 *)reg_address, mask, - false, 20000, false); + return wait_for_bit_le32(reg_address, mask, false, 20000, false); } /* @@ -269,26 +268,26 @@ int cm_basic_init(const struct cm_config * const cfg) * are aligned nicely; so we can change any phase. */ ret = cm_write_with_phase(cfg->ddrdqsclk, - (u32)&clock_manager_base->sdr_pll.ddrdqsclk, + &clock_manager_base->sdr_pll.ddrdqsclk, CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); if (ret) return ret; /* SDRAM DDR2XDQSCLK */ ret = cm_write_with_phase(cfg->ddr2xdqsclk, - (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, + &clock_manager_base->sdr_pll.ddr2xdqsclk, CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->ddrdqclk, - (u32)&clock_manager_base->sdr_pll.ddrdqclk, + &clock_manager_base->sdr_pll.ddrdqclk, CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->s2fuser2clk, - (u32)&clock_manager_base->sdr_pll.s2fuser2clk, + &clock_manager_base->sdr_pll.s2fuser2clk, CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); if (ret) return ret; @@ -509,6 +508,14 @@ unsigned int cm_get_spi_controller_clk_hz(void) return clock; } +/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); |