diff options
Diffstat (limited to 'arch/arm/mach-stm32mp')
| -rw-r--r-- | arch/arm/mach-stm32mp/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 180 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 58 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/sys_proto.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/spl.c | 30 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/syscon.c | 23 |
7 files changed, 294 insertions, 24 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 8c755f8e64..8ca97bf0c9 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -16,6 +16,7 @@ config SPL select SPL_RESET_SUPPORT select SPL_SERIAL_SUPPORT select SPL_SYSCON + select SPL_DRIVERS_MISC_SUPPORT imply SPL_LIBDISK_SUPPORT config SYS_SOC @@ -26,6 +27,7 @@ config TARGET_STM32MP1 select CPU_V7 select PINCTRL_STM32 select STM32_RESET + select SYSRESET_SYSCON help target STMicroelectronics SOC STM32MP1 family STMicroelectronics MPU with core ARMv7 @@ -38,6 +40,14 @@ config SYS_TEXT_BASE when DDR driver is used: DDR + 1MB (0xC0100000) +config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 + hex "Partition on MMC2 to use to load U-Boot from" + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + default 1 + help + Partition on the second MMC to load U-Boot from when the MMC is being + used in raw mode + source "board/st/stm32mp1/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 4620869b36..a495c53be8 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -6,5 +6,6 @@ obj-y += cpu.o obj-y += dram_init.o +obj-y += syscon.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 7c43dc1294..f9f3bf9050 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -7,17 +7,19 @@ #include <clk.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <dm/uclass.h> -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) +#define RCC_DBGCFGR_DBGCKEN BIT(8) -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -/********************************************** - * Security init - *********************************************/ +/* Security register */ #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) @@ -30,13 +32,26 @@ void enable_caches(void) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_CR1_DBP BIT(8) -#define RCC_TZCR (STM32_RCC_BASE + 0x00) -#define RCC_BDCR (STM32_RCC_BASE + 0x0140) -#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 -#define RCC_BDCR_VSWRST BIT(31) -#define RCC_BDCR_RTCSRC GENMASK(17, 16) +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_PARAM_ADDR 0x2FFC0078 +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) static void security_init(void) { /* Disable the backup domain write protection */ @@ -93,15 +108,9 @@ static void security_init(void) writel(0x0, TAMP_CR1); } -/********************************************** +/* * Debug init - *********************************************/ -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) - + */ static void dbgmcu_init(void) { setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); @@ -111,6 +120,37 @@ static void dbgmcu_init(void) } #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ +static u32 get_bootmode(void) +{ + u32 boot_mode; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_device, bootrom_instance; + + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +#else + /* read TAMP backup register */ + boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; +#endif + return boot_mode; +} + +/* + * Early system init + */ int arch_cpu_init(void) { /* early armv7 timer init: needed for polling */ @@ -121,19 +161,111 @@ int arch_cpu_init(void) security_init(); #endif + /* get bootmode from BootRom context: saved in TAMP register */ + get_bootmode(); return 0; } +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +static u32 read_idc(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +u32 get_cpu_type(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: STM32MP15x\n"); + char *cpu_s, *cpu_r; + + switch (get_cpu_type()) { + case CPU_STMP32MP15x: + cpu_s = "15x"; + break; + default: + cpu_s = "?"; + break; + } + + switch (get_cpu_rev()) { + case CPU_REVA: + cpu_r = "A"; + break; + case CPU_REVB: + cpu_r = "B"; + break; + default: + cpu_r = "?"; + break; + } + + printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ -void reset_cpu(ulong addr) +static void setup_boot_mode(void) { + char cmd[60]; + u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); + u32 boot_mode = + (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; + int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + + pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n", + __func__, boot_ctx, boot_mode, instance); + + switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_SERIAL_UART: + sprintf(cmd, "%d", instance); + env_set("boot_device", "uart"); + env_set("boot_instance", cmd); + break; + case BOOT_SERIAL_USB: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + sprintf(cmd, "%d", instance); + env_set("boot_device", "mmc"); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_NAND: + env_set("boot_device", "nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_NOR: + env_set("boot_device", "nor"); + env_set("boot_instance", "0"); + break; + default: + pr_debug("unexpected boot mode = %x\n", boot_mode); + break; + } +} + +int arch_misc_init(void) +{ + setup_boot_mode(); + + return 0; } diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index ffbe0b1034..c7a27894c4 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -24,4 +24,62 @@ #define STM32_DDR_BASE 0xC0000000 #define STM32_DDR_SIZE SZ_1G +#ifndef __ASSEMBLY__ +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_STGEN, +}; + +/* + * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT + * - boot device = bit 8:4 + * - boot instance = bit 3:0 + */ +#define BOOT_TYPE_MASK 0xF0 +#define BOOT_TYPE_SHIFT 4 +#define BOOT_INSTANCE_MASK 0x0F +#define BOOT_INSTANCE_SHIFT 0 + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, +}; + +/* TAMP registers */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) + +#endif /* __ASSEMBLY__*/ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h new file mode 100644 index 0000000000..a8c20d1b2a --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#define CPU_STMP32MP15x 0x500 + +/* return CPU_STMP32MPxx constants */ +u32 get_cpu_type(void); + +#define CPU_REVA 0x1000 +#define CPU_REVB 0x2000 + +/* return CPU_REV constants */ +u32 get_cpu_rev(void); diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 8f5962a935..bfb3e50f67 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -7,9 +7,27 @@ #include <common.h> #include <dm.h> #include <spl.h> +#include <asm/io.h> u32 spl_boot_device(void) { + u32 boot_mode; + + boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); + + switch (boot_mode) { + case BOOT_FLASH_SD_1: + case BOOT_FLASH_EMMC_1: + return BOOT_DEVICE_MMC1; + case BOOT_FLASH_SD_2: + case BOOT_FLASH_EMMC_2: + return BOOT_DEVICE_MMC2; + } + return BOOT_DEVICE_MMC1; } @@ -18,6 +36,18 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } +int spl_boot_partition(const u32 boot_device) +{ + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION; + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2; + default: + return -EINVAL; + } +} + void board_init_f(ulong dummy) { struct udevice *dev; diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c new file mode 100644 index 0000000000..5641745931 --- /dev/null +++ b/arch/arm/mach-stm32mp/syscon.c @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/stm32.h> + +static const struct udevice_id stm32mp_syscon_ids[] = { + { .compatible = "st,stm32-stgen", + .data = STM32MP_SYSCON_STGEN }, + { } +}; + +U_BOOT_DRIVER(syscon_stm32mp) = { + .name = "stmp32mp_syscon", + .id = UCLASS_SYSCON, + .of_match = stm32mp_syscon_ids, + .bind = dm_scan_fdt_dev, +}; |