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-rw-r--r--arch/arm/mach-sunxi/Kconfig3
-rw-r--r--arch/arm/mach-sunxi/board.c9
-rw-r--r--arch/arm/mach-sunxi/clock_sun6i.c2
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h6.c78
4 files changed, 66 insertions, 26 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ffdf09f29e..16d41b83af 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -275,7 +275,10 @@ config MACH_SUN9I
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
+ select SPI
select DM_I2C
+ select DM_SPI if SPI
+ select DM_SPI_FLASH
select PHY_SUN4I_USB
select SUN6I_PRCM
select SUNXI_DE2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 8e9bb63d9d..db506367bf 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
+ __maybe_unused uint val;
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
@@ -139,6 +140,14 @@ static int gpio_init(void)
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
+#ifdef CONFIG_MACH_SUN50I_H6
+ /* Update PIO power bias configuration by copy hardware detected value */
+ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+#endif
+
return 0;
}
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 1628f3a7b6..6ca38f73d9 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
if (clk > 1152000000) {
k = 2;
} else if (clk > 768000000) {
- k = 3;
+ k = 4;
m = 2;
}
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 2a8275da3a..9375db76a1 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para)
u8 rows = para->rows;
u8 ranks = para->ranks;
+ if (!para->bus_full_width)
+ cols -= 1;
+
/* Ranks */
if (ranks == 2)
mctl_ctl->addrmap[0] = rows + cols - 3;
@@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para)
/* Columns */
mctl_ctl->addrmap[2] = 0;
switch (cols) {
+ case 7:
+ mctl_ctl->addrmap[3] = 0x1F1F1F00;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
case 8:
mctl_ctl->addrmap[3] = 0x1F1F0000;
mctl_ctl->addrmap[4] = 0x1F1F;
@@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para)
reg_val = 0x3f00;
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
- /* TODO: half DQ, DDR4 */
- reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
- MSTR_ACTIVE_RANKS(para->ranks);
+ /* TODO: DDR4 */
+ reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ if (para->bus_full_width)
+ reg_val |= MSTR_BUSWIDTH_FULL;
+ else
+ reg_val |= MSTR_BUSWIDTH_HALF;
writel(reg_val | BIT(31), &mctl_ctl->mstr);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
@@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para)
}
writel(reg_val, &mctl_ctl->odtcfg);
- /* TODO: half DQ */
+ if (!para->bus_full_width) {
+ writel(0x0, &mctl_phy->dx[2].gcr[0]);
+ writel(0x0, &mctl_phy->dx[3].gcr[0]);
+ }
}
static void mctl_bit_delay_set(struct dram_para *para)
@@ -514,22 +527,35 @@ static void mctl_channel_init(struct dram_para *para)
if (readl(&mctl_phy->pgsr[0]) & 0x400000)
{
- /*
- * Detect single rank.
- * TODO: also detect half DQ.
- */
+ /* Check for single rank and optionally half DQ. */
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
para->ranks = 1;
+
+ if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
+ (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
+ para->bus_full_width = 0;
+
/* Restart DRAM initialization from scratch. */
mctl_core_init(para);
return;
}
- else {
- panic("This DRAM setup is currently not supported.\n");
+
+ /*
+ * Check for dual rank and half DQ. NOTE: This combination
+ * is highly unlikely and was not tested. Condition is the
+ * same as in libdram, though.
+ */
+ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
+ para->bus_full_width = 0;
+
+ /* Restart DRAM initialization from scratch. */
+ mctl_core_init(para);
+ return;
}
+
+ panic("This DRAM setup is currently not supported.\n");
}
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
@@ -557,11 +583,8 @@ static void mctl_channel_init(struct dram_para *para)
static void mctl_auto_detect_dram_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
- /*
- * Detect rank number by the code in mctl_channel_init. Furtherly
- * when DQ detection is available it will also be executed there.
- */
+ /* TODO: non-(LP)DDR3 */
+ /* Detect rank number and half DQ by the code in mctl_channel_init. */
mctl_core_init(para);
/* detect row address bits */
@@ -570,8 +593,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->rows = 13; para->rows < 18; para->rows++) {
- /* 8 banks, 8 bit per byte and 32 bit width */
- if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
+ /* 8 banks, 8 bit per byte and 16/32 bit width */
+ if (mctl_mem_matches((1 << (para->rows + para->cols +
+ 4 + para->bus_full_width))))
break;
}
@@ -580,18 +604,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->cols = 8; para->cols < 11; para->cols++) {
- /* 8 bits per byte and 32 bit width */
- if (mctl_mem_matches(1 << (para->cols + 2)))
+ /* 8 bits per byte and 16/32 bit width */
+ if (mctl_mem_matches(1 << (para->cols + 1 +
+ para->bus_full_width)))
break;
}
}
unsigned long mctl_calc_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
+ u8 width = para->bus_full_width ? 4 : 2;
+
+ /* TODO: non-(LP)DDR3 */
- /* 8 banks, 32-bit (4 byte) data width */
- return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
+ /* 8 banks */
+ return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
}
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
@@ -625,6 +652,7 @@ unsigned long sunxi_dram_init(void)
.ranks = 2,
.cols = 11,
.rows = 14,
+ .bus_full_width = 1,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
generated by cgit (git 2.34.1) at 2025-02-11 16:19:30 +0000