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-rw-r--r--arch/arm/mach-uniphier/dram/Makefile16
-rw-r--r--arch/arm/mach-uniphier/dram/cmd_ddrphy.c168
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-ld4.c (renamed from arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c)3
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-regs.h14
-rw-r--r--arch/arm/mach-uniphier/dram/umc-ld4.c (renamed from arch/arm/mach-uniphier/dram/umc-ph1-ld4.c)4
-rw-r--r--arch/arm/mach-uniphier/dram/umc-pro4.c (renamed from arch/arm/mach-uniphier/dram/umc-ph1-pro4.c)4
-rw-r--r--arch/arm/mach-uniphier/dram/umc-pxs2.c (renamed from arch/arm/mach-uniphier/dram/umc-proxstream2.c)2
-rw-r--r--arch/arm/mach-uniphier/dram/umc-sld8.c (renamed from arch/arm/mach-uniphier/dram/umc-ph1-sld8.c)4
8 files changed, 122 insertions, 93 deletions
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 3d1553cbe1..615ba2cce9 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -4,14 +4,14 @@
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
- ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
+ ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
else
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index 078eb6f71b..7a9f76caeb 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -5,8 +5,11 @@
*/
#include <common.h>
+#include <mapmem.h>
#include <linux/io.h>
+#include <linux/sizes.h>
+#include "../soc-info.h"
#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
@@ -18,26 +21,45 @@
/* field separator */
#define FS " "
+static unsigned long uniphier_ld4_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
+static unsigned long uniphier_pro4_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
+static unsigned long uniphier_sld8_base[] = {
+ 0x5bc01000,
+ 0x5be01000,
+ 0 /* sentinel */
+};
+
static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
{
return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
}
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+static void dump_loop(unsigned long *base,
+ void (*callback)(struct ddrphy_datx8 __iomem *))
{
- int ch, p, dx;
struct ddrphy __iomem *phy;
+ int p, dx;
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+ for (p = 0; *base; base++, p++) {
+ phy = map_sysmem(*base, SZ_4K);
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- printf("CH%dP%dDX%d:", ch, p, dx);
- (*callback)(&phy->dx[dx]);
- printf("\n");
- }
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ printf("PHY%dDX%d:", p, dx);
+ (*callback)(&phy->dx[dx]);
+ printf("\n");
}
+
+ unmap_sysmem(phy);
}
}
@@ -51,12 +73,12 @@ static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
}
-static void wbdl_dump(void)
+static void wbdl_dump(unsigned long *base)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(&__wbdl_dump);
+ dump_loop(base, &__wbdl_dump);
}
static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
@@ -69,12 +91,12 @@ static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
}
-static void rbdl_dump(void)
+static void rbdl_dump(unsigned long *base)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
- dump_loop(&__rbdl_dump);
+ dump_loop(base, &__rbdl_dump);
}
static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
@@ -92,12 +114,12 @@ static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
}
}
-static void wld_dump(void)
+static void wld_dump(unsigned long *base)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__wld_dump);
+ dump_loop(base, &__wld_dump);
}
static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
@@ -114,12 +136,12 @@ static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
}
}
-static void dqsgd_dump(void)
+static void dqsgd_dump(unsigned long *base)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(&__dqsgd_dump);
+ dump_loop(base, &__dqsgd_dump);
}
static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
@@ -130,90 +152,106 @@ static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(void)
+static void mdl_dump(unsigned long *base)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
- dump_loop(&__mdl_dump);
+ dump_loop(base, &__mdl_dump);
}
#define REG_DUMP(x) \
{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
p - (u32 *)phy, #x, p, readl(p)); }
-static void reg_dump(void)
+static void reg_dump(unsigned long *base)
{
- int ch, p;
struct ddrphy __iomem *phy;
+ int p;
printf("\n--- DDR PHY registers ---\n");
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- printf("== Ch%d, PHY%d ==\n", ch, p);
- printf(" No: Name : Address : Data\n");
-
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
- }
+ for (p = 0; *base; base++, p++) {
+ phy = map_sysmem(*base, SZ_4K);
+
+ printf("== PHY%d (base: %p) ==\n", p, phy);
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(ridr);
+ REG_DUMP(pir);
+ REG_DUMP(pgcr[0]);
+ REG_DUMP(pgcr[1]);
+ REG_DUMP(pgsr[0]);
+ REG_DUMP(pgsr[1]);
+ REG_DUMP(pllcr);
+ REG_DUMP(ptr[0]);
+ REG_DUMP(ptr[1]);
+ REG_DUMP(ptr[2]);
+ REG_DUMP(ptr[3]);
+ REG_DUMP(ptr[4]);
+ REG_DUMP(acmdlr);
+ REG_DUMP(acbdlr);
+ REG_DUMP(dxccr);
+ REG_DUMP(dsgcr);
+ REG_DUMP(dcr);
+ REG_DUMP(dtpr[0]);
+ REG_DUMP(dtpr[1]);
+ REG_DUMP(dtpr[2]);
+ REG_DUMP(mr0);
+ REG_DUMP(mr1);
+ REG_DUMP(mr2);
+ REG_DUMP(mr3);
+ REG_DUMP(dx[0].gcr);
+ REG_DUMP(dx[0].gtr);
+ REG_DUMP(dx[1].gcr);
+ REG_DUMP(dx[1].gtr);
+
+ unmap_sysmem(phy);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
+ unsigned long *base;
+
+ switch (uniphier_get_soc_type()) {
+ case SOC_UNIPHIER_LD4:
+ base = uniphier_ld4_base;
+ break;
+ case SOC_UNIPHIER_PRO4:
+ base = uniphier_pro4_base;
+ break;
+ case SOC_UNIPHIER_SLD8:
+ base = uniphier_sld8_base;
+ break;
+ default:
+ printf("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
if (argc == 1)
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
+ wbdl_dump(base);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
+ rbdl_dump(base);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
+ wld_dump(base);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
+ dqsgd_dump(base);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
+ mdl_dump(base);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
+ reg_dump(base);
- return 0;
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
index eb9bf24da0..c9e164fc31 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
@@ -27,7 +27,8 @@ static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
+int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
+ bool ddr3plus)
{
enum dram_freq freq_e;
u32 tmp;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
index 87f6d0d3a2..a8fe6a08fb 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -158,19 +158,9 @@ struct ddrphy {
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-#define NR_DDRPHY_PER_CH 1
-#else
-#define NR_DDRPHY_PER_CH 2
-#endif
-
-#define NR_DDRCH 2
-
-#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
-
#ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus);
+int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
+ bool ddr3plus);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c
index 72447cc776..fc75864a10 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -152,7 +152,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
writel(0x00000101, dc_base + UMC_DIOCTLA);
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
@@ -164,7 +164,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
}
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
+int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c
index 23fb7b9f53..853f561cb2 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -142,7 +142,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
writel(0x00000100 | ((1 << (phy + 1)) - 1),
dc_base + UMC_DIOCTLA);
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
@@ -158,7 +158,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
ddr3plus);
}
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
+int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-pxs2.c
index 50c023825e..b4da3d26c2 100644
--- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c
+++ b/arch/arm/mach-uniphier/dram/umc-pxs2.c
@@ -598,7 +598,7 @@ static void um_init(void __iomem *um_base)
writel(0x000000ff, um_base + UMC_MBUS3);
}
-int proxstream2_umc_init(const struct uniphier_board_data *bd)
+int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5b600000;
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c
index 6cacd25e7c..e831766583 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -155,7 +155,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
writel(0x00000101, dc_base + UMC_DIOCTLA);
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
@@ -167,7 +167,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
}
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
+int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
generated by cgit (git 2.34.1) at 2025-01-27 21:06:32 +0000