7 files changed, 45 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 912e05a725..6c698a3922 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -1,5 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-y					+= sbc-boot.o
+
+ifndef CONFIG_SPL_BUILD
 obj-y					+= sbc.o
 
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= sbc-ld4.o
@@ -9,3 +12,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= sbc-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS3)	+= sbc-pxs2.o
+endif
diff --git a/arch/arm/mach-uniphier/sbc/sbc-boot.c b/arch/arm/mach-uniphier/sbc/sbc-boot.c
new file mode 100644
index 0000000000..ec22b453e0
--- /dev/null
+++ b/arch/arm/mach-uniphier/sbc/sbc-boot.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2011-2014 Panasonic Corporation
+// Copyright (C) 2015-2019 Socionext Inc.
+
+#include <linux/io.h>
+
+#include "sbc-regs.h"
+
+int uniphier_sbc_boot_is_swapped(void)
+{
+	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld11.c b/arch/arm/mach-uniphier/sbc/sbc-ld11.c
index 44d8a1e3bd..21972ac949 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ld11.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ld11.c
@@ -12,6 +12,9 @@
 
 void uniphier_ld11_sbc_init(void)
 {
+	if (!uniphier_sbc_is_enabled())
+		return;
+
 	uniphier_sbc_init_savepin();
 
 	/* necessary for ROM boot ?? */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ld4.c
index d08b571e23..72e9743c8f 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ld4.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ld4.c
@@ -13,6 +13,9 @@ void uniphier_ld4_sbc_init(void)
 {
 	u32 tmp;
 
+	if (!uniphier_sbc_is_enabled())
+		return;
+
 	uniphier_sbc_init_savepin();
 
 	/* system bus output enable */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
index 8c167ef069..3275f22ce9 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
@@ -10,6 +10,9 @@
 
 void uniphier_pxs2_sbc_init(void)
 {
+	if (!uniphier_sbc_is_enabled())
+		return;
+
 	uniphier_sbc_init_savepin();
 
 	/* necessary for ROM boot ?? */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h
index 853015acbc..1e9618653f 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-regs.h
+++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h
@@ -76,12 +76,7 @@
 
 #define PC0CTRL				0x598000c0
 
-#ifndef __ASSEMBLY__
-#include <linux/io.h>
-static inline int boot_is_swapped(void)
-{
-	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}
-#endif
+int uniphier_sbc_boot_is_swapped(void);
+int uniphier_sbc_is_enabled(void);
 
 #endif	/* ARCH_SBC_REGS_H */
diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c
index df01e5c01d..af8d6f4f9d 100644
--- a/arch/arm/mach-uniphier/sbc/sbc.c
+++ b/arch/arm/mach-uniphier/sbc/sbc.c
@@ -5,7 +5,9 @@
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
+#include <common.h>
 #include <linux/io.h>
+#include <asm/global_data.h>
 
 #include "../init.h"
 #include "sbc-regs.h"
@@ -31,6 +33,20 @@
 #define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
 #define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
 
+int uniphier_sbc_is_enabled(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	const void *fdt = gd->fdt_blob;
+	int offset;
+
+	offset = fdt_node_offset_by_compatible(fdt, 0,
+					       "socionext,uniphier-system-bus");
+	if (offset < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(fdt, offset);
+}
+
 static void __uniphier_sbc_init(int savepin)
 {
 	/*
@@ -48,7 +64,7 @@ static void __uniphier_sbc_init(int savepin)
 		writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
 	}
 
-	if (boot_is_swapped()) {
+	if (uniphier_sbc_boot_is_swapped()) {
 		/*
 		 * Boot Swap On: boot from external NOR/SRAM
 		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.