19 files changed, 306 insertions, 252 deletions

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index e256eeb668..e39ced674f 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -12,6 +12,7 @@ config ARCH_UNIPHIER_64BIT
 	select ARM64
 	select SPL_SEPARATE_BSS
 	select ARMV8_MULTIENTRY
+	select ARMV8_SPIN_TABLE
 
 choice
         prompt "UniPhier SoC select"
diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile
index 376c06b597..5074ebda97 100644
--- a/arch/arm/mach-uniphier/arm32/Makefile
+++ b/arch/arm/mach-uniphier/arm32/Makefile
@@ -7,7 +7,7 @@ obj-y += lowlevel_init.o
 obj-$(CONFIG_DEBUG_LL) += debug_ll.o
 else
 obj-y += late_lowlevel_init.o
-obj-y += cache_uniphier.o
+obj-y += cache-uniphier.o
 endif
 
 obj-y += timer.o
diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
new file mode 100644
index 0000000000..76fe5ebe09
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <asm/armv7.h>
+
+#include "ssc-regs.h"
+
+#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_sync(void)
+{
+	/* drain internal buffers */
+	writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
+	/* need a read back to confirm */
+	readl(UNIPHIER_SSCOPE);
+}
+
+static void uniphier_cache_maint_all(u32 operation)
+{
+	/* clear the complete notification flag */
+	writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
+
+	/* try until the command is successfully set */
+	do {
+		writel(UNIPHIER_SSCOQM_S_ALL | UNIPHIER_SSCOQM_CE | operation,
+		       UNIPHIER_SSCOQM);
+	} while (readl(UNIPHIER_SSCOPPQSEF) &
+		 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
+		;
+
+	uniphier_cache_sync();
+}
+
+void v7_outer_cache_flush_all(void)
+{
+	uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
+}
+
+void v7_outer_cache_inval_all(void)
+{
+	uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
+}
+
+static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
+{
+	/* clear the complete notification flag */
+	writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
+
+	/* try until the command is successfully set */
+	do {
+		writel(UNIPHIER_SSCOQM_S_RANGE | UNIPHIER_SSCOQM_CE | operation,
+		       UNIPHIER_SSCOQM);
+		writel(start, UNIPHIER_SSCOQAD);
+		writel(size, UNIPHIER_SSCOQSZ);
+
+	} while (readl(UNIPHIER_SSCOPPQSEF) &
+		 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
+		;
+}
+
+static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
+{
+	u32 size;
+
+	/*
+	 * If start address is not aligned to cache-line,
+	 * do cache operation for the first cache-line
+	 */
+	start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
+
+	size = end - start;
+
+	if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
+		/* this means cache operation for all range */
+		uniphier_cache_maint_all(operation);
+		return;
+	}
+
+	/*
+	 * If end address is not aligned to cache-line,
+	 * do cache operation for the last cache-line
+	 */
+	size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
+
+	while (size) {
+		u32 chunk_size = size > UNIPHIER_SSC_RANGE_OP_MAX_SIZE ?
+					UNIPHIER_SSC_RANGE_OP_MAX_SIZE : size;
+		__uniphier_cache_maint_range(start, chunk_size, operation);
+
+		start += chunk_size;
+		size -= chunk_size;
+	}
+
+	uniphier_cache_sync();
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+	if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
+		start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
+		__uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE,
+					     UNIPHIER_SSCOQM_CM_FLUSH);
+		start += UNIPHIER_SSC_LINE_SIZE;
+	}
+
+	if (start >= end) {
+		uniphier_cache_sync();
+		return;
+	}
+
+	if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
+		end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
+		__uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE,
+					     UNIPHIER_SSCOQM_CM_FLUSH);
+	}
+
+	if (start >= end) {
+		uniphier_cache_sync();
+		return;
+	}
+
+	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);
+}
+
+void v7_outer_cache_enable(void)
+{
+	u32 tmp;
+
+	writel(U32_MAX, UNIPHIER_SSCLPDAWCR);	/* activate all ways */
+	tmp = readl(UNIPHIER_SSCC);
+	tmp |= UNIPHIER_SSCC_ON;
+	writel(tmp, UNIPHIER_SSCC);
+}
+#endif
+
+void v7_outer_cache_disable(void)
+{
+	u32 tmp;
+
+	tmp = readl(UNIPHIER_SSCC);
+	tmp &= ~UNIPHIER_SSCC_ON;
+	writel(tmp, UNIPHIER_SSCC);
+}
+
+void enable_caches(void)
+{
+	dcache_enable();
+}
diff --git a/arch/arm/mach-uniphier/arm32/cache_uniphier.c b/arch/arm/mach-uniphier/arm32/cache_uniphier.c
deleted file mode 100644
index 4398114658..0000000000
--- a/arch/arm/mach-uniphier/arm32/cache_uniphier.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <asm/armv7.h>
-
-#include "ssc-regs.h"
-
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
-static void uniphier_cache_sync(void)
-{
-	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-	readl(SSCOPE); /* need a read back to confirm */
-}
-
-static void uniphier_cache_maint_all(u32 operation)
-{
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-
-	uniphier_cache_sync();
-}
-
-void v7_outer_cache_flush_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_INV);
-}
-
-static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
-{
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
-		writel(start, SSCOQAD);
-		writel(size, SSCOQSZ);
-
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-}
-
-static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-{
-	u32 size;
-
-	/*
-	 * If start address is not aligned to cache-line,
-	 * do cache operation for the first cache-line
-	 */
-	start = start & ~(SSC_LINE_SIZE - 1);
-
-	size = end - start;
-
-	if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
-		/* this means cache operation for all range */
-		uniphier_cache_maint_all(operation);
-		return;
-	}
-
-	/*
-	 * If end address is not aligned to cache-line,
-	 * do cache operation for the last cache-line
-	 */
-	size = ALIGN(size, SSC_LINE_SIZE);
-
-	while (size) {
-		u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
-						SSC_RANGE_OP_MAX_SIZE : size;
-		__uniphier_cache_maint_range(start, chunk_size, operation);
-
-		start += chunk_size;
-		size -= chunk_size;
-	}
-
-	uniphier_cache_sync();
-}
-
-void v7_outer_cache_flush_range(u32 start, u32 end)
-{
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_range(u32 start, u32 end)
-{
-	if (start & (SSC_LINE_SIZE - 1)) {
-		start &= ~(SSC_LINE_SIZE - 1);
-		__uniphier_cache_maint_range(start, SSC_LINE_SIZE,
-					     SSCOQM_CM_WB_INV);
-		start += SSC_LINE_SIZE;
-	}
-
-	if (start >= end) {
-		uniphier_cache_sync();
-		return;
-	}
-
-	if (end & (SSC_LINE_SIZE - 1)) {
-		end &= ~(SSC_LINE_SIZE - 1);
-		__uniphier_cache_maint_range(end, SSC_LINE_SIZE,
-					     SSCOQM_CM_WB_INV);
-	}
-
-	if (start >= end) {
-		uniphier_cache_sync();
-		return;
-	}
-
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
-}
-
-void v7_outer_cache_enable(void)
-{
-	u32 tmp;
-
-	writel(U32_MAX, SSCLPDAWCR);	/* activate all ways */
-	tmp = readl(SSCC);
-	tmp |= SSCC_ON;
-	writel(tmp, SSCC);
-}
-#endif
-
-void v7_outer_cache_disable(void)
-{
-	u32 tmp;
-	tmp = readl(SSCC);
-	tmp &= ~SSCC_ON;
-	writel(tmp, SSCC);
-}
-
-void enable_caches(void)
-{
-	dcache_enable();
-}
diff --git a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
index cce91dfac7..001d732e39 100644
--- a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
@@ -10,9 +10,9 @@
 #include "ssc-regs.h"
 
 ENTRY(lowlevel_init)
-	ldr	r1, = SSCC
+	ldr	r1, = UNIPHIER_SSCC
 	ldr	r0, [r1]
-	bic	r0, r0, #SSCC_ON	@ L2 disable
+	bic	r0, r0, #UNIPHIER_SSCC_ON	@ L2 disable
 	str	r0, [r1]
 	mov	pc, lr
 ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index cc34116baa..8e32b35723 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -94,26 +96,26 @@ ENTRY(setup_init_ram)
 	 */
 0:
 	/*
-	 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
+	 * set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order
 	 */
 	ldr	r0, = 0x00408006	@ touch to zero with address range
-	ldr	r1, = SSCOQM
+	ldr	r1, = UNIPHIER_SSCOQM
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_BASE
-	ldr	r1, = SSCOQAD
+	ldr	r1, = UNIPHIER_SSCOQAD
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_SIZE
-	ldr	r1, = SSCOQSZ
+	ldr	r1, = UNIPHIER_SSCOQSZ
 	str	r0, [r1]
 	ldr	r0, = BOOT_WAY_BITS
-	ldr	r1, = SSCOQWN
+	ldr	r1, = UNIPHIER_SSCOQWN
 	str	r0, [r1]
-	ldr	r1, = SSCOPPQSEF
+	ldr	r1, = UNIPHIER_SSCOPPQSEF
 	ldr	r0, [r1]
 	cmp	r0, #0			@ check if the command is successfully set
 	bne	0b			@ try again if an error occurs
 
-	ldr	r1, = SSCOLPQS
+	ldr	r1, = UNIPHIER_SSCOLPQS
 1:
 	ldr	r0, [r1]
 	cmp	r0, #0x4
diff --git a/arch/arm/mach-uniphier/arm32/ssc-regs.h b/arch/arm/mach-uniphier/arm32/ssc-regs.h
index 02fca3b6f6..8f423e92da 100644
--- a/arch/arm/mach-uniphier/arm32/ssc-regs.h
+++ b/arch/arm/mach-uniphier/arm32/ssc-regs.h
@@ -2,6 +2,7 @@
  * UniPhier System Cache (L2 Cache) registers
  *
  * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2016      Socionext Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,57 +10,59 @@
 #ifndef ARCH_SSC_REGS_H
 #define ARCH_SSC_REGS_H
 
-#define SSCC			0x500c0000
-#define SSCC_BST		(0x1 << 20)
-#define SSCC_ACT		(0x1 << 19)
-#define SSCC_WTG		(0x1 << 18)
-#define SSCC_PRD		(0x1 << 17)
-#define SSCC_WBWA		(0x1 << 16)
-#define SSCC_EX			(0x1 << 13)
-#define SSCC_ON			(0x1 <<  0)
+/* control registers */
+#define UNIPHIER_SSCC		0x500c0000	/* Control Register */
+#define    UNIPHIER_SSCC_BST			(0x1 << 20)	/* UCWG burst read */
+#define    UNIPHIER_SSCC_ACT			(0x1 << 19)	/* Inst-Data separate */
+#define    UNIPHIER_SSCC_WTG			(0x1 << 18)	/* WT gathering on */
+#define    UNIPHIER_SSCC_PRD			(0x1 << 17)	/* enable pre-fetch */
+#define    UNIPHIER_SSCC_ON			(0x1 <<  0)	/* enable cache */
+#define UNIPHIER_SSCLPDAWCR	0x500c0030	/* Unified/Data Active Way Control */
+#define UNIPHIER_SSCLPIAWCR	0x500c0034	/* Instruction Active Way Control */
 
-#define SSCLPDAWCR		0x500c0030
+/* revision registers */
+#define UNIPHIER_SSCID		0x503c0100	/* ID Register */
 
-#define SSCOPE			0x506c0244
-#define SSCOPE_CM_SYNC		0x00000008
+/* operation registers */
+#define UNIPHIER_SSCOPE		0x506c0244	/* Cache Operation Primitive Entry */
+#define    UNIPHIER_SSCOPE_CM_INV		0x0	/* invalidate */
+#define    UNIPHIER_SSCOPE_CM_CLEAN		0x1	/* clean */
+#define    UNIPHIER_SSCOPE_CM_FLUSH		0x2	/* flush */
+#define    UNIPHIER_SSCOPE_CM_SYNC		0x8	/* sync (drain bufs) */
+#define    UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH	0x9	/* flush p-fetch buf */
+#define UNIPHIER_SSCOQM		0x506c0248
+#define    UNIPHIER_SSCOQM_TID_MASK		(0x3 << 21)
+#define    UNIPHIER_SSCOQM_TID_LRU_DATA		(0x0 << 21)
+#define    UNIPHIER_SSCOQM_TID_LRU_INST		(0x1 << 21)
+#define    UNIPHIER_SSCOQM_TID_WAY		(0x2 << 21)
+#define    UNIPHIER_SSCOQM_S_MASK		(0x3 << 17)
+#define    UNIPHIER_SSCOQM_S_RANGE		(0x0 << 17)
+#define    UNIPHIER_SSCOQM_S_ALL		(0x1 << 17)
+#define    UNIPHIER_SSCOQM_S_WAY		(0x2 << 17)
+#define    UNIPHIER_SSCOQM_CE			(0x1 << 15)	/* notify completion */
+#define    UNIPHIER_SSCOQM_CW			(0x1 << 14)
+#define    UNIPHIER_SSCOQM_CM_MASK		(0x7)
+#define    UNIPHIER_SSCOQM_CM_INV		0x0	/* invalidate */
+#define    UNIPHIER_SSCOQM_CM_CLEAN		0x1	/* clean */
+#define    UNIPHIER_SSCOQM_CM_FLUSH		0x2	/* flush */
+#define    UNIPHIER_SSCOQM_CM_PREFETCH		0x3	/* prefetch to cache */
+#define    UNIPHIER_SSCOQM_CM_PREFETCH_BUF	0x4	/* prefetch to pf-buf */
+#define    UNIPHIER_SSCOQM_CM_TOUCH		0x5	/* touch */
+#define    UNIPHIER_SSCOQM_CM_TOUCH_ZERO	0x6	/* touch to zero */
+#define    UNIPHIER_SSCOQM_CM_TOUCH_DIRTY	0x7	/* touch with dirty */
+#define UNIPHIER_SSCOQAD	0x506c024c	/* Cache Operation Queue Address */
+#define UNIPHIER_SSCOQSZ	0x506c0250	/* Cache Operation Queue Size */
+#define UNIPHIER_SSCOQMASK	0x506c0254	/* Cache Operation Queue Address Mask */
+#define UNIPHIER_SSCOQWN	0x506c0258	/* Cache Operation Queue Way Number */
+#define UNIPHIER_SSCOPPQSEF	0x506c025c	/* Cache Operation Queue Set Complete */
+#define    UNIPHIER_SSCOPPQSEF_FE		(0x1 << 1)
+#define    UNIPHIER_SSCOPPQSEF_OE		(0x1 << 0)
+#define UNIPHIER_SSCOLPQS	0x506c0260	/* Cache Operation Queue Status */
+#define    UNIPHIER_SSCOLPQS_EF			(0x1 << 2)
+#define    UNIPHIER_SSCOLPQS_EST		(0x1 << 1)
+#define    UNIPHIER_SSCOLPQS_QST		(0x1 << 0)
 
-#define SSCOQM			0x506c0248
-#define SSCOQM_TID_MASK		(0x3 << 21)
-#define SSCOQM_TID_BY_WAY	(0x2 << 21)
-#define SSCOQM_TID_BY_INST_WAY	(0x1 << 21)
-#define SSCOQM_TID_BY_DATA_WAY	(0x0 << 21)
-#define SSCOQM_S_MASK		(0x3 << 17)
-#define SSCOQM_S_WAY		(0x2 << 17)
-#define SSCOQM_S_ALL		(0x1 << 17)
-#define SSCOQM_S_ADDRESS	(0x0 << 17)
-#define SSCOQM_CE		(0x1 << 15)
-#define SSCOQM_CW		(0x1 << 14)
-#define SSCOQM_CM_MASK		(0x7)
-#define SSCOQM_CM_DIRT_TOUCH	(0x7)
-#define SSCOQM_CM_ZERO_TOUCH	(0x6)
-#define SSCOQM_CM_NORM_TOUCH	(0x5)
-#define SSCOQM_CM_PREF_FETCH	(0x4)
-#define SSCOQM_CM_SSC_FETCH	(0x3)
-#define SSCOQM_CM_WB_INV	(0x2)
-#define SSCOQM_CM_WB		(0x1)
-#define SSCOQM_CM_INV		(0x0)
-
-#define SSCOQAD			0x506c024c
-#define SSCOQSZ			0x506c0250
-#define SSCOQWN			0x506c0258
-
-#define SSCOPPQSEF		0x506c025c
-#define SSCOPPQSEF_FE		(0x1 << 1)
-#define SSCOPPQSEF_OE		(0x1 << 0)
-
-#define SSCOLPQS		0x506c0260
-#define SSCOLPQS_EF		(0x1 << 2)
-#define SSCOLPQS_EST		(0x1 << 1)
-#define SSCOLPQS_QST		(0x1 << 0)
-
-#define SSCOQCE0		0x506c0270
-
-#define SSC_LINE_SIZE		128
-#define SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (SSC_LINE_SIZE))
+#define UNIPHIER_SSC_LINE_SIZE		128
+#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
 
 #endif  /* ARCH_SSC_REGS_H */
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
index 607f96a58d..f18595dc13 100644
--- a/arch/arm/mach-uniphier/arm64/arm-cci500.c
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -1,13 +1,12 @@
 /*
  * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
  *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -28,13 +27,13 @@ void cci500_init(unsigned int nr_slaves)
 		void __iomem *base;
 		u32 tmp;
 
-		base = map_sysmem(slave_base, SZ_4K);
+		base = ioremap(slave_base, SZ_4K);
 
 		tmp = readl(base);
 		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
 		writel(tmp, base);
 
-		unmap_sysmem(base);
+		iounmap(base);
 
 		slave_base += CCI500_SLAVE_OFFSET;
 	}
diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c
index 74ef91984c..67bc4f1209 100644
--- a/arch/arm/mach-uniphier/arm64/mem_map.c
+++ b/arch/arm/mach-uniphier/arm64/mem_map.c
@@ -10,14 +10,16 @@
 
 static struct mm_region uniphier_mem_map[] = {
 	{
-		.base = 0x00000000,
+		.virt = 0x00000000,
+		.phys = 0x00000000,
 		.size = 0x80000000,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{
-		.base = 0x80000000,
+		.virt = 0x80000000,
+		.phys = 0x80000000,
 		.size = 0xc0000000,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 5971ad256b..4f08963118 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
 
@@ -18,11 +17,11 @@ void uniphier_smp_kick_all_cpus(void)
 {
 	void __iomem *rom_boot_rsv0;
 
-	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
+	rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
 
 	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
 
-	unmap_sysmem(rom_boot_rsv0);
+	iounmap(rom_boot_rsv0);
 
 	uniphier_smp_setup();
 
diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c
index 4beab9dca8..c10903ae58 100644
--- a/arch/arm/mach-uniphier/arm64/timer.c
+++ b/arch/arm/mach-uniphier/arm64/timer.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -21,7 +20,7 @@ int timer_init(void)
 	void __iomem *base;
 	u32 tmp;
 
-	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
+	base = ioremap(CNT_CONTROL_BASE, SZ_4K);
 
 	/*
 	 * Note:
@@ -32,7 +31,7 @@ int timer_init(void)
 	tmp |= CNTCR_EN;
 	writel(tmp, base + CNTCR);
 
-	unmap_sysmem(base);
+	iounmap(base);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index ed308f3ecb..20093d8178 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -38,7 +39,6 @@ static const struct uniphier_board_data uniphier_sld3_data = {
 static const struct uniphier_board_data uniphier_ld4_data = {
 	.dram_freq = 1600,
 	.dram_nr_ch = 2,
-	.dram_ddr3plus = true,
 	.dram_ch[0] = {
 		.base = 0x80000000,
 		.size = 0x10000000,
@@ -49,6 +49,7 @@ static const struct uniphier_board_data uniphier_ld4_data = {
 		.size = 0x10000000,
 		.width = 16,
 	},
+	.flags = UNIPHIER_BD_DDR3PLUS,
 };
 #endif
 
@@ -90,7 +91,6 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = {
 static const struct uniphier_board_data uniphier_sld8_data = {
 	.dram_freq = 1333,
 	.dram_nr_ch = 2,
-	.dram_ddr3plus = true,
 	.dram_ch[0] = {
 		.base = 0x80000000,
 		.size = 0x10000000,
@@ -101,6 +101,7 @@ static const struct uniphier_board_data uniphier_sld8_data = {
 		.size = 0x10000000,
 		.width = 16,
 	},
+	.flags = UNIPHIER_BD_DDR3PLUS,
 };
 #endif
 
@@ -202,6 +203,22 @@ static const struct uniphier_board_data uniphier_ld20_data = {
 		.width = 32,
 	},
 };
+
+static const struct uniphier_board_data uniphier_ld21_data = {
+	.dram_freq = 1866,
+	.dram_nr_ch = 2,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[1] = {
+		.base = 0xc0000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.flags = UNIPHIER_BD_PACKAGE_LD21,
+};
 #endif
 
 struct uniphier_board_id {
@@ -237,6 +254,7 @@ static const struct uniphier_board_id uniphier_boards[] = {
 	{ "socionext,ph1-ld11", &uniphier_ld11_data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{ "socionext,ph1-ld21", &uniphier_ld21_data, },
 	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
 #endif
 };
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index 76bf856c9e..0d9240519c 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
@@ -32,12 +33,16 @@ void uniphier_pxs2_clk_init(void)
 	tmp |= SC_RSTCTRL2_NRST_USB3B1;
 	writel(tmp, SC_RSTCTRL2);
 	readl(SC_RSTCTRL2); /* dummy read */
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= 0x37;
+	writel(tmp, SC_RSTCTRL6);
 #endif
 
 	/* provide clocks */
 	tmp = readl(SC_CLKCTRL);
 #ifdef CONFIG_USB_XHCI_UNIPHIER
-	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+	tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
 		SC_CLKCTRL_CEN_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index 7a9f76caeb..0a5a73d8ee 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <mapmem.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
 
@@ -51,7 +52,7 @@ static void dump_loop(unsigned long *base,
 	int p, dx;
 
 	for (p = 0; *base; base++, p++) {
-		phy = map_sysmem(*base, SZ_4K);
+		phy = ioremap(*base, SZ_4K);
 
 		for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
 			printf("PHY%dDX%d:", p, dx);
@@ -59,7 +60,7 @@ static void dump_loop(unsigned long *base,
 			printf("\n");
 		}
 
-		unmap_sysmem(phy);
+		iounmap(phy);
 	}
 }
 
@@ -172,7 +173,7 @@ static void reg_dump(unsigned long *base)
 	printf("\n--- DDR PHY registers ---\n");
 
 	for (p = 0; *base; base++, p++) {
-		phy = map_sysmem(*base, SZ_4K);
+		phy = ioremap(*base, SZ_4K);
 
 		printf("== PHY%d (base: %p) ==\n", p, phy);
 		printf(" No: Name      : Address  : Data\n");
@@ -206,7 +207,7 @@ static void reg_dump(unsigned long *base)
 		REG_DUMP(dx[1].gcr);
 		REG_DUMP(dx[1].gtr);
 
-		unmap_sysmem(phy);
+		iounmap(phy);
 	}
 }
 
diff --git a/arch/arm/mach-uniphier/dram/umc-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c
index fc75864a10..1ea6193f88 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -175,7 +177,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
-				  bd->dram_ddr3plus, ch);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/dram/umc-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c
index 853f561cb2..f6c2d7f145 100644
--- a/arch/arm/mach-uniphier/dram/umc-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -170,7 +172,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
 				  bd->dram_ch[ch].width,
-				  bd->dram_ddr3plus);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS));
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/dram/umc-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c
index e831766583..61b1dc1a3a 100644
--- a/arch/arm/mach-uniphier/dram/umc-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -178,7 +180,7 @@ int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
-				  bd->dram_ddr3plus, ch);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index cba0bc9d37..db80074fc9 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -20,8 +21,11 @@ struct uniphier_dram_ch {
 struct uniphier_board_data {
 	unsigned int dram_freq;
 	unsigned int dram_nr_ch;
-	bool dram_ddr3plus;
 	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
+	unsigned int flags;
+#define UNIPHIER_BD_DDR3PLUS		BIT(2)
+#define UNIPHIER_BD_PACKAGE_LD21	1
+#define UNIPHIER_BD_PACKAGE_TYPE(f)	((f) & 0x3)
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void);
diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index a0955893ef..ad58e10e23 100644
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -1,7 +1,9 @@
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -68,6 +70,10 @@
 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
 
+#define SC_RSTCTRL5			(SC_BASE_ADDR | 0x2010)
+
+#define SC_RSTCTRL6			(SC_BASE_ADDR | 0x2014)
+
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */