diff options
Diffstat (limited to 'arch/arm')
107 files changed, 6845 insertions, 653 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0e38d3247b..eb6ce299f0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -664,6 +664,20 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select BINMAN + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family developed by MediaTek Inc. + Please refer to doc/README.mediatek for more information. + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -1450,6 +1464,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1935..c38ef3cb69 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S index 0d8b59eb6b..eae69e36c3 100644 --- a/arch/arm/cpu/armv7/smccc-call.S +++ b/arch/arm/cpu/armv7/smccc-call.S @@ -7,6 +7,8 @@ #include <asm/opcodes-sec.h> #include <asm/opcodes-virt.h> + .section .text.efi_runtime + #define UNWIND(x...) /* * Wrap c macros in asm macros to delay expansion until after the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 81edec01bf..0cb6dd39cc 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,6 +205,15 @@ ENTRY(cpu_init_cp15) mov r2, r3, lsl #4 @ shift variant field for combined value orr r2, r4, r2 @ r2 has combined CPU variant + revision +/* Early stack for ERRATA that needs into call C code */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) +#else + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) +#endif + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 + #ifdef CONFIG_ARM_ERRATA_798870 cmp r2, #0x30 @ Applies to lower than R3p0 bge skip_errata_798870 @ skip if not affected rev diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index ff42791fb4..1c12bbde75 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -96,6 +96,7 @@ endmenu config PSCI_RESET bool "Use PSCI for reset and shutdown" default y + select ARM_SMCCC if OF_CONTROL depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 0ba3dad8cc..9957c2974b 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <efi_loader.h> #include <version.h> #include <asm/macro.h> #include <asm/psci.h> @@ -19,7 +18,7 @@ * x0~x7: input arguments * x0~x3: output arguments */ -static void __efi_runtime hvc_call(struct pt_regs *args) +static void hvc_call(struct pt_regs *args) { asm volatile( "ldr x0, %0\n" @@ -53,7 +52,7 @@ static void __efi_runtime hvc_call(struct pt_regs *args) * x0~x3: output arguments */ -void __efi_runtime smc_call(struct pt_regs *args) +void smc_call(struct pt_regs *args) { asm volatile( "ldr x0, %0\n" @@ -83,9 +82,9 @@ void __efi_runtime smc_call(struct pt_regs *args) * use PSCI on U-Boot running below a hypervisor, please detect * this and set the flag accordingly. */ -static const __efi_runtime_data bool use_smc_for_psci = true; +static const bool use_smc_for_psci = true; -void __noreturn __efi_runtime psci_system_reset(void) +void __noreturn psci_system_reset(void) { struct pt_regs regs; @@ -100,7 +99,7 @@ void __noreturn __efi_runtime psci_system_reset(void) ; } -void __noreturn __efi_runtime psci_system_off(void) +void __noreturn psci_system_off(void) { struct pt_regs regs; @@ -114,44 +113,3 @@ void __noreturn __efi_runtime psci_system_off(void) while (1) ; } - -#ifdef CONFIG_CMD_POWEROFF -int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - puts("poweroff ...\n"); - - udelay(50000); /* wait 50 ms */ - - disable_interrupts(); - - psci_system_off(); - - /*NOTREACHED*/ - return 0; -} -#endif - -#ifdef CONFIG_PSCI_RESET -void reset_misc(void) -{ - psci_system_reset(); -} - -#ifdef CONFIG_EFI_LOADER -void __efi_runtime EFIAPI efi_reset_system( - enum efi_reset_type reset_type, - efi_status_t reset_status, - unsigned long data_size, void *reset_data) -{ - if (reset_type == EFI_RESET_COLD || - reset_type == EFI_RESET_WARM || - reset_type == EFI_RESET_PLATFORM_SPECIFIC) { - psci_system_reset(); - } else if (reset_type == EFI_RESET_SHUTDOWN) { - psci_system_off(); - } - - while (1) { } -} -#endif /* CONFIG_EFI_LOADER */ -#endif /* CONFIG_PSCI_RESET */ diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S index 16c9e298b4..86de4b4089 100644 --- a/arch/arm/cpu/armv8/smccc-call.S +++ b/arch/arm/cpu/armv8/smccc-call.S @@ -6,6 +6,8 @@ #include <linux/arm-smccc.h> #include <generated/asm-offsets.h> + .section .text.efi_runtime + .macro SMCCC instr .cfi_startproc \instr #0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ed810e8b74..c5960d3f92 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-p212.dtb \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ - meson-gxm-khadas-vim2.dtb + meson-gxm-khadas-vim2.dtb \ + meson-axg-s400.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -188,7 +189,8 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-icev2.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ - am335x-pdu001.dtb + am335x-pdu001.dtb \ + am335x-chiliboard.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ @@ -563,6 +565,10 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \ dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts new file mode 100644 index 0000000000..f939cf6406 --- /dev/null +++ b/arch/arm/dts/am335x-baltos.dts @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "OnRISC Baltos"; + compatible = "vscom,onrisc", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + >; + }; + + tps65910_pins: pinmux_tps65910_pins { + pinctrl-single,pins = < + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + + }; + tca6416_pins: pinmux_tca6416_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + boot@0 { + label = "SPL"; + reg = <0x0 0x20000>; + }; + boot@20000{ + label = "SPL.backup1"; + reg = <0x20000 0x20000>; + }; + boot@40000 { + label = "SPL.backup2"; + reg = <0x40000 0x20000>; + }; + boot@60000 { + label = "SPL.backup3"; + reg = <0x60000 0x20000>; + }; + boot@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + boot@260000 { + label = "UBI"; + reg = <0x260000 0xfda0000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <1000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi new file mode 100644 index 0000000000..4f9d308039 --- /dev/null +++ b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2018 Grinn Sp. z o.o. -- http://www.grinn-global.com/ + * Author: Marcin Niestroj <m.niestroj@grinn-global.com> + */ + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts new file mode 100644 index 0000000000..59431b2359 --- /dev/null +++ b/arch/arm/dts/am335x-chiliboard.dts @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy <lisovy@jablotron.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "am335x-chilisom.dtsi" + +/ { + model = "AM335x Chiliboard"; + compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", + "ti,am33xx"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_gpio_pins>; + + led0 { + label = "led0"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led1"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&am33xx_pinmux { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + /* mdio_clk.mdio_clk */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb1_drvvbus: usb1_drvvbus { + pinctrl-single,pins = < + AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + led_gpio_pins: led_gpio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&ldo4_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* Ethernet */ +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +/* USB */ +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_drvvbus>; + + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* microSD */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + vmmc-supply = <&ldo4_reg>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&tps { + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + charger { + status = "okay"; + }; + + pwrbutton { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi new file mode 100644 index 0000000000..1b43ebd08b --- /dev/null +++ b/arch/arm/dts/am335x-chilisom.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy <lisovy@jablotron.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am33xx.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Grinn AM335x ChiliSOM"; + compatible = "grinn,am335x-chilisom", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3d"; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&rtc { + system-power-controller; + + pinctrl-0 = <&ext_wakeup>; + pinctrl-names = "default"; + + ext_wakeup: ext-wakeup { + pins = "ext_wakeup0"; + input-enable; + }; +}; + +/* NAND Flash */ +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + }; +}; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index f912596c2c..7e8e2f707c 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -154,6 +154,12 @@ status = "okay"; }; +&cpm_mdio { + ge_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + &cpm_comphy { /* * CP0 Serdes Configuration: @@ -197,6 +203,16 @@ status = "okay"; }; +&cps_ethernet { + status = "okay"; +}; + +&cps_eth1 { + status = "okay"; + phy = <&ge_phy>; + phy-mode = "sgmii"; +}; + &cps_pinctl { /* * MPP Bus: diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi index 9bcfea6d86..bbbb9874c8 100644 --- a/arch/arm/dts/keystone-k2g.dtsi +++ b/arch/arm/dts/keystone-k2g.dtsi @@ -85,7 +85,7 @@ }; qspi: qspi@2940000 { - compatible = "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0x02940000 0x1000>, diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts new file mode 100644 index 0000000000..18778ada7b --- /dev/null +++ b/arch/arm/dts/meson-axg-s400.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-axg.dtsi" +#include <dt-bindings/input/input.h> + +/ { + compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; + model = "Amlogic Meson AXG S400 Development Board"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-next { + label = "Next"; + linux,code = <KEY_NEXT>; + press-threshold-microvolt = <1116000>; /* 62% */ + }; + + button-prev { + label = "Previous"; + linux,code = <KEY_PREVIOUS>; + press-threshold-microvolt = <900000>; /* 50% */ + }; + + button-wifi { + label = "Wifi"; + linux,code = <KEY_WLAN>; + press-threshold-microvolt = <684000>; /* 38% */ + }; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <468000>; /* 26% */ + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <252000>; /* 14% */ + }; + + button-voice { + label = "Voice"; + linux,code = <KEY_VOICECOMMAND>; + press-threshold-microvolt = <0>; /* 0% */ + }; + }; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + linein: audio-codec@0 { + #sound-dai-cells = <0>; + compatible = "everest,es7241"; + VDDA-supply = <&vcc_3v3>; + VDDP-supply = <&vcc_3v3>; + VDDD-supply = <&vcc_3v3>; + status = "okay"; + sound-name-prefix = "Linein"; + }; + + lineout: audio-codec@1 { + #sound-dai-cells = <0>; + compatible = "everest,es7154"; + VDD-supply = <&vcc_3v3>; + PVDD-supply = <&vcc_5v>; + status = "okay"; + sound-name-prefix = "Lineout"; + }; + + spdif_dit: audio-codec@2 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + dmics: audio-codec@3 { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <7>; + wakeup-delay-ms = <50>; + status = "okay"; + sound-name-prefix = "MIC"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + usb_pwr: regulator-usb_pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + speaker-leds { + compatible = "gpio-leds"; + + aled1 { + label = "speaker:aled1"; + gpios = <&gpio_speaker 7 0>; + }; + + aled2 { + label = "speaker:aled2"; + gpios = <&gpio_speaker 6 0>; + }; + + aled3 { + label = "speaker:aled3"; + gpios = <&gpio_speaker 5 0>; + }; + + aled4 { + label = "speaker:aled4"; + gpios = <&gpio_speaker 4 0>; + }; + + aled5 { + label = "speaker:aled5"; + gpios = <&gpio_speaker 3 0>; + }; + + aled6 { + label = "speaker:aled6"; + gpios = <&gpio_speaker 2 0>; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "AXG-S400"; + audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, + <&tdmin_lb>, <&tdmout_c>; + audio-widgets = "Line", "Lineout", + "Line", "Linein", + "Speaker", "Speaker1 Left", + "Speaker", "Speaker1 Right"; + audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "SPDIFOUT IN 0", "FRDDR_A OUT 3", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "SPDIFOUT IN 1", "FRDDR_B OUT 3", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "SPDIFOUT IN 2", "FRDDR_C OUT 3", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 2", "TDM_C Capture", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 2", "TDM_C Capture", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 2", "TDM_C Capture", + "TDMIN_C IN 5", "TDM_C Loopback", + "TDMIN_LB IN 2", "TDM_C Loopback", + "TDMIN_LB IN 5", "TDM_C Capture", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "TODDR_A IN 4", "PDM Capture", + "TODDR_B IN 4", "PDM Capture", + "TODDR_C IN 4", "PDM Capture", + "TODDR_A IN 6", "TDMIN_LB OUT", + "TODDR_B IN 6", "TDMIN_LB OUT", + "TODDR_C IN 6", "TDMIN_LB OUT", + "Lineout", "Lineout AOUTL", + "Lineout", "Lineout AOUTR", + "Speaker1 Left", "SPK1 OUT_A", + "Speaker1 Left", "SPK1 OUT_B", + "Speaker1 Right", "SPK1 OUT_C", + "Speaker1 Right", "SPK1 OUT_D", + "Linein AINL", "Linein", + "Linein AINR", "Linein"; + assigned-clocks = <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <589824000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link@0 { + sound-dai = <&frddr_a>; + }; + + dai-link@1 { + sound-dai = <&frddr_b>; + }; + + dai-link@2 { + sound-dai = <&frddr_c>; + }; + + dai-link@3 { + sound-dai = <&toddr_a>; + }; + + dai-link@4 { + sound-dai = <&toddr_b>; + }; + + dai-link@5 { + sound-dai = <&toddr_c>; + }; + + dai-link@6 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-rx-mask-1 = <1 1>; + mclk-fs = <256>; + + codec@0 { + sound-dai = <&lineout>; + }; + + codec@1 { + sound-dai = <&speaker_amp1>; + }; + + codec@2 { + sound-dai = <&linein>; + }; + + }; + + dai-link@7 { + sound-dai = <&spdifout>; + + codec { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link@8 { + sound-dai = <&pdm>; + + codec { + sound-dai = <&dmics>; + }; + }; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ + }; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_y_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_z_pins>; + pinctrl-names = "default"; + + speaker_amp1: audio-codec@1b { + compatible = "ti,tas5707"; + reg = <0x1b>; + reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcc_3v3>; + DVDD-supply = <&vcc_3v3>; + PVDD_A-supply = <&main_12v>; + PVDD_B-supply = <&main_12v>; + PVDD_C-supply = <&main_12v>; + PVDD_D-supply = <&main_12v>; + sound-name-prefix = "SPK1"; + }; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; + pinctrl-names = "default"; + + gpio_speaker: gpio-controller@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vddao_3v3>; + }; +}; + +&pdm { + pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, + <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_x20_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* wifi module */ +&sd_emmc_b { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "disabled"; + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <180000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&spdifout { + pinctrl-0 = <&spdif_out_a20_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_a { + pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, + <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_b { + pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, + <&tdmb_din3_pins>, <&mclk_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_c { + pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, + <&tdmc_din1_pins>, <&tdmc_dout2_pins>, + <&mclk_c_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmin_lb { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>; + pinctrl-names = "default"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi new file mode 100644 index 0000000000..df017dbd2e --- /dev/null +++ b/arch/arm/dts/meson-axg.dtsi @@ -0,0 +1,1589 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/clock/axg-aoclkc.h> +#include <dt-bindings/clock/axg-audio-clkc.h> +#include <dt-bindings/clock/axg-clkc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/meson-axg-gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> +#include <dt-bindings/reset/amlogic,meson-axg-reset.h> + +/ { + compatible = "amlogic,meson-axg"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + tdmif_a: audio-controller@0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller@1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller@2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + ao_alt_xtal: ao_alt_xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <32000000>; + clock-output-names = "ao_alt_xtal"; + #clock-cells = <0>; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + status = "disabled"; + }; + + pdm: audio-controller@ff632000 { + compatible = "amlogic,axg-pdm"; + reg = <0x0 0xff632000 0x0 0x34>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM"; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + status = "disabled"; + }; + + periphs: bus@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng@18 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x18 0x0 0x4>; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; + }; + + pinctrl_periphs: pinctrl@480 { + compatible = "amlogic,meson-axg-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@480 { + reg = <0x0 0x00480 0x0 0x40>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00520 0x0 0x14>, + <0x0 0x00430 0x0 0x3c>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 86>; + }; + + i2c0_pins: i2c0 { + mux { + groups = "i2c0_sck", + "i2c0_sda"; + function = "i2c0"; + }; + }; + + i2c1_x_pins: i2c1_x { + mux { + groups = "i2c1_sck_x", + "i2c1_sda_x"; + function = "i2c1"; + }; + }; + + i2c1_z_pins: i2c1_z { + mux { + groups = "i2c1_sck_z", + "i2c1_sda_z"; + function = "i2c1"; + }; + }; + + i2c2_a_pins: i2c2_a { + mux { + groups = "i2c2_sck_a", + "i2c2_sda_a"; + function = "i2c2"; + }; + }; + + i2c2_x_pins: i2c2_x { + mux { + groups = "i2c2_sck_x", + "i2c2_sda_x"; + function = "i2c2"; + }; + }; + + i2c3_a6_pins: i2c3_a6 { + mux { + groups = "i2c3_sda_a6", + "i2c3_sck_a7"; + function = "i2c3"; + }; + }; + + i2c3_a12_pins: i2c3_a12 { + mux { + groups = "i2c3_sda_a12", + "i2c3_sck_a13"; + function = "i2c3"; + }; + }; + + i2c3_a19_pins: i2c3_a19 { + mux { + groups = "i2c3_sda_a19", + "i2c3_sck_a20"; + function = "i2c3"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd", + "emmc_ds"; + function = "emmc"; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + + eth_rgmii_x_pins: eth-x-rgmii { + mux { + groups = "eth_mdio_x", + "eth_mdc_x", + "eth_rgmii_rx_clk_x", + "eth_rx_dv_x", + "eth_rxd0_x", + "eth_rxd1_x", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_x", + "eth_txd0_x", + "eth_txd1_x", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; + + eth_rgmii_y_pins: eth-y-rgmii { + mux { + groups = "eth_mdio_y", + "eth_mdc_y", + "eth_rgmii_rx_clk_y", + "eth_rx_dv_y", + "eth_rxd0_y", + "eth_rxd1_y", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_y", + "eth_txd0_y", + "eth_txd1_y", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; + + eth_rmii_x_pins: eth-x-rmii { + mux { + groups = "eth_mdio_x", + "eth_mdc_x", + "eth_rgmii_rx_clk_x", + "eth_rx_dv_x", + "eth_rxd0_x", + "eth_rxd1_x", + "eth_txen_x", + "eth_txd0_x", + "eth_txd1_x"; + function = "eth"; + }; + }; + + eth_rmii_y_pins: eth-y-rmii { + mux { + groups = "eth_mdio_y", + "eth_mdc_y", + "eth_rgmii_rx_clk_y", + "eth_rx_dv_y", + "eth_rxd0_y", + "eth_rxd1_y", + "eth_txen_y", + "eth_txd0_y", + "eth_txd1_y"; + function = "eth"; + }; + }; + + mclk_b_pins: mclk_b { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + mclk_c_pins: mclk_c { + mux { + groups = "mclk_c"; + function = "mclk_c"; + }; + }; + + pdm_dclk_a14_pins: pdm_dclk_a14 { + mux { + groups = "pdm_dclk_a14"; + function = "pdm"; + }; + }; + + pdm_dclk_a19_pins: pdm_dclk_a19 { + mux { + groups = "pdm_dclk_a19"; + function = "pdm"; + }; + }; + + pdm_din0_pins: pdm_din0 { + mux { + groups = "pdm_din0"; + function = "pdm"; + }; + }; + + pdm_din1_pins: pdm_din1 { + mux { + groups = "pdm_din1"; + function = "pdm"; + }; + }; + + pdm_din2_pins: pdm_din2 { + mux { + groups = "pdm_din2"; + function = "pdm"; + }; + }; + + pdm_din3_pins: pdm_din3 { + mux { + groups = "pdm_din3"; + function = "pdm"; + }; + }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + + spdif_in_z_pins: spdif_in_z { + mux { + groups = "spdif_in_z"; + function = "spdif_in"; + }; + }; + + spdif_in_a1_pins: spdif_in_a1 { + mux { + groups = "spdif_in_a1"; + function = "spdif_in"; + }; + }; + + spdif_in_a7_pins: spdif_in_a7 { + mux { + groups = "spdif_in_a7"; + function = "spdif_in"; + }; + }; + + spdif_in_a19_pins: spdif_in_a19 { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + spdif_in_a20_pins: spdif_in_a20 { + mux { + groups = "spdif_in_a20"; + function = "spdif_in"; + }; + }; + + spdif_out_a1_pins: spdif_out_a1 { + mux { + groups = "spdif_out_a1"; + function = "spdif_out"; + }; + }; + + spdif_out_a11_pins: spdif_out_a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + }; + }; + + spdif_out_a19_pins: spdif_out_a19 { + mux { + groups = "spdif_out_a19"; + function = "spdif_out"; + }; + }; + + spdif_out_a20_pins: spdif_out_a20 { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdif_out_z_pins: spdif_out_z { + mux { + groups = "spdif_out_z"; + function = "spdif_out"; + }; + }; + + spi0_pins: spi0 { + mux { + groups = "spi0_miso", + "spi0_mosi", + "spi0_clk"; + function = "spi0"; + }; + }; + + spi0_ss0_pins: spi0_ss0 { + mux { + groups = "spi0_ss0"; + function = "spi0"; + }; + }; + + spi0_ss1_pins: spi0_ss1 { + mux { + groups = "spi0_ss1"; + function = "spi0"; + }; + }; + + spi0_ss2_pins: spi0_ss2 { + mux { + groups = "spi0_ss2"; + function = "spi0"; + }; + }; + + spi1_a_pins: spi1_a { + mux { + groups = "spi1_miso_a", + "spi1_mosi_a", + "spi1_clk_a"; + function = "spi1"; + }; + }; + + spi1_ss0_a_pins: spi1_ss0_a { + mux { + groups = "spi1_ss0_a"; + function = "spi1"; + }; + }; + + spi1_ss1_pins: spi1_ss1 { + mux { + groups = "spi1_ss1"; + function = "spi1"; + }; + }; + + spi1_x_pins: spi1_x { + mux { + groups = "spi1_miso_x", + "spi1_mosi_x", + "spi1_clk_x"; + function = "spi1"; + }; + }; + + spi1_ss0_x_pins: spi1_ss0_x { + mux { + groups = "spi1_ss0_x"; + function = "spi1"; + }; + }; + + tdma_din0_pins: tdma_din0 { + mux { + groups = "tdma_din0"; + function = "tdma"; + }; + }; + + tdma_dout0_x14_pins: tdma_dout0_x14 { + mux { + groups = "tdma_dout0_x14"; + function = "tdma"; + }; + }; + + tdma_dout0_x15_pins: tdma_dout0_x15 { + mux { + groups = "tdma_dout0_x15"; + function = "tdma"; + }; + }; + + tdma_dout1_pins: tdma_dout1 { + mux { + groups = "tdma_dout1"; + function = "tdma"; + }; + }; + + tdma_din1_pins: tdma_din1 { + mux { + groups = "tdma_din1"; + function = "tdma"; + }; + }; + + tdma_fs_pins: tdma_fs { + mux { + groups = "tdma_fs"; + function = "tdma"; + }; + }; + + tdma_fs_slv_pins: tdma_fs_slv { + mux { + groups = "tdma_fs_slv"; + function = "tdma"; + }; + }; + + tdma_sclk_pins: tdma_sclk { + mux { + groups = "tdma_sclk"; + function = "tdma"; + }; + }; + + tdma_sclk_slv_pins: tdma_sclk_slv { + mux { + groups = "tdma_sclk_slv"; + function = "tdma"; + }; + }; + + tdmb_din0_pins: tdmb_din0 { + mux { + groups = "tdmb_din0"; + function = "tdmb"; + }; + }; + + tdmb_din1_pins: tdmb_din1 { + mux { + groups = "tdmb_din1"; + function = "tdmb"; + }; + }; + + tdmb_din2_pins: tdmb_din2 { + mux { + groups = "tdmb_din2"; + function = "tdmb"; + }; + }; + + tdmb_din3_pins: tdmb_din3 { + mux { + groups = "tdmb_din3"; + function = "tdmb"; + }; + }; + + tdmb_dout0_pins: tdmb_dout0 { + mux { + groups = "tdmb_dout0"; + function = "tdmb"; + }; + }; + + tdmb_dout1_pins: tdmb_dout1 { + mux { + groups = "tdmb_dout1"; + function = "tdmb"; + }; + }; + + tdmb_dout2_pins: tdmb_dout2 { + mux { + groups = "tdmb_dout2"; + function = "tdmb"; + }; + }; + + tdmb_dout3_pins: tdmb_dout3 { + mux { + groups = "tdmb_dout3"; + function = "tdmb"; + }; + }; + + tdmb_fs_pins: tdmb_fs { + mux { + groups = "tdmb_fs"; + function = "tdmb"; + }; + }; + + tdmb_fs_slv_pins: tdmb_fs_slv { + mux { + groups = "tdmb_fs_slv"; + function = "tdmb"; + }; + }; + + tdmb_sclk_pins: tdmb_sclk { + mux { + groups = "tdmb_sclk"; + function = "tdmb"; + }; + }; + + tdmb_sclk_slv_pins: tdmb_sclk_slv { + mux { + groups = "tdmb_sclk_slv"; + function = "tdmb"; + }; + }; + + tdmc_fs_pins: tdmc_fs { + mux { + groups = "tdmc_fs"; + function = "tdmc"; + }; + }; + + tdmc_fs_slv_pins: tdmc_fs_slv { + mux { + groups = "tdmc_fs_slv"; + function = "tdmc"; + }; + }; + + tdmc_sclk_pins: tdmc_sclk { + mux { + groups = "tdmc_sclk"; + function = "tdmc"; + }; + }; + + tdmc_sclk_slv_pins: tdmc_sclk_slv { + mux { + groups = "tdmc_sclk_slv"; + function = "tdmc"; + }; + }; + + tdmc_din0_pins: tdmc_din0 { + mux { + groups = "tdmc_din0"; + function = "tdmc"; + }; + }; + + tdmc_din1_pins: tdmc_din1 { + mux { + groups = "tdmc_din1"; + function = "tdmc"; + }; + }; + + tdmc_din2_pins: tdmc_din2 { + mux { + groups = "tdmc_din2"; + function = "tdmc"; + }; + }; + + tdmc_din3_pins: tdmc_din3 { + mux { + groups = "tdmc_din3"; + function = "tdmc"; + }; + }; + + tdmc_dout0_pins: tdmc_dout0 { + mux { + groups = "tdmc_dout0"; + function = "tdmc"; + }; + }; + + tdmc_dout1_pins: tdmc_dout1 { + mux { + groups = "tdmc_dout1"; + function = "tdmc"; + }; + }; + + tdmc_dout2_pins: tdmc_dout2 { + mux { + groups = "tdmc_dout2"; + function = "tdmc"; + }; + }; + + tdmc_dout3_pins: tdmc_dout3 { + mux { + groups = "tdmc_dout3"; + function = "tdmc"; + }; + }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + uart_b_x_pins: uart_b_x { + mux { + groups = "uart_tx_b_x", + "uart_rx_b_x"; + function = "uart_b"; + }; + }; + + uart_b_x_cts_rts_pins: uart_b_x_cts_rts { + mux { + groups = "uart_cts_b_x", + "uart_rts_b_x"; + function = "uart_b"; + }; + }; + + uart_b_z_pins: uart_b_z { + mux { + groups = "uart_tx_b_z", + "uart_rx_b_z"; + function = "uart_b"; + }; + }; + + uart_b_z_cts_rts_pins: uart_b_z_cts_rts { + mux { + groups = "uart_cts_b_z", + "uart_rts_b_z"; + function = "uart_b"; + }; + }; + + uart_ao_b_z_pins: uart_ao_b_z { + mux { + groups = "uart_ao_tx_b_z", + "uart_ao_rx_b_z"; + function = "uart_ao_b_z"; + }; + }; + + uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { + mux { + groups = "uart_ao_cts_b_z", + "uart_ao_rts_b_z"; + function = "uart_ao_b_z"; + }; + }; + }; + }; + + hiubus: bus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x1c00>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; + + sysctrl: system-controller@0 { + compatible = "amlogic,meson-axg-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,axg-clkc"; + #clock-cells = <1>; + }; + }; + }; + + mailbox: mailbox@ff63dc00 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0xff63dc00 0 0x400>; + interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + toddr_a: audio-controller@100 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x100 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_A"; + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_A>; + resets = <&arb AXG_ARB_TODDR_A>; + status = "disabled"; + }; + + toddr_b: audio-controller@140 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x140 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_B"; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_B>; + resets = <&arb AXG_ARB_TODDR_B>; + status = "disabled"; + }; + + toddr_c: audio-controller@180 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x180 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_C"; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_C>; + resets = <&arb AXG_ARB_TODDR_C>; + status = "disabled"; + }; + + frddr_a: audio-controller@1c0 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x1c0 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_A"; + interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + resets = <&arb AXG_ARB_FRDDR_A>; + status = "disabled"; + }; + + frddr_b: audio-controller@200 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x200 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_B"; + interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; + resets = <&arb AXG_ARB_FRDDR_B>; + status = "disabled"; + }; + + frddr_c: audio-controller@240 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x240 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_C"; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; + resets = <&arb AXG_ARB_FRDDR_C>; + status = "disabled"; + }; + + arb: reset-controller@280 { + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + }; + + aobus: bus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + sysctrl_AO: sys-ctrl@0 { + compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; + reg = <0x0 0x0 0x0 0x100>; + + clkc_AO: clock-controller { + compatible = "amlogic,meson-axg-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-axg-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 15>; + }; + + i2c_ao_sck_4_pins: i2c_ao_sck_4 { + mux { + groups = "i2c_ao_sck_4"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sck_8_pins: i2c_ao_sck_8 { + mux { + groups = "i2c_ao_sck_8"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sck_10_pins: i2c_ao_sck_10 { + mux { + groups = "i2c_ao_sck_10"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_5_pins: i2c_ao_sda_5 { + mux { + groups = "i2c_ao_sda_5"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_9_pins: i2c_ao_sda_9 { + mux { + groups = "i2c_ao_sda_9"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_11_pins: i2c_ao_sda_11 { + mux { + groups = "i2c_ao_sda_11"; + function = "i2c_ao"; + }; + }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_ao_tx_a", + "uart_ao_rx_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { + mux { + groups = "uart_ao_cts_a", + "uart_ao_rts_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_b_pins: uart_ao_b { + mux { + groups = "uart_ao_tx_b", + "uart_ao_rx_b"; + function = "uart_ao_b"; + }; + }; + + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { + mux { + groups = "uart_ao_cts_b", + "uart_ao_rts_b"; + function = "uart_ao_b"; + }; + }; + }; + + sec_AO: ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x05000 0x0 0x20>; + interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_AO_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8000 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8000 0x0 0x20>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + saradc: adc@9000 { + compatible = "amlogic,meson-axg-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x9000 0x0 0x38>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_SAR_ADC>, + <&clkc_AO CLKID_AO_SAR_ADC_CLK>, + <&clkc_AO CLKID_AO_SAR_ADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x25000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; + + reset: reset-controller@1004 { + compatible = "amlogic,meson-axg-reset"; + reg = <0x0 0x01004 0x0 0x9c>; + #reset-cells = <1>; + }; + + gpio_intc: interrupt-controller@f080 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x0 0xf080 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + spicc0: spi@13000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x13000 0x0 0x3c>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_SPICC0>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@15000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x15000 0x0 0x3c>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_SPICC1>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1c000 0x0 0x20>; + interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1d000 0x0 0x20>; + interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1e000 0x0 0x20>; + interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1f000 0x0 0x20>; + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x23000 0x0 0x18>; + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x24000 0x0 0x18>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + + apb: bus@ffe00000 { + compatible = "simple-bus"; + reg = <0x0 0xffe00000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; + + sd_emmc_b: sd@5000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x5000 0x0 0x800>; + interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_c: mmc@7000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x7000 0x0 0x800>; + interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; + }; + + sram: sram@fffc0000 { + compatible = "amlogic,meson-axg-sram", "mmio-sram"; + reg = <0x0 0xfffc0000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffc0000 0x20000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 3c31e21cbe..f1e5cdbade 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -35,10 +35,16 @@ no-map; }; + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved_alt: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0xbc00000>; + size = <0x0 0x10000000>; alignment = <0x0 0x400000>; linux,cma-default; }; @@ -338,7 +344,7 @@ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; pwrc_vpu: power-controller-vpu { @@ -417,6 +423,19 @@ }; }; + dmcbus: bus@c8838000 { + compatible = "simple-bus"; + reg = <0x0 0xc8838000 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x0 0x48 0x0 0x14>; + }; + }; + hiubus: bus@c883c000 { compatible = "simple-bus"; reg = <0x0 0xc883c000 0x0 0x2000>; @@ -425,7 +444,7 @@ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; reg = <0 0 0 0x400>; }; @@ -457,21 +476,21 @@ sd_emmc_a: mmc@70000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x2000>; + reg = <0x0 0x70000 0x0 0x800>; interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; sd_emmc_b: mmc@72000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x2000>; + reg = <0x0 0x72000 0x0 0x800>; interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; sd_emmc_c: mmc@74000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x2000>; + reg = <0x0 0x74000 0x0 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts index 7d5709c37e..cbe99bd4e0 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts @@ -106,6 +106,42 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + /* CVBS is available on CON1 pin 36, disabled by default */ + cvbs-connector { + compatible = "composite-video-connector"; + status = "disabled"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; }; ðmac { @@ -137,6 +173,18 @@ }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 562c26a0ba..1ade7e4868 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -307,11 +307,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { +&sysctrl { + clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -391,7 +390,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -716,6 +715,7 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { @@ -723,6 +723,7 @@ <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -730,6 +731,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -749,12 +751,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi index eb327664a4..6aaafff674 100644 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ b/arch/arm/dts/meson-gxl-mali.dtsi @@ -6,7 +6,7 @@ &apb { mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; reg = <0x0 0xc0000 0x0 0x40000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index 3e3eb31748..90a56af967 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -13,7 +13,7 @@ / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Libre Technology CC"; + model = "Libre Computer Board AML-S905X-CC"; aliases { serial0 = &uart_AO; @@ -234,9 +234,6 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; max-frequency = <100000000>; disable-wp; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 3bd405079b..a1b31013ab 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -191,8 +191,8 @@ }; &usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; + /* + * HDMI_5V is also used as supply for the USB VBUS. + */ + phy-supply = <&hdmi_5v>; }; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index dba365ed4b..8f0bb3c44b 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -13,14 +13,6 @@ / { compatible = "amlogic,meson-gxl"; - reserved-memory { - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - soc { usb0: usb@c9000000 { status = "disabled"; @@ -267,11 +259,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { - compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; +&sysctrl { + clkc: clock-controller { + compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -346,7 +337,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -725,13 +716,15 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -739,6 +732,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -758,12 +752,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 0868da476e..313f88f875 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -209,10 +209,34 @@ #cooling-cells = <2>; }; +&cpu1 { + #cooling-cells = <2>; +}; + +&cpu2 { + #cooling-cells = <2>; +}; + +&cpu3 { + #cooling-cells = <2>; +}; + &cpu4 { #cooling-cells = <2>; }; +&cpu5 { + #cooling-cells = <2>; +}; + +&cpu6 { + #cooling-cells = <2>; +}; + +&cpu7 { + #cooling-cells = <2>; +}; + ðmac { pinctrl-0 = <ð_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi new file mode 100644 index 0000000000..f50f4ef1b9 --- /dev/null +++ b/arch/arm/dts/mt7623.dtsi @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/clock/mt7623-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/mt7623-power.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt7623"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc32k: oscillator-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + + clk26m: oscillator-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt7623-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt7623-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt7623-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pinctrl: pinctrl@10005000 { + compatible = "mediatek,mt7623-pinctrl"; + reg = <0x10005000 0x1000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7623-scpsys"; + #power-domain-cells = <1>; + reg = <0x10006000 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x100>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&watchdog>; + }; + + timer0: timer@10008000 { + compatible = "mediatek,timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>; + clock-names = "system-clk"; + u-boot,dm-pre-reloc; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7623-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart3: serial@11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7623-mmc"; + reg = <0x11230000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC30_0_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7623-mmc"; + reg = <0x11240000 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts new file mode 100644 index 0000000000..84a77fde44 --- /dev/null +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7623.dtsi" + +/ { + model = "Bananapi BPI-R2"; + compatible = "bananapi,bpi-r2", "mediatek,mt7623"; + + chosen { + stdout-path = &uart2; + tick-timer = &timer0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bpi-r2:pio:blue"; + gpios = <&gpio 241 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green { + label = "bpi-r2:pio:green"; + gpios = <&gpio 240 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red { + label = "bpi-r2:pio:red"; + gpios = <&gpio 239 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&gpio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&pinctrl { + ephy_default: ephy_default { + mux { + function = "eth"; + groups = "mdc_mdio", "ephy"; + }; + + conf { + pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2", + "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0", + "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV", + "MDC", "MDIO"; + drive-strength = <12>; + mediatek,tdsel = <5>; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + mux { + function = "msdc"; + groups = "msdc1", "msdc1_wp_0"; + }; + + conf-cmd-data { + pins = "MSDC1_DAT0", "MSDC1_DAT1", "MSDC1_DAT2", + "MSDC1_DAT3", "MSDC1_DAT3", "MSDC1_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC1_CLK"; + drive-strength = <4>; + }; + + conf-wp { + pins = "EINT7"; + input-enable; + bias-pull-up; + }; + }; + + uart0_pins_a: uart0-default { + mux { + function = "uart"; + groups = "uart0_0_txd_rxd"; + }; + }; + + uart1_pins_a: uart1-default { + mux { + function = "uart"; + groups = "uart1_0_txd_rxd"; + }; + }; + + uart2_pins_a: uart2-default { + mux { + function = "uart"; + groups = "uart2_0_txd_rxd"; + }; + }; + + uart2_pins_b: uart2-alt { + mux { + function = "uart"; + groups = "uart2_1_txd_rxd"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi new file mode 100644 index 0000000000..1ef5568518 --- /dev/null +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <config.h> +/ { + binman { + filename = "u-boot-mtk.bin"; + pad-byte = <0xff>; + +#ifdef CONFIG_SPL + blob { + filename = "spl/u-boot-spl-mtk.bin"; + size = <CONFIG_SPL_PAD_TO>; + }; + + u-boot-img { + }; +#endif + }; +}; diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts new file mode 100644 index 0000000000..a6d28a060f --- /dev/null +++ b/arch/arm/dts/mt7629-rfb.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7629.dtsi" + +/ { + model = "MediaTek MT7629 RFB"; + compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; + + aliases { + spi0 = &qspi; + }; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; +}; + +&pinctrl { + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-default { + mux { + function = "uart"; + groups = "uart0_txd_rxd"; + }; + }; + + watchdog_pins: watchdog-default { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + status = "okay"; + + spi-flash@0{ + compatible = "spi-flash"; + reg = <0>; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi new file mode 100644 index 0000000000..e6052bbdcf --- /dev/null +++ b/arch/arm/dts/mt7629.dtsi @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/clock/mt7629-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/mt7629-power.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt7629"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1250000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1250000000>; + }; + }; + + clk20m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "clk20m"; + }; + + clk40m: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <20000000>; + arm,cpu-registers-not-fw-configured; + }; + + infracfg: syscon@10000000 { + compatible = "mediatek,mt7629-infracfg", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pericfg: syscon@10002000 { + compatible = "mediatek,mt7629-pericfg", "syscon"; + reg = <0x10002000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + timer0: timer@10004000 { + compatible = "mediatek,timer"; + reg = <0x10004000 0x80>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_10M_SEL>, + <&topckgen CLK_TOP_CLKXTAL_D4>; + clock-names = "mux", "src"; + u-boot,dm-pre-reloc; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7629-scpsys"; + reg = <0x10006000 0x1000>; + clocks = <&topckgen CLK_TOP_HIF_SEL>; + clock-names = "hif_sel"; + assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; + #power-domain-cells = <1>; + infracfg = <&infracfg>; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt7629-mcucfg", "syscon"; + reg = <0x10200000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,sysirq"; + reg = <0x10200a80 0x20>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + dramc: dramc@10203000 { + compatible = "mediatek,mt7629-dramc"; + reg = <0x10203000 0x600>, /* EMI */ + <0x10213000 0x1000>, /* DDRPHY */ + <0x10214000 0xd00>; /* DRAMC_AO */ + clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>, + <&topckgen CLK_TOP_SYSPLL1_D8>, + <&topckgen CLK_TOP_MEM_SEL>, + <&topckgen CLK_TOP_DMPLL>; + clock-names = "phy", "phy_mux", "mem", "mem_mux"; + u-boot,dm-pre-reloc; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7629-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + topckgen: clock-controller@10210000 { + compatible = "mediatek,mt7629-topckgen"; + reg = <0x10210000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + watchdog: watchdog@10212000 { + compatible = "mediatek,wdt"; + reg = <0x10212000 0x600>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + status = "disabled"; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&watchdog>; + }; + + pinctrl: pinctrl@10217000 { + compatible = "mediatek,mt7629-pinctrl"; + reg = <0x10217000 0x8000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + u-boot,dm-pre-reloc; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2_PD>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + status = "disabled"; + }; + + qspi: qspi@11014000 { + compatible = "mediatek,mt7629-qspi"; + reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; + reg-names = "reg_base", "mem_base"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7629-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@1b128000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b128000 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@1b130000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b130000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 5e3c195d4c..0f269d0469 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -46,6 +46,54 @@ regulator-boot-on; regulator-always-on; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &avb { @@ -94,14 +142,38 @@ function = "scif_clk"; }; + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + sdhi3_pins: sd2 { - groups = "sdhi3_data8", "sdhi3_ctrl"; + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; function = "sdhi3"; power-source = <1800>; }; sdhi3_pins_uhs: sd2_uhs { - groups = "sdhi3_data8", "sdhi3_ctrl"; + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; function = "sdhi3"; power-source = <1800>; }; @@ -120,11 +192,40 @@ }; &sdhi0 { + /* full size SD */ + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi1 { + /* microSD */ + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi3 { @@ -137,6 +238,7 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 6e7e1e3528..11ffcb7177 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -503,7 +503,7 @@ &sdmmc { u-boot,dm-pre-reloc; clock-frequency = <150000000>; - clock-freq-min-max = <100000 150000000>; + max-frequency = <40000000>; supports-sd; bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi index acfd97e18d..215d885225 100644 --- a/arch/arm/dts/rv1108.dtsi +++ b/arch/arm/dts/rv1108.dtsi @@ -121,8 +121,35 @@ }; grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon"; + compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; reg = <0x10300000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rv1108-usb2phy"; + reg = <0x100 0x0c>; + clocks = <&cru SCLK_USBPHY>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usbphy"; + rockchip,usbgrf = <&usbgrf>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-mux"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; saradc: saradc@1038c000 { @@ -141,6 +168,11 @@ reg = <0x20060000 0x1000>; }; + usbgrf: syscon@202a0000 { + compatible = "rockchip,rv1108-usbgrf", "syscon"; + reg = <0x202a0000 0x1000>; + }; + cru: clock-controller@20200000 { compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; @@ -200,12 +232,19 @@ }; usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", + compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x30180000 0x40000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - hnp-srp-disable; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -427,6 +466,35 @@ }; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index a36e0ebca0..b036a713ea 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -480,13 +480,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -618,8 +618,13 @@ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + + max-frequency = <208000000>; }; &sdhi2 { @@ -632,9 +637,11 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; fixed-emmc-driver-type = <1>; status = "okay"; + max-frequency = <200000000>; }; &sdhi3 { @@ -647,8 +654,12 @@ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &ssi1 { diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 314449478d..2458d6707d 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera <www.altera.com> + * Copyright (C) 2012 Altera <www.altera.com> */ -#include "skeleton.dtsi" #include <dt-bindings/reset/altr,rst-mgr.h> / { @@ -11,34 +10,26 @@ #size-cells = <1>; aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; timer1 = &timer1; timer2 = &timer2; timer3 = &timer3; - spi0 = &qspi; - spi1 = &spi0; - spi2 = &spi1; }; cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-smp"; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; @@ -46,6 +37,15 @@ }; }; + pmu: pmu@ff111000 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 176 4>, <0 177 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; + reg = <0xff111000 0x1000>, + <0xff113000 0x1000>; + }; + intc: intc@fffed000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -63,7 +63,7 @@ ranges; amba { - compatible = "arm,amba-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -87,6 +87,14 @@ }; }; + base_fpga_region { + compatible = "fpga-region"; + fpga-mgr = <&fpgamgr0>; + + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + can0: can@ffc00000 { compatible = "bosch,d_can"; reg = <0xffc00000 0x1000>; @@ -131,7 +139,7 @@ compatible = "fixed-clock"; }; - main_pll: main_pll { + main_pll: main_pll@40 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -139,7 +147,7 @@ clocks = <&osc1>; reg = <0x40>; - mpuclk: mpuclk { + mpuclk: mpuclk@48 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -147,7 +155,7 @@ reg = <0x48>; }; - mainclk: mainclk { + mainclk: mainclk@4c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -155,29 +163,29 @@ reg = <0x4C>; }; - dbg_base_clk: dbg_base_clk { + dbg_base_clk: dbg_base_clk@50 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; }; - main_qspi_clk: main_qspi_clk { + main_qspi_clk: main_qspi_clk@54 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; reg = <0x54>; }; - main_nand_sdmmc_clk: main_nand_sdmmc_clk { + main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; reg = <0x58>; }; - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -185,7 +193,7 @@ }; }; - periph_pll: periph_pll { + periph_pll: periph_pll@80 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -193,42 +201,42 @@ clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; reg = <0x80>; - emac0_clk: emac0_clk { + emac0_clk: emac0_clk@88 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x88>; }; - emac1_clk: emac1_clk { + emac1_clk: emac1_clk@8c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x8C>; }; - per_qspi_clk: per_qsi_clk { + per_qspi_clk: per_qsi_clk@90 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x90>; }; - per_nand_mmc_clk: per_nand_mmc_clk { + per_nand_mmc_clk: per_nand_mmc_clk@94 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x94>; }; - per_base_clk: per_base_clk { + per_base_clk: per_base_clk@98 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x98>; }; - h2f_usr1_clk: h2f_usr1_clk { + h2f_usr1_clk: h2f_usr1_clk@9c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; @@ -236,7 +244,7 @@ }; }; - sdram_pll: sdram_pll { + sdram_pll: sdram_pll@c0 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -244,28 +252,28 @@ clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; reg = <0xC0>; - ddr_dqs_clk: ddr_dqs_clk { + ddr_dqs_clk: ddr_dqs_clk@c8 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xC8>; }; - ddr_2x_dqs_clk: ddr_2x_dqs_clk { + ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xCC>; }; - ddr_dq_clk: ddr_dq_clk { + ddr_dq_clk: ddr_dq_clk@d0 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xD0>; }; - h2f_usr2_clk: h2f_usr2_clk { + h2f_usr2_clk: h2f_usr2_clk@d4 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; @@ -312,7 +320,7 @@ l3_sp_clk: l3_sp_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + clocks = <&l3_mp_clk>; div-reg = <0x64 2 2>; }; @@ -343,7 +351,7 @@ dbg_clk: dbg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; + clocks = <&dbg_at_clk>; div-reg = <0x68 2 2>; clk-gate = <0x60 5>; }; @@ -446,6 +454,14 @@ clk-phase = <0 135>; }; + sdmmc_clk_divided: sdmmc_clk_divided { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&sdmmc_clk>; + clk-gate = <0xa0 8>; + fixed-divider = <4>; + }; + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; @@ -453,10 +469,17 @@ clk-gate = <0xa0 9>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 9>; + }; + nand_clk: nand_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clocks = <&nand_x_clk>; clk-gate = <0xa0 10>; fixed-divider = <4>; }; @@ -467,8 +490,58 @@ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + }; - }; + }; + + fpga_bridge0: fpga_bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + + fpga_bridge1: fpga_bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + + fpgamgr0: fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x4>; + interrupts = <0 175 4>; + }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; @@ -477,12 +550,14 @@ interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; + clocks = <&emac_0_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -493,60 +568,14 @@ interrupts = <0 120 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; + clocks = <&emac_1_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; - status = "disabled"; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C0_RESET>; - reset-names = "i2c"; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C1_RESET>; - reset-names = "i2c"; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C2_RESET>; - reset-names = "i2c"; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C3_RESET>; - reset-names = "i2c"; - interrupts = <0 161 0x4>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -555,12 +584,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -576,12 +604,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -597,12 +624,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; @@ -613,15 +639,68 @@ }; }; - sdr: sdr@ffc25000 { - compatible = "syscon"; - reg = <0xffc25000 0x1000>; + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + resets = <&rst I2C0_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; }; - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + resets = <&rst I2C1_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + resets = <&rst I2C2_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + resets = <&rst I2C3_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + eccmgr: eccmgr { + compatible = "altr,socfpga-ecc-manager"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l2-ecc@ffd08140 { + compatible = "altr,socfpga-l2-ecc"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocram-ecc@ffd08144 { + compatible = "altr,socfpga-ocram-ecc"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; }; L2: l2-cache@fffef000 { @@ -632,36 +711,89 @@ cache-level = <2>; arm,tag-latency = <1 1 1>; arm,data-latency = <2 1 1>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <0>; + arm,prefetch-offset = <7>; + }; + + l3regs@0xff800000 { + compatible = "altr,l3regs", "syscon"; + reg = <0xff800000 0x1000>; }; - mmc0: dwmmc0@ff704000 { + mmc: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; fifo-depth = <0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + status = "disabled"; + }; + + nand0: nand@ff900000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xff900000 0x100000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0x0 0x90 0x4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; + status = "disabled"; + }; + + ocram: sram@ffff0000 { + compatible = "mmio-sram"; + reg = <0xffff0000 0x10000>; }; qspi: spi@ff705000 { - compatible = "cadence,qspi"; - #address-cells = <1>; + compatible = "cdns,qspi-nor"; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; + <0xffa00000 0x1000>; interrupts = <0 151 4>; - clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; cdns,fifo-depth = <128>; cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; - bus-num = <2>; + clocks = <&qspi_clk>; status = "disabled"; }; + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + altr,modrst-offset = <0x10>; + }; + + scu: snoop-control-unit@fffec000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffec000 0x100>; + }; + + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + spi0: spi@fff00000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; @@ -669,10 +801,7 @@ reg = <0xfff00000 0x1000>; interrupts = <0 154 4>; num-cs = <4>; - bus-num = <0>; - tx-dma-channel = <&pdma 16>; - rx-dma-channel = <&pdma 17>; - clocks = <&per_base_clk>; + clocks = <&spi_m_clk>; status = "disabled"; }; @@ -681,20 +810,22 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfff01000 0x1000>; - interrupts = <0 156 4>; + interrupts = <0 155 4>; num-cs = <4>; - bus-num = <1>; - tx-dma-channel = <&pdma 20>; - rx-dma-channel = <&pdma 21>; - clocks = <&per_base_clk>; + clocks = <&spi_m_clk>; status = "disabled"; }; + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf04>; + interrupts = <1 13 0xf01>; clocks = <&mpu_periph_clk>; }; @@ -704,6 +835,8 @@ reg = <0xffc08000 0x1000>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; }; timer1: timer1@ffc09000 { @@ -712,6 +845,8 @@ reg = <0xffc09000 0x1000>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; }; timer2: timer2@ffd00000 { @@ -720,6 +855,8 @@ reg = <0xffd00000 0x1000>; clocks = <&osc1>; clock-names = "timer"; + resets = <&rst OSC1TIMER0_RESET>; + reset-names = "timer"; }; timer3: timer3@ffd01000 { @@ -728,6 +865,8 @@ reg = <0xffd01000 0x1000>; clocks = <&osc1>; clock-names = "timer"; + resets = <&rst OSC1TIMER1_RESET>; + reset-names = "timer"; }; uart0: serial0@ffc02000 { @@ -737,7 +876,9 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; - clock-frequency = <100000000>; + dmas = <&pdma 28>, + <&pdma 29>; + dma-names = "tx", "rx"; }; uart1: serial1@ffc03000 { @@ -747,16 +888,12 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; - clock-frequency = <100000000>; + dmas = <&pdma 30>, + <&pdma 31>; + dma-names = "tx", "rx"; }; - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; - - usbphy0: usbphy@0 { + usbphy0: usbphy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; status = "okay"; @@ -768,6 +905,8 @@ interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -779,6 +918,8 @@ interrupts = <0 128 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -799,10 +940,5 @@ clocks = <&osc1>; status = "disabled"; }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; }; }; diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 46f2fd4b69..2c5249c1eb 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -748,7 +748,7 @@ }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor", "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi index b117383d75..22dbf07afc 100644 --- a/arch/arm/dts/socfpga_arria5.dtsi +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013 Altera Corporation <www.altera.com> */ /dts-v1/; @@ -19,13 +19,10 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - drvsel = <3>; - smplsel = <0>; }; sysmgr@ffd08000 { @@ -33,3 +30,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..c44d1ee2fa --- /dev/null +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 6f4de2f563..90e676e701 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013 Altera Corporation <www.altera.com> */ #include "socfpga_arria5.dtsi" @@ -10,22 +10,44 @@ compatible = "altr,socfpga-arria5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; aliases { - /* this allow the ethaddr uboot environment variable contents - * to be added to the gmac1 device tree blob. - */ + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ ethernet0 = &gmac1; - udc0 = &usb1; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&porta 0 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 11 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&porta 17 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&porta 18 1>; + }; }; regulator_3_3v: 3-3-v-regulator { @@ -34,10 +56,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { @@ -54,8 +72,28 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; @@ -72,35 +110,42 @@ &mmc0 { vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; - bus-width = <4>; - u-boot,dm-pre-reloc; -}; - -&usb1 { status = "okay"; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q00@0 { - u-boot,dm-pre-reloc; + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; }; }; -&uart0 { - u-boot,dm-pre-reloc; +&usb1 { + status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 8f356cb580..319a71e41e 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012 Altera Corporation <www.altera.com> */ /dts-v1/; @@ -19,13 +19,10 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - drvsel = <3>; - smplsel = <0>; }; sysmgr@ffd08000 { @@ -33,3 +30,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index 139a70f265..a387071674 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -47,9 +47,20 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; - bus-width = <4>; u-boot,dm-pre-reloc; }; @@ -61,3 +72,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi new file mode 100644 index 0000000000..08d81da169 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index d504150edd..67076e1b1c 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -1,32 +1,43 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright Altera Corporation (C) 2015 + * Copyright Altera Corporation (C) 2015. All rights reserved. */ #include "socfpga_cyclone5.dtsi" / { - model = "Terasic DE0-Nano(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + model = "Terasic DE-0(Atlas)"; + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + aliases { ethernet0 = &gmac1; - udc0 = &usb1; }; - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; - soc { - u-boot,dm-pre-reloc; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; }; }; @@ -34,14 +45,20 @@ status = "okay"; phy-mode = "rgmii"; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - txen-skew-ps = <0>; - txc-skew-ps = <1860>; - rxdv-skew-ps = <420>; - rxc-skew-ps = <1680>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; }; &gpio0 { @@ -58,8 +75,9 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; - dxl345: adxl345@0 { + adxl345: adxl345@53 { compatible = "adi,adxl345"; reg = <0x53>; @@ -69,14 +87,15 @@ }; &mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; status = "okay"; - u-boot,dm-pre-reloc; }; -&usb1 { +&uart0 { status = "okay"; }; -&uart0 { - u-boot,dm-pre-reloc; +&usb1 { + status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index d4dd9e9bca..e9105743ea 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -58,6 +58,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; @@ -70,3 +82,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index f62292284d..4f076bce93 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; @@ -68,3 +80,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 4e94d86114..b7054bfd5a 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -55,6 +55,10 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + &i2c0 { status = "okay"; @@ -107,3 +111,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..9436e0fa8b --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&can0 { + status = "okay"; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index c28be67bb9..6f138b2b26 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -1,31 +1,53 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012 Altera Corporation <www.altera.com> */ #include "socfpga_cyclone5.dtsi" / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; aliases { - /* this allow the ethaddr uboot environment variable contents + /* this allow the ethaddr uboot environmnet variable contents * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; - udc0 = &usb1; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 15 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 14 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 13 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&portb 12 1>; + }; }; regulator_3_3v: 3-3-v-regulator { @@ -34,10 +56,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; +}; - soc { - u-boot,dm-pre-reloc; - }; +&can0 { + status = "okay"; }; &gmac1 { @@ -68,6 +90,14 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; @@ -82,39 +112,55 @@ }; &mmc0 { - status = "okay"; - u-boot,dm-pre-reloc; - cd-gpios = <&portb 18 0>; vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; + status = "okay"; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; flash0: n25q00@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ + compatible = "n25q00"; + reg = <0>; /* chip select */ spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; }; }; -&usb1 { +&spi0 { status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <1000000>; + }; }; -&uart0 { - u-boot,dm-pre-reloc; +&usb1 { + status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi new file mode 100644 index 0000000000..648f1bd01d --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index c7a6cf2db8..c155ff02eb 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -1,32 +1,121 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> */ #include "socfpga_cyclone5.dtsi" / { model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ ethernet0 = &gmac1; - udc0 = &usb1; }; - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:blue:led0"; + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:blue:led1"; + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led2 { + label = "hps:blue:led2"; + gpios = <&portb 26 0>; /* HPS_GPIO55 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:blue:led3"; + gpios = <&portb 27 0>; /* HPS_GPIO56 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&portc 20 0>; /* HPS_GPI7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; /* SW_LID */ + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&portc 19 0>; /* HPS_GPI6 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x5>; /* SW_DOCK */ + }; + + hps_sw2 { + label = "hps_sw2"; + gpios = <&portc 18 0>; /* HPS_GPI5 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ + }; + + hps_sw3 { + label = "hps_sw3"; + gpios = <&portc 17 0>; /* HPS_GPI4 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xc>; /* SW_ROTATE_LOCK */ + }; + + hps_hkey0 { + label = "hps_hkey0"; + gpios = <&portc 21 1>; /* HPS_GPI8 */ + linux,code = <187>; /* KEY_F17 */ + }; + + hps_hkey1 { + label = "hps_hkey1"; + gpios = <&portc 22 1>; /* HPS_GPI9 */ + linux,code = <188>; /* KEY_F18 */ + }; + + hps_hkey2 { + label = "hps_hkey2"; + gpios = <&portc 23 1>; /* HPS_GPI10 */ + linux,code = <189>; /* KEY_F19 */ + }; + + hps_hkey3 { + label = "hps_hkey3"; + gpios = <&portc 24 1>; /* HPS_GPI11 */ + linux,code = <190>; /* KEY_F20 */ + }; }; - soc { - u-boot,dm-pre-reloc; + regulator_3_3v: vcc3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; }; @@ -44,46 +133,50 @@ rxc-skew-ps = <2000>; }; -&gpio0 { +&gpio0 { /* GPIO 0..29 */ status = "okay"; }; -&gpio1 { +&gpio1 { /* GPIO 30..57 */ status = "okay"; }; -&gpio2 { +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; -&i2c0 { +&i2c1 { status = "okay"; - rtc: rtc@68 { - compatible = "stm,m41t82"; - reg = <0x68>; + accel1: accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; }; }; &mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; status = "okay"; - u-boot,dm-pre-reloc; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q00@0 { - u-boot,dm-pre-reloc; + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q00"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; @@ -94,7 +187,3 @@ &usb1 { status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi new file mode 100644 index 0000000000..31bd1dba0f --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q256a", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&usb1 { + status = "okay"; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 8cde9906a0..93c3fa4a48 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> */ #include "socfpga_cyclone5.dtsi" @@ -9,83 +9,88 @@ model = "EBV SOCrates"; compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = "serial0:115200n8"; - }; - aliases { - /* - * This allows the ethaddr uboot environment variable - * contents to be added to the gmac1 device tree blob. - */ ethernet0 = &gmac1; - udc0 = &usb1; }; - memory { + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - soc { - u-boot,dm-pre-reloc; + leds: gpio-leds { }; }; &gmac1 { - status = "okay"; phy-mode = "rgmii"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; +&gpio1 { + status = "okay"; }; &i2c0 { status = "okay"; rtc: rtc@68 { - compatible = "stm,m41t82"; + compatible = "st,m41t82"; reg = <0x68>; }; }; -&mmc0 { +&leds { + compatible = "gpio-leds"; + + led0 { + label = "led:green:heartbeat"; + gpios = <&porta 28 1>; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led:green:D7"; + gpios = <&portb 19 1>; + }; + + led2 { + label = "led:green:D8"; + gpios = <&portb 25 1>; + }; +}; + +&mmc { status = "okay"; - u-boot,dm-pre-reloc; }; &qspi { status = "okay"; + u-boot,dm-pre-reloc; - flash0: n25q00@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + status = "okay"; + u-boot,dm-pre-reloc; }; }; - -&usb1 { - disable-over-current; - status = "okay"; -}; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 86c61fe081..6a6c29be79 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -50,6 +50,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &i2c0 { status = "okay"; speed-mode = <0>; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi new file mode 100644 index 0000000000..360b946ba2 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * U-Boot additions + * + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb0; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; + + n25q128@0 { + compatible = "n25q128", "spi-flash"; + u-boot,dm-pre-reloc; + }; + n25q00@1 { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index 85ab56379f..355b3dbf43 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,100 +1,238 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) /* * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ #include "socfpga_cyclone5.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "samtec VIN|ING FPGA"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + aliases { + /* + * This allow the ethaddr uboot environment variable contents + * to be added to the gmac1 device tree blob. + */ ethernet0 = &gmac1; - udc0 = &usb0; + ethernet1 = &gmac0; }; - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ + gpio-keys { + compatible = "gpio-keys"; + + hps_temp0 { + label = "BTN_0"; /* TEMP_OS */ + gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */ + linux,code = <BTN_0>; + }; + + hps_hkey0 { + label = "BTN_1"; /* DIS_PWR */ + gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */ + linux,code = <BTN_1>; + }; + + hps_hkey1 { + label = "hps_hkey1"; /* POWER_DOWN */ + gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ + linux,code = <KEY_POWER>; + }; }; - soc { - u-boot,dm-pre-reloc; + regulator-usb-nrst { + compatible = "regulator-fixed"; + regulator-name = "usb_nrst"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; }; }; &gmac1 { status = "okay"; phy-mode = "rgmii"; + phy-handle = <&phy1>; + + snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <10000 10000 10000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + }; + }; }; -&gpio0 { +&gpio0 { /* GPIO 0..29 */ status = "okay"; }; -&gpio1 { +&gpio1 { /* GPIO 30..57 */ status = "okay"; }; -&gpio2 { +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; &i2c0 { status = "okay"; - rtc: rtc@68 { - compatible = "stm,m41t82"; - reg = <0x68>; + gpio: pca9557@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + temp: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + at24@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + + i2cswitch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@6 { /* Backplane EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@7 { /* Power board EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; }; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q128@0 { - u-boot,dm-pre-reloc; + n25q128@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q128"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; }; - flash1: n25q00@1 { - u-boot,dm-pre-reloc; + n25q00@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <1>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q00"; + reg = <1>; /* chip select */ + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; @@ -103,13 +241,11 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { + dr_mode = "peripheral"; status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index bceac09154..98bd5dfc70 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -26,7 +26,7 @@ }; qspi: spi@80203000 { - compatible = "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0x80203000 0x100>, diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index ab886650cd..e16c7f245e 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -308,13 +308,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -396,8 +396,12 @@ vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi2 { @@ -410,8 +414,10 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; status = "okay"; + max-frequency = <200000000>; }; &ssi1 { diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h b/arch/arm/include/asm/arch-mediatek/gpio.h new file mode 100644 index 0000000000..4ea1020634 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_GPIO_H +#define __MEDIATEK_GPIO_H + +#endif /* __MEDIATEK_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 0000000000..2530e78a5f --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x08000000 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 0000000000..d293f2a839 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_BOOT_DEVICE 0xF +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) + +#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) +#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) + +#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h new file mode 100644 index 0000000000..a90fe55081 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/boot.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __MESON_BOOT_H__ +#define __MESON_BOOT_H__ + +/* Boot device */ +#define BOOT_DEVICE_RESERVED 0 +#define BOOT_DEVICE_EMMC 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_SPI 3 +#define BOOT_DEVICE_SD 4 +#define BOOT_DEVICE_USB 5 + +int meson_get_boot_device(void); + +#endif /* __MESON_BOOT_H__ */ diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h new file mode 100644 index 0000000000..1ef88e4fad --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-axg.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#ifndef _ARCH_MESON_CLOCK_AXG_H_ +#define _ARCH_MESON_CLOCK_AXG_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + +#endif diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock-gx.h index c0ff00fc9a..13a2e7688f 100644 --- a/arch/arm/include/asm/arch-meson/clock.h +++ b/arch/arm/include/asm/arch-meson/clock-gx.h @@ -3,8 +3,8 @@ * Copyright 2016 - AmLogic, Inc. * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> */ -#ifndef _ARCH_MESON_CLOCK_H_ -#define _ARCH_MESON_CLOCK_H_ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ /* * Clock controller register offsets diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index 1aa0872d53..08acc5cbf7 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -10,13 +10,13 @@ #include <phy.h> enum { - /* Use GXL Internal RMII PHY */ - MESON_GXL_USE_INTERNAL_RMII_PHY = 1, + /* Use Internal RMII PHY */ + MESON_USE_INTERNAL_RMII_PHY = 1, }; /* Configure the Ethernet MAC with the requested interface mode * with some optional flags. */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); +void meson_eth_init(phy_interface_t mode, unsigned int flags); #endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 4bc9475d35..b781ba9475 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -21,6 +21,7 @@ #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) +#define GX_AO_BOOT_DEVICE 0xF #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 #define GX_AO_MEM_SIZE_SHIFT 16 #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h index 62818335d9..a65100aeb7 100644 --- a/arch/arm/include/asm/arch-meson/mem.h +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -10,6 +10,7 @@ /* Configure the reserved memory zones exported by the secure registers * into EFI and DTB reserved memory entries. */ -void meson_gx_init_reserved_memory(void *fdt); +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); #endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 1d5b3a07d0..0eb19ca86f 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -43,6 +43,12 @@ struct sysreset_reg { unsigned int glb_srst_snd_value; }; +struct softreset_reg { + void __iomem *base; + unsigned int sf_reset_offset; + unsigned int sf_reset_num; +}; + /** * clk_get_divisor() - Calculate the required clock divisior * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index b18de9f7c2..15eeb9c440 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -69,16 +69,21 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) +#define LPLL_HZ (600*MHz) +#define BPLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (676*MHz) #define PMU_PCLK_HZ (48*MHz) -#define ACLKM_CORE_HZ (300*MHz) -#define ATCLK_CORE_HZ (300*MHz) -#define PCLK_DBG_HZ (100*MHz) +#define ACLKM_CORE_L_HZ (300*MHz) +#define ATCLK_CORE_L_HZ (300*MHz) +#define PCLK_DBG_L_HZ (100*MHz) + +#define ACLKM_CORE_B_HZ (300*MHz) +#define ATCLK_CORE_B_HZ (300*MHz) +#define PCLK_DBG_B_HZ (100*MHz) #define PERIHP_ACLK_HZ (148500*KHz) #define PERIHP_HCLK_HZ (148500*KHz) @@ -98,4 +103,13 @@ enum apll_l_frequencies { APLL_L_600_MHZ, }; +enum apll_b_frequencies { + APLL_B_600_MHZ, +}; + +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq); +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq); + #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 3cc2ed0187..7697e96a91 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -11,7 +11,11 @@ #define OSC_HZ (24 * 1000 * 1000) #define APLL_HZ (600 * 1000000) -#define GPLL_HZ (594 * 1000000) +#define GPLL_HZ (1188 * 1000000) +#define ACLK_PERI_HZ (148500000) +#define HCLK_PERI_HZ (148500000) +#define PCLK_PERI_HZ (74250000) +#define ACLK_BUS_HZ (148500000) struct rv1108_clk_priv { struct rv1108_cru *cru; @@ -80,6 +84,11 @@ enum { WORK_MODE_NORMAL = 1, DSMPD_SHIFT = 3, DSMPD_MASK = 1 << DSMPD_SHIFT, + INTEGER_MODE = 1, + GLOBAL_POWER_DOWN_SHIFT = 0, + GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, + GLOBAL_POWER_DOWN = 1, + GLOBAL_POWER_UP = 0, /* CLKSEL0_CON */ CORE_PLL_SEL_SHIFT = 8, @@ -90,11 +99,77 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON1 */ + PCLK_DBG_DIV_CON_SHIFT = 4, + PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, + ACLK_CORE_DIV_CON_SHIFT = 0, + ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, + + /* CLKSEL_CON2 */ + ACLK_BUS_PLL_SEL_SHIFT = 8, + ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, + ACLK_BUS_PLL_SEL_GPLL = 0, + ACLK_BUS_PLL_SEL_APLL = 1, + ACLK_BUS_PLL_SEL_DPLL = 2, + ACLK_BUS_DIV_CON_SHIFT = 0, + ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, + ACLK_BUS_DIV_CON_WIDTH = 5, + + /* CLKSEL_CON3 */ + PCLK_BUS_DIV_CON_SHIFT = 8, + PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, + HCLK_BUS_DIV_CON_SHIFT = 0, + HCLK_BUS_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON4 */ + CLK_DDR_PLL_SEL_SHIFT = 8, + CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, + CLK_DDR_DIV_CON_SHIFT = 0, + CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, + + /* CLKSEL_CON19 */ + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, + CLK_I2C1_PLL_SEL_DPLL = 0, + CLK_I2C1_PLL_SEL_GPLL = 1, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, + CLK_I2C0_DIV_CON_SHIFT = 0, + CLK_I2C0_DIV_CON_MASK = 0x7f, + I2C_DIV_CON_WIDTH = 7, + + /* CLKSEL_CON20 */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, + CLK_I2C3_PLL_SEL_DPLL = 0, + CLK_I2C3_PLL_SEL_GPLL = 1, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, + CLK_I2C2_DIV_CON_SHIFT = 0, + CLK_I2C2_DIV_CON_MASK = 0x7f, + /* CLKSEL_CON22 */ CLK_SARADC_DIV_CON_SHIFT= 0, CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL_CON23 */ + ACLK_PERI_PLL_SEL_SHIFT = 15, + ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, + ACLK_PERI_PLL_SEL_GPLL = 0, + ACLK_PERI_PLL_SEL_DPLL = 1, + PCLK_PERI_DIV_CON_SHIFT = 10, + PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, + HCLK_PERI_DIV_CON_SHIFT = 5, + HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, + ACLK_PERI_DIV_CON_SHIFT = 0, + ACLK_PERI_DIV_CON_MASK = 0x1f, + PERI_DIV_CON_WIDTH = 5, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, @@ -105,6 +180,17 @@ enum { MAC_CLK_DIV_MASK = 0x1f, MAC_CLK_DIV_SHIFT = 0, + /* CLKSEL25_CON */ + EMMC_PLL_SEL_SHIFT = 12, + EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, + EMMC_PLL_SEL_DPLL = 0, + EMMC_PLL_SEL_GPLL, + EMMC_PLL_SEL_OSC, + + /* CLKSEL26_CON */ + EMMC_CLK_DIV_SHIFT = 8, + EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, + /* CLKSEL27_CON */ SFC_PLL_SEL_SHIFT = 7, SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, @@ -112,5 +198,61 @@ enum { SFC_PLL_SEL_GPLL = 1, SFC_CLK_DIV_SHIFT = 0, SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, + + /* CLKSEL28_CON */ + ACLK_VIO1_PLL_SEL_SHIFT = 14, + ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, + VIO_PLL_SEL_DPLL = 0, + VIO_PLL_SEL_GPLL = 1, + ACLK_VIO1_CLK_DIV_SHIFT = 8, + ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, + CLK_VIO_DIV_CON_WIDTH = 5, + ACLK_VIO0_PLL_SEL_SHIFT = 6, + ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, + ACLK_VIO0_CLK_DIV_SHIFT = 0, + ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, + + /* CLKSEL29_CON */ + PCLK_VIO_CLK_DIV_SHIFT = 8, + PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, + HCLK_VIO_CLK_DIV_SHIFT = 0, + HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, + + /* CLKSEL32_CON */ + DCLK_VOP_SEL_SHIFT = 7, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_HDMI = 0, + DCLK_VOP_SEL_PLL = 1, + DCLK_VOP_PLL_SEL_SHIFT = 6, + DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_GPLL = 0, + DCLK_VOP_PLL_SEL_DPLL = 1, + DCLK_VOP_CLK_DIV_SHIFT = 0, + DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, + DCLK_VOP_DIV_CON_WIDTH = 6, + + /* SOFTRST1_CON*/ + DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, + DDRPHY_SRSTN_CLKDIV_REQ = 1, + DDRPHY_SRSTN_CLKDIV_DIS = 0, + DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, + DDRPHY_SRSTN_REQ_SHIFT = 1, + DDRPHY_SRSTN_REQ = 1, + DDRPHY_SRSTN_DIS = 0, + DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, + DDRPHY_PSRSTN_REQ_SHIFT = 2, + DDRPHY_PSRSTN_REQ = 1, + DDRPHY_PSRSTN_DIS = 0, + DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, + + /* SOFTRST2_CON*/ + DDRUPCTL_PSRSTN_REQ_SHIFT = 0, + DDRUPCTL_PSRSTN_REQ = 1, + DDRUPCTL_PSRSTN_DIS = 0, + DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, + DDRUPCTL_NSRSTN_REQ_SHIFT = 1, + DDRUPCTL_NSRSTN_REQ = 1, + DDRUPCTL_NSRSTN_DIS = 0, + DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h index 28a159c5b7..d05197670d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -205,4 +205,46 @@ enum { ATO_AE_SHIFT = 0, ATO_AE_MASK = 1, }; + +/* GRF_UOC_CON0 */ +enum { + SIDDQ_SHIFT = 13, + SIDDQ_MASK = 1 << SIDDQ_SHIFT, + + BYPASSSEL_SHIFT = 9, + BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, + + BYPASSDMEN_SHIFT = 8, + BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, + + UOC_DISABLE_SHIFT = 4, + UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, + + COMMON_ON_N_SHIFT = 0, + COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, +}; + +/* GRF_UOC_CON2 */ +enum { + SOFT_CON_SEL_SHIFT = 2, + SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, +}; + +/* GRF_UOC0_CON3 */ +enum { + TERMSEL_FULLSPEED_SHIFT = 5, + TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, + + XCVRSELECT_SHIFT = 3, + XCVRSELECT_FSTRANSC = 1, + XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, + + OPMODE_SHIFT = 1, + OPMODE_NODRIVING = 1, + OPMODE_MASK = 3 << OPMODE_SHIFT, + + SUSPENDN_SHIFT = 0, + SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, +}; + #endif diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S index 0db4360bcf..cb205fa30a 100644 --- a/arch/arm/lib/crt0_aarch64_efi.S +++ b/arch/arm/lib/crt0_aarch64_efi.S @@ -28,13 +28,13 @@ coff_header: .short 2 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ - .long 1 /* NumberOfSymbols */ + .long 0 /* NumberOfSymbols */ .short section_table - optional_header /* SizeOfOptionalHeader */ - /* - * Characteristics: IMAGE_FILE_DEBUG_STRIPPED | - * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED - */ - .short 0x206 + /* Characteristics */ + .short (IMAGE_FILE_EXECUTABLE_IMAGE | \ + IMAGE_FILE_LINE_NUMS_STRIPPED | \ + IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ + IMAGE_FILE_DEBUG_STRIPPED) optional_header: .short 0x20b /* PE32+ format */ .byte 0x02 /* MajorLinkerVersion */ diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S index 23db49f1fc..5470e2ff0e 100644 --- a/arch/arm/lib/crt0_arm_efi.S +++ b/arch/arm/lib/crt0_arm_efi.S @@ -27,16 +27,16 @@ coff_header: .short 2 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ - .long 1 /* NumberOfSymbols */ + .long 0 /* NumberOfSymbols */ .short section_table - optional_header /* SizeOfOptionalHeader */ - /* - * Characteristics: IMAGE_FILE_32BIT_MACHINE | - * IMAGE_FILE_DEBUG_STRIPPED | IMAGE_FILE_EXECUTABLE_IMAGE | - * IMAGE_FILE_LINE_NUMS_STRIPPED - */ - .short 0x306 + /* Characteristics */ + .short (IMAGE_FILE_EXECUTABLE_IMAGE | \ + IMAGE_FILE_LINE_NUMS_STRIPPED | \ + IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ + IMAGE_FILE_32BIT_MACHINE | \ + IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short 0x10b /* PE32+ format */ + .short 0x10b /* PE32 format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 406dda3b02..bd4ab361b2 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -5,5 +5,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_CPU_V7R) += r5_mpu.o +obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-y += common.o diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S new file mode 100644 index 0000000000..70c5d1cade --- /dev/null +++ b/arch/arm/mach-k3/lowlevel_init.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + and r0, #0xff + cmp r0, #0x0 + bne park_cpu + bx lr +park_cpu: + wfi + b park_cpu + +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 0000000000..7a733e95df --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,39 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7623 + bool "MediaTek MT7623 SoC" + select CPU_V7A + select ARCH_MISC_INIT + help + The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-450 graphics, several DDR3 options, + crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder, + video interfaces supporting HDMI and MIPI, and video codec support. + Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe, + I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM. + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + select CPU_V7A + select SPL + select ARCH_MISC_INIT + help + The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 + including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, + switch, USB3.0, PCIe, UART, SPI, I2C and PWM. + +endchoice + +source "board/mediatek/mt7623/Kconfig" +source "board/mediatek/mt7629/Kconfig" + +endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile new file mode 100644 index 0000000000..b5d3a379bc --- /dev/null +++ b/arch/arm/mach-mediatek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += cpu.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-$(CONFIG_TARGET_MT7623) += mt7623/ +obj-$(CONFIG_TARGET_MT7629) += mt7629/ diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c new file mode 100644 index 0000000000..b37e299b74 --- /dev/null +++ b/arch/arm/mach-mediatek/cpu.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <common.h> +#include <dm.h> +#include <wdt.h> +#include <dm/uclass-internal.h> + +int arch_misc_init(void) +{ + struct udevice *wdt; + int ret; + + ret = uclass_first_device_err(UCLASS_WDT, &wdt); + if (!ret) + wdt_stop(wdt); + + return 0; +} + +int arch_cpu_init(void) +{ + icache_enable(); + + return 0; +} + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} diff --git a/arch/arm/mach-mediatek/init.h b/arch/arm/mach-mediatek/init.h new file mode 100644 index 0000000000..1d896fbbf7 --- /dev/null +++ b/arch/arm/mach-mediatek/init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_INIT_H_ +#define __MEDIATEK_INIT_H_ + +extern int mtk_soc_early_init(void); + +#endif /* __MEDIATEK_INIT_H_ */ diff --git a/arch/arm/mach-mediatek/mt7623/Makefile b/arch/arm/mach-mediatek/mt7623/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c new file mode 100644 index 0000000000..0ee8c6664c --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <common.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/arch/misc.h> + +#include "preloader.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct boot_argument *preloader_param; + +int mtk_soc_early_init(void) +{ + return 0; +} + +int dram_init(void) +{ + u32 i; + + if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + ((size_t)preloader_param % sizeof(size_t) == 0) && + preloader_param->magic == BOOT_ARGUMENT_MAGIC && + preloader_param->dram_rank_num <= + ARRAY_SIZE(preloader_param->dram_rank_size)) { + gd->ram_size = 0; + + for (i = 0; i < preloader_param->dram_rank_num; i++) + gd->ram_size += preloader_param->dram_rank_size[i]; + } else { + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + SZ_2G); + } + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1); + + return 0; +} diff --git a/arch/arm/mach-mediatek/mt7623/lowlevel_init.S b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S new file mode 100644 index 0000000000..afb94767ee --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <linux/linkage.h> + +.extern preloader_param + +ENTRY(save_boot_params) + ldr r6, =preloader_param + str r4, [r6] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(lowlevel_init) + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-mediatek/mt7623/preloader.h b/arch/arm/mach-mediatek/mt7623/preloader.h new file mode 100644 index 0000000000..2d2c71ad4c --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/preloader.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __PRELOADER_H_ +#define __PRELOADER_H_ + +enum forbidden_mode { + F_FACTORY_MODE = 0x0001 +}; + +union lk_hdr { + struct { + u32 magic; + u32 size; + char name[32]; + u32 loadaddr; + }; + + u8 data[512]; +}; + +struct sec_limit { + unsigned int magic_num; + enum forbidden_mode forbid_mode; +}; + +enum bootmode { + NORMAL_BOOT = 0, + META_BOOT = 1, + RECOVERY_BOOT = 2, + SW_REBOOT = 3, + FACTORY_BOOT = 4, + ADVMETA_BOOT = 5, + ATE_FACTORY_BOOT = 6, + ALARM_BOOT = 7, + + KERNEL_POWER_OFF_CHARGING_BOOT = 8, + LOW_POWER_OFF_CHARGING_BOOT = 9, + + FAST_BOOT = 99, + DOWNLOAD_BOOT = 100, + UNKNOWN_BOOT +}; + +enum boot_reason { + BR_POWER_KEY = 0, + BR_USB, + BR_RTC, + BR_WDT, + BR_WDT_BY_PASS_PWK, + BR_TOOL_BY_PASS_PWK, + BR_2SEC_REBOOT, + BR_UNKNOWN +}; + +enum meta_com_type { + META_UNKNOWN_COM = 0, + META_UART_COM, + META_USB_COM +}; + +struct da_info_t { + u32 addr; + u32 arg1; + u32 arg2; + u32 len; + u32 sig_len; +}; + +struct boot_argument { + u32 magic; + enum bootmode boot_mode; + u32 e_flag; + u32 log_port; + u32 log_baudrate; + u8 log_enable; + u8 part_num; + u8 reserved[2]; + u32 dram_rank_num; + u32 dram_rank_size[4]; + u32 boot_reason; + enum meta_com_type meta_com_type; + u32 meta_com_id; + u32 boot_time; + struct da_info_t da_info; + struct sec_limit sec_limit; + union lk_hdr *part_info; + u8 md_type[4]; + u32 ddr_reserve_enable; + u32 ddr_reserve_success; + u32 chip_ver; + char pl_version[8]; +}; + +#define BOOT_ARGUMENT_MAGIC 0x504c504c + +#endif /* __PRELOADER_H_ */ diff --git a/arch/arm/mach-mediatek/mt7629/Makefile b/arch/arm/mach-mediatek/mt7629/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c new file mode 100644 index 0000000000..ba91a6eaa6 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <linux/io.h> + +#include <dt-bindings/clock/mt7629-clk.h> + +#define L2_CFG_BASE 0x10200000 +#define L2_CFG_SIZE 0x1000 +#define L2_SHARE_CFG_MP0 0x7f0 +#define L2_SHARE_MODE_OFF BIT(8) + +DECLARE_GLOBAL_DATA_PTR; + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1250000000, + [CLK_APMIXED_MAINPLL] = 1120000000, + [CLK_APMIXED_UNIV2PLL] = 1200000000, + [CLK_APMIXED_ETH1PLL] = 500000000, + [CLK_APMIXED_ETH2PLL] = 700000000, + [CLK_APMIXED_SGMIPLL] = 650000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + /* setup mcu bus */ + ret = uclass_get_device_by_driver(UCLASS_SYSCON, + DM_GET_DRIVER(mtk_mcucfg), &dev); + if (ret) + return ret; + + return 0; +} + +int mtk_soc_early_init(void) +{ + struct udevice *dev; + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + return 0; +} + +int mach_cpu_init(void) +{ + void __iomem *base; + + base = ioremap(L2_CFG_BASE, L2_CFG_SIZE); + + /* disable L2C shared mode */ + writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0); + + return 0; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + ret = ram_get_info(dev, &ram); + if (ret) + return ret; + + debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 hwcode, swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + hwcode = readl(chipid + APHW_CODE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1); + + return 0; +} diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S new file mode 100644 index 0000000000..90dd4ea48e --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + +#ifndef CONFIG_SPL_BUILD + /* Return to U-Boot via saved link register */ + mov pc, lr +#else + /* + * Arch timer : + * set CNTFRQ = 20Mhz, set CNTVOFF = 0 + */ + movw r0, #0x2d00 + movt r0, #0x131 + mcr p15, 0, r0, c14, c0, 0 + + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + + /* if MP core, handle secondary cores */ + mrc p15, 0, r0, c0, c0, 5 + ands r1, r0, #0x40000000 + bne go @ Go if UP + ands r0, r0, #0x0f + beq go @ Go if core0 on primary core tile + b secondary + +go: + /* master CPU */ + mov pc, lr + +secondary: + /* read slave CPU number into r0 firstly */ + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #0x0f + +loop: + dsb + isb + wfi @Zzz... + b loop +#endif +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c new file mode 100644 index 0000000000..9b3590ff3d --- /dev/null +++ b/arch/arm/mach-mediatek/spl.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <spl.h> + +#include "init.h" + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + hang(); + + /* enable console uart printing */ + preloader_console_init(); + + /* soc early initialization */ + ret = mtk_soc_early_init(); + if (ret) + hang(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + return BOOT_DEVICE_SPI; +#elif defined(CONFIG_SPL_MMC_SUPPORT) + return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_SPL_NAND_SUPPORT) + return BOOT_DEVICE_NAND; +#elif defined(CONFIG_SPL_NOR_SUPPORT) + return BOOT_DEVICE_NOR; +#else + return BOOT_DEVICE_NONE; +#endif +} diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index cc943443b3..11077bc6cc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -1,89 +1,49 @@ if ARCH_MESON -config MESON_GXBB - bool "Support Meson GXBaby" - select ARM64 - select CLK - select DM - select DM_SERIAL - imply CMD_DM - help - The Amlogic Meson GXBaby (S905) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. - -config MESON_GXL - bool "Support Meson GXL" +config MESON64_COMMON + bool select ARM64 select CLK select DM select DM_SERIAL + select SYSCON + select REGMAP + select BOARD_LATE_INIT imply CMD_DM - help - The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. - -config MESON_GXM - bool "Support Meson GXM" - select ARM64 - select CLK - select DM - select DM_SERIAL - help - The Amlogic Meson GXM (S912) is an ARM SoC with an - octo-core Cortex-A53 CPU and a Mali-T860 GPU. - -if MESON_GXBB -config TARGET_ODROID_C2 - bool "ODROID-C2" - help - ODROID-C2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD - slot, eMMC, IR receiver and a 40-pin GPIO header. +config MESON_GX + bool + select MESON64_COMMON -config TARGET_NANOPI_K2 - bool "NANOPI_K2" - help - NANOPI_K2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB, - micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. -endif +choice + prompt "Platform select" + default MESON_GXBB -if MESON_GXL - -config TARGET_P212 - bool "P212" +config MESON_GXBB + bool "GXBB" + select MESON_GX help - P212 is a reference dessign board based on Meson GXL S905X SoC - with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, - eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. + Select this if your SoC is an S905 -config TARGET_LIBRETECH_CC - bool "LIBRETECH-CC" +config MESON_GXL + bool "GXL" + select MESON_GX help - LibreTech CC is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. + Select this if your SoC is an S905X/D or S805X -config TARGET_KHADAS_VIM - bool "KHADAS-VIM" +config MESON_GXM + bool "GXM" + select MESON_GX help - Khadas VIM is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. - -endif + Select this if your SoC is an S912 -if MESON_GXM - -config TARGET_KHADAS_VIM2 - bool "KHADAS-VIM2" +config MESON_AXG + bool "AXG" + select MESON64_COMMON help - Khadas VIM2 is a single board computer based on Meson GXM - with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. + Select this if your SoC is an A113X/D -endif +endchoice config SYS_SOC default "meson" @@ -91,16 +51,32 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x1000 -source "board/amlogic/odroid-c2/Kconfig" - -source "board/amlogic/nanopi-k2/Kconfig" - -source "board/amlogic/p212/Kconfig" - -source "board/amlogic/libretech-cc/Kconfig" - -source "board/amlogic/khadas-vim/Kconfig" +config SYS_VENDOR + string "Vendor name" + default "amlogic" + help + This option contains information about board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will + be used. + +config SYS_BOARD + string "Board name" + default "odroid-c2" if MESON_GXBB + default "p212" if MESON_GXL + default "q200" if MESON_GXM + default "s400" if MESON_AXG + default "" + help + This option contains information about board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will + be used. -source "board/amlogic/khadas-vim2/Kconfig" +config SYS_CONFIG_NAME + string "Board configuration name" + default "meson64" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 8ad9b3e575..b716e1a152 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -2,4 +2,6 @@ # # Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com> -obj-y += board.o sm.o eth.o +obj-y += board-common.o sm.o +obj-$(CONFIG_MESON_GX) += board-gx.o +obj-$(CONFIG_MESON_AXG) += board-axg.o diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c new file mode 100644 index 0000000000..173905e762 --- /dev/null +++ b/arch/arm/mach-meson/board-axg.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/boot.h> +#include <asm/arch/eth.h> +#include <asm/arch/axg.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +int meson_get_boot_device(void) +{ + return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; +} + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(AXG_AO_SEC_GP_CFG3); + + bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK) + >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(AXG_AO_SEC_GP_CFG5); + bl32_start = readl(AXG_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK) + >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region axg_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = axg_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | + AXG_ETH_REG_0_TX_PHASE(1) | + AXG_ETH_REG_0_TX_RATIO(4) | + AXG_ETH_REG_0_PHY_CLK_EN | + AXG_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | + AXG_ETH_REG_0_INVERT_RMII_CLK | + AXG_ETH_REG_0_CLK_EN); + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c new file mode 100644 index 0000000000..8c41301674 --- /dev/null +++ b/arch/arm/mach-meson/board-common.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + */ + +#include <common.h> +#include <asm/arch/boot.h> +#include <linux/libfdt.h> +#include <linux/err.h> +#include <asm/arch/mem.h> +#include <asm/arch/sm.h> +#include <asm/armv8/mmu.h> +#include <asm/unaligned.h> +#include <efi_loader.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + const fdt64_t *val; + int offset; + int len; + + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + + /* Use unaligned access since cache is still disabled */ + gd->ram_size = get_unaligned_be64(&val[1]); + + return 0; +} + +__weak int meson_ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_init_reserved_memory(blob); + + return meson_ft_board_setup(blob, bd); +} + +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) +{ + int ret; + + ret = fdt_add_mem_rsv(fdt, start, size); + if (ret) + printf("Could not reserve zone @ 0x%llx\n", start); + + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + efi_add_memory_map(start, + ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); + } +} + +static void meson_set_boot_source(void) +{ + const char *source; + + switch (meson_get_boot_device()) { + case BOOT_DEVICE_EMMC: + source = "emmc"; + break; + + case BOOT_DEVICE_NAND: + source = "nand"; + break; + + case BOOT_DEVICE_SPI: + source = "spi"; + break; + + case BOOT_DEVICE_SD: + source = "sd"; + break; + + case BOOT_DEVICE_USB: + source = "usb"; + break; + + default: + source = "unknown"; + } + + env_set("boot_source", source); +} + +__weak int meson_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + meson_set_boot_source(); + + return meson_board_late_init(); +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board-gx.c index d6c6253152..e41552db52 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board-gx.c @@ -1,64 +1,30 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> */ #include <common.h> -#include <linux/libfdt.h> -#include <linux/err.h> +#include <asm/arch/boot.h> +#include <asm/arch/eth.h> #include <asm/arch/gx.h> -#include <asm/arch/sm.h> +#include <asm/arch/mem.h> +#include <asm/io.h> #include <asm/armv8/mmu.h> -#include <asm/unaligned.h> #include <linux/sizes.h> -#include <efi_loader.h> -#include <asm/io.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) -{ - const fdt64_t *val; - int offset; - int len; - - offset = fdt_path_offset(gd->fdt_blob, "/memory"); - if (offset < 0) - return -EINVAL; - - val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); - if (len < sizeof(*val) * 2) - return -EINVAL; - - /* Use unaligned access since cache is still disabled */ - gd->ram_size = get_unaligned_be64(&val[1]); - - return 0; -} - -phys_size_t get_effective_memsize(void) +int meson_get_boot_device(void) { - /* Size is reported in MiB, convert it in bytes */ - return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) - >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; + return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; } -static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) -{ - int ret; - - ret = fdt_add_mem_rsv(fdt, start, size); - if (ret) - printf("Could not reserve zone @ 0x%llx\n", start); - - if (IS_ENABLED(CONFIG_EFI_LOADER)) { - efi_add_memory_map(start, - ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -} - -void meson_gx_init_reserved_memory(void *fdt) +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) { u64 bl31_size, bl31_start; u64 bl32_size, bl32_start; @@ -70,7 +36,6 @@ void meson_gx_init_reserved_memory(void *fdt) * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL */ - reg = readl(GX_AO_SEC_GP_CFG3); bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) @@ -102,9 +67,11 @@ void meson_gx_init_reserved_memory(void *fdt) meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); } -void reset_cpu(ulong addr) +phys_size_t get_effective_memsize(void) { - psci_system_reset(); + /* Size is reported in MiB, convert it in bytes */ + return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) + >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; } static struct mm_region gx_mem_map[] = { @@ -128,3 +95,44 @@ static struct mm_region gx_mem_map[] = { }; struct mm_region *mem_map = gx_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); + + /* Use GXL RMII Internal PHY */ + if (IS_ENABLED(CONFIG_MESON_GXL) && + (flags & MESON_USE_INTERNAL_RMII_PHY)) { + writel(0x10110181, GX_ETH_REG_2); + writel(0xe40908ff, GX_ETH_REG_3); + } + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c deleted file mode 100644 index 8b28bc8531..0000000000 --- a/arch/arm/mach-meson/eth.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/arch/gx.h> -#include <asm/arch/eth.h> -#include <phy.h> - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | - GX_ETH_REG_0_TX_PHASE(1) | - GX_ETH_REG_0_TX_RATIO(4) | - GX_ETH_REG_0_PHY_CLK_EN | - GX_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | - GX_ETH_REG_0_CLK_EN); - - /* Use GXL RMII Internal PHY */ - if (IS_ENABLED(CONFIG_MESON_GXL) && - (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { - writel(0x10110181, GX_ETH_REG_2); - writel(0xe40908ff, GX_ETH_REG_3); - } - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); -} diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 0bba5e4a07..a07b46895d 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -6,7 +6,6 @@ */ #include <common.h> -#include <asm/arch/gx.h> #include <linux/kernel.h> #define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020 diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0d2d39878d..aa1be8ebab 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -261,6 +261,9 @@ int print_cpuinfo(void) case MV_88F68XX_A0_ID: puts("A0"); break; + case MV_88F68XX_B0_ID: + puts("B0"); + break; default: printf("?? (%x)", revid); break; diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 6e2e14efe0..01577f469b 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -27,6 +27,7 @@ /* A38x revisions */ #define MV_88F68XX_Z1_ID 0x0 #define MV_88F68XX_A0_ID 0x4 +#define MV_88F68XX_B0_ID 0xa /* TCLK Core Clock definition */ #ifndef CONFIG_SYS_TCLK diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 50b2358266..365332d2b0 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -233,6 +233,7 @@ /* A38x revisions */ #define MV_88F68XX_Z1_ID 0x0 #define MV_88F68XX_A0_ID 0x4 +#define MV_88F68XX_B0_ID 0xa /* A39x revisions */ #define MV_88F69XX_Z1_ID 0x2 diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 145d96b1f0..6dc8e3a017 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,7 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM + select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -156,6 +157,14 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. +config ROCKCHIP_USB_UART + bool "Route uart output to usb pins" + help + Rockchip SoCs have the ability to route the signals of the debug + uart through the d+ and d- pins of a specific usb phy to enable + some form of closed-case debugging. With this option supported + SoCs will enable this routing as a debug measure. + config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 05706c472a..368302e1da 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o +obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 98ca971b88..3c6c3d3c09 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h> @@ -92,23 +93,38 @@ static int setup_arm_clock(void) return ret; } -void board_init_f(ulong dummy) +void board_debug_uart_init(void) { - struct udevice *pinctrl, *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3188 */ -#ifdef EARLY_UART -#include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + }; + /* Enable early UART on the RK3188 */ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl, *dev; + int ret; + +#define EARLY_UART +#ifdef EARLY_UART /* * Debug UART can be used from here if required: * @@ -124,6 +140,25 @@ void board_init_f(ulong dummy) printch('\n'); #endif +#ifdef CONFIG_ROCKCHIP_USB_UART + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[0], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); +#endif + ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 43350e38b1..0198c6c65f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -202,13 +202,13 @@ void board_init_f(ulong dummy) ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { - debug("Pinctrl init failed: %d\n", ret); + pr_err("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { - debug("DRAM init failed: %d\n", ret); + pr_err("DRAM init failed: %d\n", ret); return; } } diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c new file mode 100644 index 0000000000..3412f2c063 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108-board.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2015 Google, Inc + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rv1108_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + const void *blob = gd->fdt_blob; + bool matched = false; + int node, phy_node; + u32 grf_phy_offset; + const char *mode; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb"); + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3066-usb"); + } + + if (!matched) { + debug("usb_otg device not found\n"); + return -ENODEV; + } + + rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + node = fdtdec_lookup_phandle(blob, node, "phys"); + if (node <= 0) { + debug("phys node not found\n"); + return -ENODEV; + } + + phy_node = fdt_parent_offset(blob, node); + if (phy_node <= 0) { + debug("usb phy node not found\n"); + return -ENODEV; + } + + rv1108_otg_data.phy_of_node = phy_node; + grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); + + /* find the grf node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rv1108-grf"); + if (node <= 0) { + debug("grf node not found\n"); + return -ENODEV; + } + + rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node, + "reg"); + + return dwc2_udc_probe(&rv1108_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index bb9e3faa29..2725e9fcc3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -6,6 +6,7 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000 #define SOCFPGA_STM_ADDRESS 0xfc000000 #define SOCFPGA_DAP_ADDRESS 0xff000000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570a04..26609927c8 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -6,6 +6,8 @@ #ifndef _MISC_H_ #define _MISC_H_ +#include <asm/sections.h> + void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode); struct bsel { @@ -23,6 +25,13 @@ static inline void socfpga_fpga_add(void) {} #ifdef CONFIG_TARGET_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); +static inline bool socfpga_is_booting_from_fpga(void) +{ + if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) && + (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS)) + return true; + return false; +} #endif #ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..5fa40937c4 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void) void socfpga_sdram_remap_zero(void) { + u32 remap; + socfpga_nic301_slave_ns(); /* @@ -187,7 +189,12 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + remap = 0x1; /* remap.mpuzero */ + /* Keep fpga bridge enabled when running from FPGA onchip RAM */ + if (socfpga_is_booting_from_fpga()) + remap |= 0x8; /* remap.hps2fpga */ + writel(remap, &nic301_regs->remap); + writel(0x1, &pl310->pl310_addr_filter_start); } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..ccdc661d05 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -92,8 +92,11 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); - /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); + + if (!socfpga_is_booting_from_fpga()) { + /* Put FPGA bridges into reset too. */ + socfpga_bridges_reset(1); + } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -163,5 +166,6 @@ void board_init_f(ulong dummy) hang(); } - socfpga_bridges_reset(1); + if (!socfpga_is_booting_from_fpga()) + socfpga_bridges_reset(1); } diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 8cfacc7a13..2b072cc65e 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -251,7 +251,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, }; -struct socfpga_sdram_io_config io_config = { +static const struct socfpga_sdram_io_config io_config = { .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP, .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP, .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP, @@ -269,7 +269,7 @@ struct socfpga_sdram_io_config io_config = { .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS, }; -struct socfpga_sdram_misc_config misc_config = { +static const struct socfpga_sdram_misc_config misc_config = { .afi_rate_ratio = AFI_RATE_RATIO, .calib_lfifo_offset = CALIB_LFIFO_OFFSET, .calib_vfifo_offset = CALIB_VFIFO_OFFSET, diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 560dc9b25d..3c54f5106d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -230,6 +230,7 @@ config MACH_SUN8I_A83T select PHY_SUN4I_USB select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE + select MMC_SUNXI_HAS_MODE_SWITCH select SUPPORT_SPL config MACH_SUN8I_H3 @@ -281,6 +282,7 @@ config MACH_SUN50I select SUN6I_PRCM select SUNXI_DE2 select SUNXI_GEN_SUN6I + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index d9aa0c6d7e..1da2727f98 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -334,7 +334,7 @@ unsigned long sunxi_dram_init(void) struct dram_para para = { .cs1 = 0, .bank = 1, - .rank = 1, + .rank = 2, .rows = 15, .bus_width = 16, .page_size = 2048, |