diff options
Diffstat (limited to 'arch/arm')
22 files changed, 556 insertions, 75 deletions
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts index f3f022c375..5ed2133e78 100644 --- a/arch/arm/dts/am335x-guardian.dts +++ b/arch/arm/dts/am335x-guardian.dts @@ -32,12 +32,19 @@ gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; + pinctrl-0 = <&guardian_button_pins>; - button21 { + select-button { + label = "guardian-select-button"; + linux,code = <KEY_5>; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + power-button { label = "guardian-power-button"; linux,code = <KEY_POWER>; - gpios = <&gpio2 21 0>; + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; wakeup-source; }; }; @@ -45,19 +52,12 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led1 { - label = "green:heartbeat"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; + pinctrl-0 = <&guardian_led_pins>; - led2 { - label = "green:mmc0"; + life-led { + label = "guardian:life-led"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; + linux,default-trigger = "heartbeat"; default-state = "off"; }; }; @@ -140,22 +140,25 @@ gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; + gpmc,we-off-ns = <15>; + gpmc,oe-on-ns = <1>; + gpmc,oe-off-ns = <15>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* @@ -199,18 +202,8 @@ }; partition@6 { - label = "u-boot-env"; - reg = <0x300000 0x40000>; - }; - - partition@7 { - label = "u-boot-env.backup1"; - reg = <0x340000 0x40000>; - }; - - partition@8 { label = "UBI"; - reg = <0x380000 0x1fc80000>; + reg = <0x300000 0x1fd00000>; }; }; }; @@ -326,6 +319,12 @@ status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + &usb { status = "okay"; }; @@ -354,7 +353,7 @@ &am33xx_pinmux { pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &gpio_pins>; + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < @@ -368,16 +367,25 @@ >; }; - gpio_keys_pins: pinmux_gpio_keys_pins { + guardian_button_pins: pinmux_gpio_keys_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) >; }; - gpio_pins: pinmux_gpio_pins { + guardian_interface_pins: pinmux_guardian_interface_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7) >; }; @@ -452,10 +460,9 @@ >; }; - leds_pins: pinmux_leds_pins { + guardian_led_pins: pinmux_leds_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) >; }; @@ -487,6 +494,13 @@ >; }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi new file mode 100644 index 0000000000..cc9569af03 --- /dev/null +++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +/ { + xtal25mhz: xtal25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c0 { + cdce913: cdce913@65 { + compatible = "ti,cdce913"; + reg = <0x65>; + clocks = <&xtal25mhz>; + #clock-cells = <1>; + xtal-load-pf = <0>; + }; +}; diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi index 3aa9195e44..50fe09cfc3 100644 --- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi @@ -9,6 +9,12 @@ ocp { u-boot,dm-spl; }; + + xtal25mhz: xtal25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &uart0 { @@ -17,6 +23,14 @@ &i2c0 { u-boot,dm-spl; + + cdce913: cdce913@65 { + compatible = "ti,cdce913"; + reg = <0x65>; + clocks = <&xtal25mhz>; + #clock-cells = <1>; + xtal-load-pf = <0>; + }; }; &mmc1 { diff --git a/arch/arm/dts/am571x-idk-u-boot.dtsi b/arch/arm/dts/am571x-idk-u-boot.dtsi new file mode 100644 index 0000000000..65199200ed --- /dev/null +++ b/arch/arm/dts/am571x-idk-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am572x-idk-u-boot.dtsi b/arch/arm/dts/am572x-idk-u-boot.dtsi new file mode 100644 index 0000000000..65199200ed --- /dev/null +++ b/arch/arm/dts/am572x-idk-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am574x-idk-u-boot.dtsi b/arch/arm/dts/am574x-idk-u-boot.dtsi new file mode 100644 index 0000000000..65199200ed --- /dev/null +++ b/arch/arm/dts/am574x-idk-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi new file mode 100644 index 0000000000..b07aea0048 --- /dev/null +++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "omap5-u-boot.dtsi" + +/ { + xtal25mhz: xtal25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { + cdce913: cdce913@65 { + compatible = "ti,cdce913"; + reg = <0x65>; + clocks = <&xtal25mhz>; + #clock-cells = <1>; + xtal-load-pf = <0>; + }; +}; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c9bfd9b80f..c42e7553c7 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ */ &cbass_mcu { @@ -26,4 +26,42 @@ clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + lockstep-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xFF>; + resets = <&k3_reset 159 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xFF>; + resets = <&k3_reset 245 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; }; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index e73b9aa6b1..573ead0b4d 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -17,6 +17,11 @@ bootargs = "earlycon=ns16550a,mmio32,0x02800000"; }; + aliases { + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &mcu_r5fss0_core1; + }; + memory@80000000 { device_type = "memory"; /* 4G RAM */ diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 7ed307f0d8..e31ed4fe64 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -16,6 +16,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; }; @@ -118,6 +119,14 @@ status = "okay"; }; +&mcu_uart0 { + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <48000000>; + status = "okay"; +}; + &main_uart0 { power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; @@ -141,6 +150,16 @@ u-boot,dm-spl; }; + mcu_uart0_pins_default: mcu_uart0_pins_default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ + >; + u-boot,dm-spl; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index b5b8c3c5cc..c978cabd13 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -12,6 +12,18 @@ stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + + aliases { + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &mcu_r5fss0_core1; + remoteproc2 = &main_r5fss0_core0; + remoteproc3 = &main_r5fss0_core1; + remoteproc4 = &main_r5fss1_core0; + remoteproc5 = &main_r5fss1_core1; + remoteproc6 = &c66_0; + remoteproc7 = &c66_1; + remoteproc8 = &c71_0; + }; }; &wkup_uart0 { @@ -19,6 +31,10 @@ status = "disabled"; }; +&main_uart0 { + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + &main_uart3 { /* UART not brought out */ status = "disabled"; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 3445784293..6bd59bac52 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -228,4 +228,115 @@ ti,trm-icp = <0x8>; dma-coherent; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721e-r5fss"; + lockstep-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5c00000 0x00008000>, + <0x5c10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x06 0xFF>; + resets = <&k3_reset 245 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5d00000 0x00008000>, + <0x5d10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <246>; + ti,sci-proc-ids = <0x07 0xFF>; + resets = <&k3_reset 246 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721e-r5fss"; + lockstep-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5e00000 0x00008000>, + <0x5e10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <247>; + ti,sci-proc-ids = <0x08 0xFF>; + resets = <&k3_reset 247 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5f00000 0x00008000>, + <0x5f10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <248>; + ti,sci-proc-ids = <0x09 0xFF>; + resets = <&k3_reset 248 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; + + c66_0: dsp@4d80800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x80800000 0x00 0x00048000>, + <0x4d 0x80e00000 0x00 0x00008000>, + <0x4d 0x80f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <142>; + ti,sci-proc-ids = <0x03 0xFF>; + resets = <&k3_reset 142 1>; + }; + + c66_1: dsp@4d81800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x81800000 0x00 0x00048000>, + <0x4d 0x81e00000 0x00 0x00008000>, + <0x4d 0x81f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <143>; + ti,sci-proc-ids = <0x04 0xFF>; + resets = <&k3_reset 143 1>; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721e-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <15>; + ti,sci-proc-ids = <0x30 0xFF>; + resets = <&k3_reset 15 1>; + }; }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 1175fa9a50..b958b5b3c1 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -69,4 +69,42 @@ clocks = <&k3_clks 149 0>; clock-names = "fclk"; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721e-r5fss"; + lockstep-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721e-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <250>; + ti,sci-proc-ids = <0x01 0xFF>; + resets = <&k3_reset 250 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721e-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <251>; + ti,sci-proc-ids = <0x02 0xFF>; + resets = <&k3_reset 251 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; }; diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index de1c1cc73f..5583241943 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -66,6 +66,27 @@ config SYS_K3_BOOT_CORE_ID int default 16 +config K3_EARLY_CONS + bool "Activate to allow for an early console during SPL" + depends on SPL + help + Turn this option on to enable an early console functionality in SPL + before the main console is being brought up. This can be useful in + situations where the main console is dependent on System Firmware + (SYSFW) being up and running, which is usually not the case during + the very early stages of boot. Using this early console functionality + will allow for an alternate serial port to be used to support things + like UART-based boot and early diagnostic messages until the main + console is ready to get activated. + +config K3_EARLY_CONS_IDX + depends on K3_EARLY_CONS + int "Index of serial device to use for SPL early console" + default 1 + help + Use this option to set the index of the serial device to be used + for the early console during SPL execution. + config K3_LOAD_SYSFW bool depends on SPL diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 82778d2197..7f908eee80 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -14,7 +14,7 @@ #ifdef CONFIG_SOC_K3_AM6 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) /* ToDo: Add 64bit IO */ struct mm_region am654_mem_map[NR_MMU_REGIONS] = { @@ -28,7 +28,19 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x80000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, + .phys = 0xa0000000UL, + .size = 0x02100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa2100000UL, + .phys = 0xa2100000UL, + .size = 0x5df00000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -68,13 +80,13 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0xa0000000UL, .phys = 0xa0000000UL, - .size = 0x0bc00000UL, + .size = 0x1bc00000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | PTE_BLOCK_NON_SHARE }, { - .virt = 0xabc00000UL, - .phys = 0xabc00000UL, - .size = 0x54400000UL, + .virt = 0xbbc00000UL, + .phys = 0xbbc00000UL, + .size = 0x44400000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index c16afc654f..f8274b39d6 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -14,19 +14,48 @@ #include <linux/soc/ti/ti_sci_protocol.h> #include <fdt_support.h> #include <asm/arch/sys_proto.h> +#include <asm/hardware.h> +#include <asm/io.h> struct ti_sci_handle *get_ti_sci_handle(void) { struct udevice *dev; int ret; - ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev); + ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, + DM_GET_DRIVER(ti_sci), &dev); if (ret) panic("Failed to get SYSFW (%d)\n", ret); return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev); } +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_K3_EARLY_CONS +int early_console_init(void) +{ + struct udevice *dev; + int ret; + + gd->baudrate = CONFIG_BAUDRATE; + + ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX, + &dev); + if (ret) { + printf("Error getting serial dev for early console! (%d)\n", + ret); + return ret; + } + + gd->cur_serial_dev = dev; + gd->flags |= GD_FLG_SERIAL_READY; + gd->have_console = 1; + + return 0; +} +#endif + #ifdef CONFIG_SYS_K3_SPL_ATF void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { @@ -164,3 +193,43 @@ void reset_cpu(ulong ignored) { } #endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 soc, rev; + char *name; + + soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) & + DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT; + rev = (readl(CTRLMMR_WKUP_JTAG_ID) & + JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; + + printf("SoC: "); + switch (soc) { + case AM654: + name = "AM654"; + break; + case J721E: + name = "J721E"; + break; + default: + name = "Unknown Silicon"; + }; + + printf("%s PG ", name); + switch (rev) { + case REV_PG1_0: + name = "1.0"; + break; + case REV_PG2_0: + name = "2.0"; + break; + default: + name = "Unknown Revision"; + }; + printf("%s\n", name); + + return 0; +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index ac7e80d9af..8f9a023921 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -8,4 +8,11 @@ #include <asm/armv7_mpu.h> +#define AM654 2 +#define J721E 4 + +#define REV_PG1_0 0 +#define REV_PG2_0 1 + void setup_k3_mpu_regions(void); +int early_console_init(void); diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 4e629822aa..d670d5a56e 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -13,4 +13,22 @@ #ifdef CONFIG_SOC_K3_J721E #include "j721e_hardware.h" #endif + +/* Assuming these addresses and definitions stay common across K3 devices */ +#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 +#define DEVICE_ID_FAMILY_SHIFT 26 +#define DEVICE_ID_FAMILY_MASK (0x3f << 26) +#define DEVICE_ID_BASE_SHIFT 11 +#define DEVICE_ID_BASE_MASK (0x1fff << 11) +#define DEVICE_ID_SPEED_SHIFT 6 +#define DEVICE_ID_SPEED_MASK (0x1f << 6) +#define DEVICE_ID_TEMP_SHIFT 3 +#define DEVICE_ID_TEMP_MASK (0x7 << 3) + +#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define JTAG_ID_VARIANT_SHIFT 28 +#define JTAG_ID_VARIANT_MASK (0xf << 28) +#define JTAG_ID_PARTNO_SHIFT 12 +#define JTAG_ID_PARTNO_MASK (0x7ff << 1) + #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 7a482bdc8a..5903bbe12a 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -12,6 +12,9 @@ #include <remoteproc.h> #include <linux/soc/ti/ti_sci_protocol.h> #include <asm/arch/sys_proto.h> +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; /* Name of the FIT image nodes for SYSFW and its config data */ #define SYSFW_FIRMWARE "sysfw.bin" @@ -215,6 +218,24 @@ void k3_sysfw_loader(void (*config_pm_done_callback)(void)) #endif break; #endif +#if CONFIG_IS_ENABLED(YMODEM_SUPPORT) + case BOOT_DEVICE_UART: +#ifdef CONFIG_K3_EARLY_CONS + /* + * Establish a serial console if not yet available as required + * for UART-based boot. For this use the early console feature + * that allows setting up a UART for use before SYSFW has been + * brought up. Note that the associated UART module's clocks + * must have gotten enabled by the ROM bootcode which will be + * the case when continuing to boot serially from the same + * UART that the ROM loaded the initial bootloader from. + */ + if (!gd->have_console) + early_console_init(); +#endif + ret = spl_ymodem_load_image(&spl_image, &bootdev); + break; +#endif default: panic("Loading SYSFW image from device %u not supported!\n", bootdev.boot_device); diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 7f6b344c82..39d9c2873b 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -89,6 +89,7 @@ config TARGET_AM335X_SHC config TARGET_AM335X_GUARDIAN bool "Support am335x based guardian board from bosch" + select BOARD_LATE_INIT select DM select DM_SERIAL select DM_GPIO diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index b384343a3f..290f9dcdb0 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -348,52 +348,63 @@ static void dra7_reset_ddr_data(u32 base, u32 size) static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 rgn, size; + u32 rgn, rgn_start, size, ctrl_reg; /* ECC available only on dra76x EMIF1 */ if ((base != EMIF1_BASE) || !is_dra76x()) return; if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) { + /* Disable high-order interleaving */ + clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); + +#ifdef CONFIG_DRA7XX + /* Clear the status flags and other history */ + writel(readl(&emif->emif_1b_ecc_err_cnt), + &emif->emif_1b_ecc_err_cnt); + writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); + writel(0x2, &emif->emif_1b_ecc_err_addr_log); + writel(0x1, &emif->emif_2b_ecc_err_addr_log); + writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | + EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | + EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, + &emif->emif_irqstatus_sys); +#endif writel(regs->emif_ecc_address_range_1, &emif->emif_ecc_address_range_1); writel(regs->emif_ecc_address_range_2, &emif->emif_ecc_address_range_2); - writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); + + /* Disable RMW and ECC verification for read accesses */ + ctrl_reg = (regs->emif_ecc_ctrl_reg & + ~EMIF_ECC_REG_RMW_EN_MASK) | + EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK; + writel(ctrl_reg, &emif->emif_ecc_ctrl_reg); /* Set region1 memory with 0 */ - rgn = ((regs->emif_ecc_address_range_1 & - EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + - CONFIG_SYS_SDRAM_BASE; + rgn_start = (regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; + rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & - EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; if (regs->emif_ecc_ctrl_reg & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) dra7_reset_ddr_data(rgn, size); /* Set region2 memory with 0 */ - rgn = ((regs->emif_ecc_address_range_2 & - EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + - CONFIG_SYS_SDRAM_BASE; + rgn_start = (regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; + rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & - EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; if (regs->emif_ecc_ctrl_reg & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) dra7_reset_ddr_data(rgn, size); -#ifdef CONFIG_DRA7XX - /* Clear the status flags and other history */ - writel(readl(&emif->emif_1b_ecc_err_cnt), - &emif->emif_1b_ecc_err_cnt); - writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); - writel(0x1, &emif->emif_2b_ecc_err_addr_log); - writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | - EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | - EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, - &emif->emif_irqstatus_sys); -#endif + /* Default value enables RMW and ECC verification */ + writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); } } diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index e2abb7d058..9eda57c450 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -202,8 +202,9 @@ void __recalibrate_iodelay_end(int ret) return; } - if (!ret) - ret = isolate_io(DEISOLATE_IO); + /* Deisolate IO if it is already isolated */ + if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK) + isolate_io(DEISOLATE_IO); /* lock IODELAY CONFIG registers */ writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + @@ -240,6 +241,12 @@ void __recalibrate_iodelay_end(int ret) debug("IODELAY: IO delay recalibration successfully completed\n"); } + /* If there is an error during iodelay recalibration, SoC is in a bad + * state. Do not progress any further. + */ + if (ret) + hang(); + return; } |