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-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/armada-3720-uDPU.dts18
-rw-r--r--arch/arm/dts/cros-ec-keyboard.dtsi10
-rw-r--r--arch/arm/dts/cros-ec-sbs.dtsi39
-rw-r--r--arch/arm/dts/imx8mm-evk-u-boot.dtsi12
-rw-r--r--arch/arm/dts/imx8mm-verdin-u-boot.dtsi12
-rw-r--r--arch/arm/dts/imx8mm.dtsi76
-rw-r--r--arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi12
-rw-r--r--arch/arm/dts/imx8mp-evk-u-boot.dtsi12
-rw-r--r--arch/arm/dts/imx8mq-phanbell.dts417
-rw-r--r--arch/arm/dts/px30-evb-u-boot.dtsi80
-rw-r--r--arch/arm/dts/px30-evb.dts1
-rw-r--r--arch/arm/dts/px30-firefly-u-boot.dtsi82
-rw-r--r--arch/arm/dts/px30-u-boot.dtsi90
-rw-r--r--arch/arm/dts/rk3328-evb-u-boot.dtsi39
-rw-r--r--arch/arm/dts/rk3328-evb.dts220
-rw-r--r--arch/arm/dts/rk3328-roc-cc-u-boot.dtsi47
-rw-r--r--arch/arm/dts/rk3328-roc-cc.dts354
-rw-r--r--arch/arm/dts/rk3328-rock64-u-boot.dtsi11
-rw-r--r--arch/arm/dts/rk3328-rock64.dts132
-rw-r--r--arch/arm/dts/rk3328-u-boot.dtsi4
-rw-r--r--arch/arm/dts/rk3328.dtsi1415
-rw-r--r--arch/arm/dts/rk3399-evb-u-boot.dtsi12
-rw-r--r--arch/arm/dts/rk3399-evb.dts522
-rw-r--r--arch/arm/dts/rk3399-ficus.dts6
-rw-r--r--arch/arm/dts/rk3399-firefly.dts251
-rw-r--r--arch/arm/dts/rk3399-gru-bob.dts16
-rw-r--r--arch/arm/dts/rk3399-gru-chromebook.dtsi40
-rw-r--r--arch/arm/dts/rk3399-gru-kevin.dts34
-rw-r--r--arch/arm/dts/rk3399-gru.dtsi89
-rw-r--r--arch/arm/dts/rk3399-khadas-edge.dtsi3
-rw-r--r--arch/arm/dts/rk3399-leez-p710.dts36
-rw-r--r--arch/arm/dts/rk3399-nanopc-t4.dts47
-rw-r--r--arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi8
-rw-r--r--arch/arm/dts/rk3399-nanopi-m4-2gb.dts66
-rw-r--r--arch/arm/dts/rk3399-nanopi4.dtsi66
-rw-r--r--arch/arm/dts/rk3399-orangepi.dts79
-rw-r--r--arch/arm/dts/rk3399-puma-u-boot.dtsi31
-rw-r--r--arch/arm/dts/rk3399-puma.dtsi578
-rw-r--r--arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi6
-rw-r--r--arch/arm/dts/rk3399-roc-pc-mezzanine.dts93
-rw-r--r--arch/arm/dts/rk3399-roc-pc-u-boot.dtsi36
-rw-r--r--arch/arm/dts/rk3399-roc-pc.dts3
-rw-r--r--arch/arm/dts/rk3399-roc-pc.dtsi35
-rw-r--r--arch/arm/dts/rk3399-rock-pi-4.dts129
-rw-r--r--arch/arm/dts/rk3399-rock960.dts49
-rw-r--r--arch/arm/dts/rk3399-rock960.dtsi13
-rw-r--r--arch/arm/dts/rk3399-rockpro64.dts751
-rw-r--r--arch/arm/dts/rk3399-rockpro64.dtsi797
-rw-r--r--arch/arm/dts/rk3399-u-boot.dtsi7
-rw-r--r--arch/arm/dts/rk3399.dtsi583
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h7
-rw-r--r--arch/arm/include/asm/arch-imx8/sci/rpc.h86
-rw-r--r--arch/arm/include/asm/arch-imx8/sci/sci.h10
-rw-r--r--arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h3
-rw-r--r--arch/arm/include/asm/arch-imx8/sci/types.h6
-rw-r--r--arch/arm/include/asm/arch-imx8/snvs_security_sc.h11
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock_imx8mm.h5
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock_imx8mq.h3
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h17
-rw-r--r--arch/arm/lib/Makefile2
-rw-r--r--arch/arm/mach-imx/cpu.c38
-rw-r--r--arch/arm/mach-imx/imx8/Kconfig13
-rw-r--r--arch/arm/mach-imx/imx8/Makefile1
-rw-r--r--arch/arm/mach-imx/imx8/ahab.c15
-rw-r--r--arch/arm/mach-imx/imx8/misc.c8
-rw-r--r--arch/arm/mach-imx/imx8/parse-container.c18
-rw-r--r--arch/arm/mach-imx/imx8/snvs_security_sc.c923
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig6
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mm.c73
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mq.c57
-rw-r--r--arch/arm/mach-imx/imx8m/clock_slice.c810
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c78
-rw-r--r--arch/arm/mach-imx/spl.c49
74 files changed, 7104 insertions, 2608 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c123bd6da..559d3ab6a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
@@ -125,12 +126,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-leez-p710.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
+ rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-roc-pc.dtb \
+ rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb
@@ -733,6 +736,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-verdin.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
+ imx8mq-phanbell.dtb \
imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts
index 683dac2a7c..07c7b91175 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -109,11 +109,11 @@
&comphy {
phy0 {
phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-speed = <PHY_SPEED_3_125G>;
};
phy1 {
phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-speed = <PHY_SPEED_3_125G>;
};
phy2 {
@@ -125,22 +125,16 @@
&eth0 {
pinctrl-0 = <&pcie_pins>;
status = "okay";
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
phy = <&ethphy0>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
};
&eth1 {
status = "okay";
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
phy = <&ethphy1>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
};
&i2c0 {
diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi
index 9c7fb0acae..4a0c1037fb 100644
--- a/arch/arm/dts/cros-ec-keyboard.dtsi
+++ b/arch/arm/dts/cros-ec-keyboard.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Keyboard dts fragment for devices that use cros-ec-keyboard
*
* Copyright (c) 2014 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
@@ -22,6 +19,7 @@
MATRIX_KEY(0x00, 0x02, KEY_F1)
MATRIX_KEY(0x00, 0x03, KEY_B)
MATRIX_KEY(0x00, 0x04, KEY_F10)
+ MATRIX_KEY(0x00, 0x05, KEY_RO)
MATRIX_KEY(0x00, 0x06, KEY_N)
MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
@@ -34,6 +32,7 @@
MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
MATRIX_KEY(0x01, 0x09, KEY_F9)
MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+ MATRIX_KEY(0x01, 0x0c, KEY_HENKAN)
MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
MATRIX_KEY(0x02, 0x01, KEY_TAB)
@@ -45,6 +44,7 @@
MATRIX_KEY(0x02, 0x07, KEY_102ND)
MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
MATRIX_KEY(0x02, 0x09, KEY_F8)
+ MATRIX_KEY(0x02, 0x0a, KEY_YEN)
MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
MATRIX_KEY(0x03, 0x02, KEY_F2)
@@ -52,7 +52,9 @@
MATRIX_KEY(0x03, 0x04, KEY_F5)
MATRIX_KEY(0x03, 0x06, KEY_6)
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+ MATRIX_KEY(0x03, 0x09, KEY_F13)
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+ MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)
MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
MATRIX_KEY(0x04, 0x01, KEY_A)
diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi
index dfe5ea6ca2..71f5c5ecce 100644
--- a/arch/arm/dts/cros-ec-sbs.dtsi
+++ b/arch/arm/dts/cros-ec-sbs.dtsi
@@ -1,8 +1,45 @@
-// SPDX-License-Identifier: GPL-2.0
/*
* Smart battery dts fragment for devices that use cros-ec-sbs
*
* Copyright (c) 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
&i2c_tunnel {
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 3502602fbb..b5c12105a9 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
* Copyright 2019 NXP
*/
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
@@ -117,3 +125,7 @@
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index e60b9faee4..fe6bb9bf03 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -3,6 +3,14 @@
* Copyright 2020 Toradex
*/
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
@@ -105,3 +113,7 @@
&usdhc3 {
u-boot,dm-spl;
};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 8aafad2449..1e5e11592f 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -12,7 +12,6 @@
#include "imx8mm-pinfunc.h"
/ {
- compatible = "fsl,imx8mm";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -141,11 +140,6 @@
};
};
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -233,7 +227,7 @@
ranges = <0x0 0x0 0x0 0x3e000000>;
aips1: bus@30000000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
@@ -394,7 +388,7 @@
};
sdma2: dma-controller@302c0000 {
- compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
@@ -405,7 +399,7 @@
};
sdma3: dma-controller@302b0000 {
- compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
@@ -439,7 +433,7 @@
};
anatop: anatop@30360000 {
- compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
+ compatible = "fsl,imx8mm-anatop", "syscon";
reg = <0x30360000 0x10000>;
};
@@ -479,14 +473,18 @@
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
- <&clk IMX8MM_VIDEO_PLL1>;
+ <&clk IMX8MM_VIDEO_PLL1>,
+ <&clk IMX8MM_AUDIO_PLL1>,
+ <&clk IMX8MM_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <0>,
<400000000>,
<400000000>,
<750000000>,
- <594000000>;
+ <594000000>,
+ <393216000>,
+ <361267200>;
};
src: reset-controller@30390000 {
@@ -498,7 +496,7 @@
};
aips2: bus@30400000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30400000 0x30400000 0x400000>;
@@ -557,7 +555,7 @@
};
aips3: bus@30800000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30800000 0x30800000 0x400000>;
@@ -638,6 +636,36 @@
status = "disabled";
};
+ crypto: crypto@30900000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30900000 0x40000>;
+ ranges = <0 0x30900000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_AHB>,
+ <&clk IMX8MM_CLK_IPG_ROOT>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
@@ -698,8 +726,6 @@
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -728,8 +754,6 @@
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -737,11 +761,11 @@
};
sdma1: dma-controller@30bd0000 {
- compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+ compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
- <&clk IMX8MM_CLK_SDMA1_ROOT>;
+ <&clk IMX8MM_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
@@ -776,7 +800,7 @@
};
aips4: bus@32c00000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
@@ -859,6 +883,16 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ ddrc: memory-controller@3d400000 {
+ compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+ reg = <0x3d400000 0x400000>;
+ clock-names = "core", "pll", "alt", "apb";
+ clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+ <&clk IMX8MM_DRAM_PLL>,
+ <&clk IMX8MM_CLK_DRAM_ALT>,
+ <&clk IMX8MM_CLK_DRAM_APB>;
+ };
+
ddr-pmu@3d800000 {
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 8d61597e0c..4419679d4c 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
* Copyright 2019 NXP
*/
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
@@ -90,3 +98,7 @@
&usdhc3 {
u-boot,dm-spl;
};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 4675ada0a0..24a93ac2d6 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
* Copyright 2019 NXP
*/
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
@@ -119,3 +127,7 @@
&usdhc3 {
u-boot,dm-spl;
};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts
new file mode 100644
index 0000000000..4892ad5ee1
--- /dev/null
+++ b/arch/arm/dts/imx8mq-phanbell.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "Google i.MX8MQ Phanbell";
+ compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0x40000000>;
+ };
+
+ pmic_osc: clock-pmic {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic_osc";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pmic@4b {
+ compatible = "rohm,bd71837";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ #clock-cells = <0>;
+ clocks = <&pmic_osc>;
+ clock-output-names = "pmic_clk";
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <900000>;
+ rohm,dvs-idle-voltage = <900000>;
+ rohm,dvs-suspend-voltage = <800000>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ rohm,dvs-run-voltage = <900000>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ rohm,dvs-run-voltage = <900000>;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7: BUCK7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck8: BUCK8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7: LDO7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <50>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi
index a2a2c07dcc..61b1433af9 100644
--- a/arch/arm/dts/px30-evb-u-boot.dtsi
+++ b/arch/arm/dts/px30-evb-u-boot.dtsi
@@ -1,84 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
-/ {
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
+#include "px30-u-boot.dtsi"
- chosen {
- u-boot,spl-boot-order = &emmc, &sdmmc;
- };
-};
-
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
-&uart2 {
- clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
-};
-
-&uart5 {
- clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-
- /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
- u-boot,spl-fifo-mode;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-
- /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
- u-boot,spl-fifo-mode;
-};
-
-&grf {
- u-boot,dm-pre-reloc;
-};
-
-&pmugrf {
- u-boot,dm-pre-reloc;
-};
-
-&xin24m {
- u-boot,dm-pre-reloc;
-};
-
-&cru {
- u-boot,dm-pre-reloc;
-};
-
-&pmucru {
- u-boot,dm-pre-reloc;
-};
-
-&saradc {
- u-boot,dm-pre-reloc;
+&rng {
status = "okay";
};
-
-&gpio0 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio1 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio2 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
index d886f17242..4134e2ee13 100644
--- a/arch/arm/dts/px30-evb.dts
+++ b/arch/arm/dts/px30-evb.dts
@@ -8,7 +8,6 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "px30.dtsi"
-#include "px30-evb-u-boot.dtsi"
/ {
model = "Rockchip PX30 EVB";
diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi
index bb782b4e2d..aea9f4d6e5 100644
--- a/arch/arm/dts/px30-firefly-u-boot.dtsi
+++ b/arch/arm/dts/px30-firefly-u-boot.dtsi
@@ -1,84 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
-/ {
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
-
- chosen {
- u-boot,spl-boot-order = &emmc, &sdmmc;
- };
-};
-
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
-&uart2 {
- clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
-};
-
-&uart5 {
- clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-
- /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
- u-boot,spl-fifo-mode;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-
- /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
- u-boot,spl-fifo-mode;
-};
-
-&grf {
- u-boot,dm-pre-reloc;
-};
-
-&pmugrf {
- u-boot,dm-pre-reloc;
-};
-
-&xin24m {
- u-boot,dm-pre-reloc;
-};
-
-&cru {
- u-boot,dm-pre-reloc;
-};
-
-&pmucru {
- u-boot,dm-pre-reloc;
-};
-
-&saradc {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&gpio0 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio1 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio2 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
+#include "px30-u-boot.dtsi"
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
new file mode 100644
index 0000000000..029c8fbd8d
--- /dev/null
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = &emmc, &sdmmc;
+ };
+
+ rng: rng@ff0b0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff0b0000 0x0 0x4000>;
+ status = "disabled";
+ };
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart5 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&pmugrf {
+ u-boot,dm-pre-reloc;
+};
+
+&xin24m {
+ u-boot,dm-pre-reloc;
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&pmucru {
+ u-boot,dm-pre-reloc;
+};
+
+&saradc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4a827063c5..4bfa0c2330 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -6,6 +6,45 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
+/{
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host_xhci";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gmac2phy {
+ /* Integrated PHY unsupported by U-boot */
+ status = "broken";
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index a2ee838fcd..6abc6f4a86 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -11,40 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
- stdout-path = &uart2;
+ stdout-path = "serial2:1500000n8";
};
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- vcc3v3_sdmmc: sdmmc-pwren {
+ dc_12v: dc-12v {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
};
- vcc5v0_otg: vcc5v0-otg-drv {
+ vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
};
- vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_host_xhci";
- gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@@ -55,96 +66,60 @@
};
};
-&saradc {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
- status = "okay";
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
- supports-emmc;
- disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
-&gmac2io {
+&gmac2phy {
phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- tx_delay = <0x26>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb20_otg {
- vbus-supply = <&vcc5v0_otg>;
- status = "okay";
};
&i2c1 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
- status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
- gpio-controller;
- #gpio-cells = <2>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <6001>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -155,19 +130,18 @@
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <6001>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
+ regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
@@ -177,32 +151,32 @@
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
- vdd_18: LDO_REG1 {
- regulator-name = "vdd_18";
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
- vcc_18emmc: LDO_REG2 {
- regulator-name = "vcc_18emmc";
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -213,8 +187,8 @@
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@@ -227,9 +201,71 @@
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
rockchip,pins =
- <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <150000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
new file mode 100644
index 0000000000..e929d86e30
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc_host1_5v>;
+ status = "okay";
+};
+
+/*
+ * This makes XHCI responsible for toggling VBUS. This is needed to work
+ * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
+ * work, depending on how VBUS is configured. Having USB 3.0 seems better.
+ */
+&vcc_host1_5v {
+ /delete-property/ regulator-always-on;
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
new file mode 100644
index 0000000000..8d553c9218
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Firefly roc-rk3328-cc";
+ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_host1_5v";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "firefly:blue:power";
+ linux,default-trigger = "heartbeat";
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ mode = <0x23>;
+ };
+
+ user {
+ label = "firefly:yellow:user";
+ linux,default-trigger = "mmc1";
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ mode = <0x05>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,aal;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,rxpbl = <0x4>;
+ snps,txpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_sdio>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index e5946d2d2d..8318bf4e60 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -12,5 +12,16 @@
};
&usb_host0_xhci {
+ vbus-supply = <&vcc_host_5v>;
status = "okay";
};
+
+/*
+ * This makes XHCI responsible for toggling VBUS. This is needed to work
+ * around an issue where either XHCI only works with USB 2.0 or OTG doesn't
+ * work, depending on how VBUS is configured. Having USB 3.0 seems better.
+ */
+&vcc_host_5v {
+ /delete-property/ regulator-always-on;
+ /delete-property/ regulator-boot-on;
+};
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index a78eb4ac6f..ebf3eb222e 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -43,6 +43,17 @@
vin-supply = <&vcc_sys>;
};
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_host1_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -51,6 +62,56 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc0";
+ };
+
+ standby {
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "rockchip,rk3328";
+ dais = <&i2s1_p0
+ &spdif_p0>;
+ };
+
+ spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port {
+ dit_p0_0: endpoint {
+ remote-endpoint = <&spdif_p0_0>;
+ };
+ };
+ };
+};
+
+&codec {
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ port@0 {
+ codec_p0_0: endpoint {
+ remote-endpoint = <&i2s1_p0_0>;
+ };
+ };
};
&cpu0 {
@@ -98,16 +159,26 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
- rk805: rk805@18 {
+ rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
@@ -169,7 +240,7 @@
};
vcc_18: LDO_REG1 {
- regulator-name = "vdd_18";
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -181,7 +252,7 @@
};
vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc_18emmc";
+ regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -207,6 +278,18 @@
};
};
+&i2s1 {
+ status = "okay";
+
+ i2s1_p0: port {
+ i2s1_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&codec_p0_0>;
+ };
+ };
+};
+
&io_domains {
status = "okay";
@@ -220,6 +303,12 @@
};
&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -245,6 +334,17 @@
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+
+ spdif_p0: port {
+ spdif_p0_0: endpoint {
+ remote-endpoint = <&dit_p0_0>;
+ };
+ };
+};
+
&spi0 {
status = "okay";
@@ -257,10 +357,28 @@
};
};
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
&uart2 {
status = "okay";
};
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
&usb20_otg {
dr_mode = "host";
status = "okay";
@@ -273,3 +391,11 @@
&usb_host0_ohci {
status = "okay";
};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 6d5b3ec06e..c69e13e11e 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -62,3 +62,7 @@
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
+
+&usb20_otg {
+ hnp-srp-disable;
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 060c84e6c0..945387e579 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rk3328-cru.h>
@@ -8,6 +8,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3328-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3328";
@@ -24,9 +27,8 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- mmc2 = &sdmmc_ext;
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
};
cpus {
@@ -35,29 +37,71 @@
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
-// clocks = <&cru ARMCLK>;
+ next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
+
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
+
cpu2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
+
cpu3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
};
};
@@ -65,39 +109,72 @@
compatible = "operating-points-v2";
opp-shared;
- opp@408000000 {
+ opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
- opp@816000000 {
+ opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <40000>;
};
- opp@1008000000 {
+ opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <40000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <40000>;
};
- opp@1296000000 {
+ opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1300000>;
clock-latency-ns = <40000>;
};
};
+ amba: bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dmac: dmac@ff1f0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff1f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+ };
+
+ analog_sound: analog-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "Analog";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
@@ -107,8 +184,29 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "HDMI";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
psci {
- compatible = "arm,psci-1.0";
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
@@ -134,8 +232,8 @@
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 11>, <&dmac 12>;
- #dma-cells = <2>;
dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -146,8 +244,8 @@
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 14>, <&dmac 15>;
- #dma-cells = <2>;
dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -158,16 +256,8 @@
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 0>, <&dmac 1>;
- #dma-cells = <2>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2s2m0_mclk
- &i2s2m0_sclk
- &i2s2m0_lrcktx
- &i2s2m0_lrckrx
- &i2s2m0_sdo
- &i2s2m0_sdi>;
- pinctrl-1 = <&i2s2m0_sleep>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -178,10 +268,31 @@
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac 10>;
- #dma-cells = <1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdifm2_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm: pdm@ff040000 {
+ compatible = "rockchip,pdm";
+ reg = <0x0 0xff040000 0x0 0x1000>;
+ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 16>;
+ dma-names = "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-1 = <&pdmm0_clk_sleep
+ &pdmm0_sdi0_sleep
+ &pdmm0_sdi1_sleep
+ &pdmm0_sdi2_sleep
+ &pdmm0_sdi3_sleep>;
status = "disabled";
};
@@ -193,6 +304,39 @@
compatible = "rockchip,rk3328-io-voltage-domain";
status = "disabled";
};
+
+ grf_gpio: grf-gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ power: power-controller {
+ compatible = "rockchip,rk3328-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_hevc@RK3328_PD_HEVC {
+ reg = <RK3328_PD_HEVC>;
+ };
+ pd_video@RK3328_PD_VIDEO {
+ reg = <RK3328_PD_VIDEO>;
+ };
+ pd_vpu@RK3328_PD_VPU {
+ reg = <RK3328_PD_VPU>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ };
+ };
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x5c8>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
};
uart0: serial@ff110000 {
@@ -201,12 +345,12 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
dmas = <&dmac 2>, <&dmac 3>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -215,13 +359,13 @@
reg = <0x0 0xff120000 0x0 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
+ clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 4>, <&dmac 5>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -231,22 +375,17 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
dmas = <&dmac 6>, <&dmac 7>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
- pmu: power-management@ff140000 {
- compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xff140000 0x0 0x1000>;
- };
-
i2c0: i2c@ff150000 {
- compatible = "rockchip,rk3328-i2c";
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff150000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -259,7 +398,7 @@
};
i2c1: i2c@ff160000 {
- compatible = "rockchip,rk3328-i2c";
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff160000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -272,7 +411,7 @@
};
i2c2: i2c@ff170000 {
- compatible = "rockchip,rk3328-i2c";
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff170000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -285,7 +424,7 @@
};
i2c3: i2c@ff180000 {
- compatible = "rockchip,rk3328-i2c";
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff180000 0x0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -306,7 +445,6 @@
clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 8>, <&dmac 9>;
- #dma-cells = <2>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
@@ -317,28 +455,141 @@
compatible = "snps,dw-wdt";
reg = <0x0 0xff1a0000 0x0 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_WDT>;
+ };
+
+ pwm0: pwm@ff1b0000 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0000 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ pwm1: pwm@ff1b0010 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0010 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
- dmac: dmac@ff1f0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff1f0000 0x0 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
+ pwm2: pwm@ff1b0020 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0020 0x0 0x10>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff1b0030 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0030 0x0 0x10>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmir_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>;
+ polling-delay = <1000>;
+ sustainable-power = <1000>;
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ target: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ soc_crit: soc-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
+ };
+ };
+
+ };
+
+ tsadc: tsadc@ff250000 {
+ compatible = "rockchip,rk3328-tsadc";
+ reg = <0x0 0xff250000 0x0 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru SCLK_TSADC>;
+ assigned-clock-rates = <50000>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <100000>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ efuse: efuse@ff260000 {
+ compatible = "rockchip,rk3328-efuse";
+ reg = <0x0 0xff260000 0x0 0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru SCLK_EFUSE>;
+ clock-names = "pclk_efuse";
+ rockchip,efuse-size = <0x20>;
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ logic_leakage: logic-leakage@19 {
+ reg = <0x19 0x1>;
+ };
+ efuse_cpu_version: cpu-version@1a {
+ reg = <0x1a 0x1>;
+ bits = <3 3>;
};
};
- saradc: saradc@ff280000 {
- compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
+ saradc: adc@ff280000 {
+ compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
@@ -349,6 +600,169 @@
status = "disabled";
};
+ gpu: gpu@ff300000 {
+ compatible = "rockchip,rk3328-mali", "arm,mali-450";
+ reg = <0x0 0xff300000 0x0 0x40000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&cru SRST_GPU_A>;
+ };
+
+ h265e_mmu: iommu@ff330200 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff330200 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "h265e_mmu";
+ clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vepu_mmu: iommu@ff340800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff340800 0x0 0x40>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu: video-codec@ff350000 {
+ compatible = "rockchip,rk3328-vpu";
+ reg = <0x0 0xff350000 0x0 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3328_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@ff350800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff350800 0x0 0x40>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3328_PD_VPU>;
+ };
+
+ rkvdec_mmu: iommu@ff360480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvdec_mmu";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vop: vop@ff370000 {
+ compatible = "rockchip,rk3328-vop";
+ reg = <0x0 0xff370000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@ff373f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff373f00 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmi: hdmi@ff3c0000 {
+ compatible = "rockchip,rk3328-dw-hdmi";
+ reg = <0x0 0xff3c0000 0x0 0x20000>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>,
+ <&cru SCLK_HDMI_SFC>,
+ <&cru SCLK_RTC32K>;
+ clock-names = "iahb",
+ "isfr",
+ "cec";
+ phys = <&hdmiphy>;
+ phy-names = "hdmi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+ hdmi_in: port {
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+ };
+ };
+
+ codec: codec@ff410000 {
+ compatible = "rockchip,rk3328-codec";
+ reg = <0x0 0xff410000 0x0 0x1000>;
+ clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
+ clock-names = "pclk", "mclk";
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmiphy: phy@ff430000 {
+ compatible = "rockchip,rk3328-hdmi-phy";
+ reg = <0x0 0xff430000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
+ clock-names = "sysclk", "refoclk", "refpclk";
+ clock-output-names = "hdmi_phy";
+ #clock-cells = <0>;
+ nvmem-cells = <&efuse_cpu_version>;
+ nvmem-cell-names = "cpu-version";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -356,6 +770,12 @@
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
+ /*
+ * CPLL should run at 1200, but that is to high for
+ * the initial dividers of most of its children.
+ * We need set cpll child clk div first,
+ * and then set the cpll frequency.
+ */
<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
<&cru SCLK_UART1>, <&cru SCLK_UART2>,
@@ -371,15 +791,7 @@
<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
- <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
- <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
- <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
- <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
- <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
- <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
+ <&cru SCLK_RTC32K>;
assigned-clock-parents =
<&cru HDMIPHY>, <&cru PLL_APLL>,
<&cru PLL_GPLL>, <&xin24m>,
@@ -400,55 +812,85 @@
<150000000>, <75000000>,
<75000000>, <150000000>,
<75000000>, <75000000>,
- <300000000>, <100000000>,
- <300000000>, <200000000>,
- <400000000>, <500000000>,
- <200000000>, <300000000>,
- <300000000>, <250000000>,
- <200000000>, <100000000>,
- <24000000>, <100000000>,
- <150000000>, <50000000>,
- <32768>, <32768>;
+ <32768>;
};
- sdmmc: rksdmmc@ff500000 {
+ usb2phy_grf: syscon@ff450000 {
+ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3328-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&xin24m>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
+ sdmmc: mmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
- max-frequency = <150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
status = "disabled";
};
- sdio: dwmmc@ff510000 {
+ sdio: mmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
status = "disabled";
};
- emmc: rksdmmc@ff520000 {
+ emmc: mmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>;
- max-frequency = <150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
status = "disabled";
};
gmac2io: ethernet@ff540000 {
compatible = "rockchip,rk3328-gmac";
reg = <0x0 0xff540000 0x0 0x10000>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
@@ -461,13 +903,56 @@
"pclk_mac";
resets = <&cru SRST_GMAC2IO_A>;
reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,txpbl = <0x4>;
status = "disabled";
};
+ gmac2phy: ethernet@ff550000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff550000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
+ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
+ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
+ <&cru SCLK_MAC2PHY_OUT>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_macphy";
+ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
+ reset-names = "stmmaceth", "mac-phy";
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
+ snps,txpbl = <0x4>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clocks = <&cru SCLK_MAC2PHY_OUT>;
+ resets = <&cru SRST_MACPHY>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
+ phy-is-integrated;
+ };
+ };
+ };
+
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
status = "disabled";
};
@@ -475,31 +960,38 @@
compatible = "generic-ohci";
reg = <0x0 0xff5d0000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
status = "disabled";
};
+ /*
+ * U-boot Specific Change
+ *
+ * The OTG controller must come after the USB host pair for it
+ * to work. This is likely due to lack of support for the USB
+ * PHYs. This must be manually changed after each device tree
+ * sync. There is no clean way to handle this in -u-boot.dtsi
+ * files.
+ */
usb20_otg: usb@ff580000 {
compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- hnp-srp-disable;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
status = "disabled";
};
- sdmmc_ext: rksdmmc@ff5f0000 {
- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff5f0000 0x0 0x4000>;
- max-frequency = <150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- gic: interrupt-controller@ffb70000 {
+ gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
@@ -647,654 +1139,576 @@
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- <2 24 RK_FUNC_1 &pcfg_pull_none>,
- <2 25 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
+ <2 RK_PD1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins =
- <2 4 RK_FUNC_2 &pcfg_pull_none>,
- <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
+ <2 RK_PA5 2 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins =
- <2 13 RK_FUNC_1 &pcfg_pull_none>,
- <2 14 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
+ <2 RK_PB6 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins =
- <0 5 RK_FUNC_2 &pcfg_pull_none>,
- <0 6 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
+ <0 RK_PA6 2 &pcfg_pull_none>;
};
i2c3_gpio: i2c3-gpio {
rockchip,pins =
- <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi_i2c {
hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
+ <0 RK_PA6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pdm-0 {
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_fsync: pdmm0-fsync {
+ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_clk_sleep: pdmm0-clk-sleep {
+ rockchip,pins =
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
+ rockchip,pins =
+ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
+ rockchip,pins =
+ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
+ rockchip,pins =
+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
+ rockchip,pins =
+ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+
+ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
rockchip,pins =
- <0 5 RK_FUNC_1 &pcfg_pull_none>,
- <0 6 RK_FUNC_1 &pcfg_pull_none>;
+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
+ tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins =
- <1 9 RK_FUNC_1 &pcfg_pull_up>,
- <1 8 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
+ <1 RK_PB0 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
- rockchip,pins =
- <1 11 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
- rockchip,pins =
- <1 10 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
};
uart0_rts_gpio: uart0-rts-gpio {
- rockchip,pins =
- <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins =
- <3 4 RK_FUNC_4 &pcfg_pull_up>,
- <3 6 RK_FUNC_4 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
+ <3 RK_PA6 4 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
- rockchip,pins =
- <3 7 RK_FUNC_4 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
- rockchip,pins =
- <3 5 RK_FUNC_4 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
};
uart1_rts_gpio: uart1-rts-gpio {
- rockchip,pins =
- <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart2-0 {
uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- <1 0 RK_FUNC_2 &pcfg_pull_up>,
- <1 1 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
+ <1 RK_PA1 2 &pcfg_pull_none>;
};
};
uart2-1 {
uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- <2 0 RK_FUNC_1 &pcfg_pull_up>,
- <2 1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
+ <2 RK_PA1 1 &pcfg_pull_none>;
};
};
spi0-0 {
spi0m0_clk: spi0m0-clk {
- rockchip,pins =
- <2 8 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
};
spi0m0_cs0: spi0m0-cs0 {
- rockchip,pins =
- <2 11 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
};
spi0m0_tx: spi0m0-tx {
- rockchip,pins =
- <2 9 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
};
spi0m0_rx: spi0m0-rx {
- rockchip,pins =
- <2 10 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
};
spi0m0_cs1: spi0m0-cs1 {
- rockchip,pins =
- <2 12 RK_FUNC_1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
};
};
spi0-1 {
spi0m1_clk: spi0m1-clk {
- rockchip,pins =
- <3 23 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
};
spi0m1_cs0: spi0m1-cs0 {
- rockchip,pins =
- <3 26 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
};
spi0m1_tx: spi0m1-tx {
- rockchip,pins =
- <3 25 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
};
spi0m1_rx: spi0m1-rx {
- rockchip,pins =
- <3 24 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
};
spi0m1_cs1: spi0m1-cs1 {
- rockchip,pins =
- <3 27 RK_FUNC_2 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
};
};
spi0-2 {
spi0m2_clk: spi0m2-clk {
- rockchip,pins =
- <3 0 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
};
spi0m2_cs0: spi0m2-cs0 {
- rockchip,pins =
- <3 8 RK_FUNC_3 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
};
spi0m2_tx: spi0m2-tx {
- rockchip,pins =
- <3 1 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
};
spi0m2_rx: spi0m2-rx {
- rockchip,pins =
- <3 2 RK_FUNC_4 &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_mclk: i2s1-mclk {
- rockchip,pins =
- <2 15 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
};
i2s1_sclk: i2s1-sclk {
- rockchip,pins =
- <2 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
};
i2s1_lrckrx: i2s1-lrckrx {
- rockchip,pins =
- <2 16 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
};
i2s1_lrcktx: i2s1-lrcktx {
- rockchip,pins =
- <2 17 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
};
i2s1_sdi: i2s1-sdi {
- rockchip,pins =
- <2 19 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
};
i2s1_sdo: i2s1-sdo {
- rockchip,pins =
- <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
};
i2s1_sdio1: i2s1-sdio1 {
- rockchip,pins =
- <2 20 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
};
i2s1_sdio2: i2s1-sdio2 {
- rockchip,pins =
- <2 21 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
};
i2s1_sdio3: i2s1-sdio3 {
- rockchip,pins =
- <2 22 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
};
i2s1_sleep: i2s1-sleep {
rockchip,pins =
- <2 15 RK_FUNC_GPIO &pcfg_input_high>,
- <2 16 RK_FUNC_GPIO &pcfg_input_high>,
- <2 17 RK_FUNC_GPIO &pcfg_input_high>,
- <2 18 RK_FUNC_GPIO &pcfg_input_high>,
- <2 19 RK_FUNC_GPIO &pcfg_input_high>,
- <2 20 RK_FUNC_GPIO &pcfg_input_high>,
- <2 21 RK_FUNC_GPIO &pcfg_input_high>,
- <2 22 RK_FUNC_GPIO &pcfg_input_high>,
- <2 23 RK_FUNC_GPIO &pcfg_input_high>;
+ <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
};
};
i2s2-0 {
i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins =
- <1 21 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
};
i2s2m0_sclk: i2s2m0-sclk {
- rockchip,pins =
- <1 22 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
};
i2s2m0_lrckrx: i2s2m0-lrckrx {
- rockchip,pins =
- <1 26 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
};
i2s2m0_lrcktx: i2s2m0-lrcktx {
- rockchip,pins =
- <1 23 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
};
i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins =
- <1 24 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
};
i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins =
- <1 25 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
};
i2s2m0_sleep: i2s2m0-sleep {
rockchip,pins =
- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
- <1 22 RK_FUNC_GPIO &pcfg_input_high>,
- <1 26 RK_FUNC_GPIO &pcfg_input_high>,
- <1 23 RK_FUNC_GPIO &pcfg_input_high>,
- <1 24 RK_FUNC_GPIO &pcfg_input_high>,
- <1 25 RK_FUNC_GPIO &pcfg_input_high>;
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
};
};
i2s2-1 {
i2s2m1_mclk: i2s2m1-mclk {
- rockchip,pins =
- <1 21 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
};
i2s2m1_sclk: i2s2m1-sclk {
- rockchip,pins =
- <3 0 RK_FUNC_6 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
};
i2s2m1_lrckrx: i2sm1-lrckrx {
- rockchip,pins =
- <3 8 RK_FUNC_6 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
};
i2s2m1_lrcktx: i2s2m1-lrcktx {
- rockchip,pins =
- <3 8 RK_FUNC_4 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
};
i2s2m1_sdi: i2s2m1-sdi {
- rockchip,pins =
- <3 2 RK_FUNC_6 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
};
i2s2m1_sdo: i2s2m1-sdo {
- rockchip,pins =
- <3 1 RK_FUNC_6 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
};
i2s2m1_sleep: i2s2m1-sleep {
rockchip,pins =
- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
- <3 0 RK_FUNC_GPIO &pcfg_input_high>,
- <3 8 RK_FUNC_GPIO &pcfg_input_high>,
- <3 2 RK_FUNC_GPIO &pcfg_input_high>,
- <3 1 RK_FUNC_GPIO &pcfg_input_high>;
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
};
};
spdif-0 {
spdifm0_tx: spdifm0-tx {
- rockchip,pins =
- <0 27 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
spdif-1 {
spdifm1_tx: spdifm1-tx {
- rockchip,pins =
- <2 17 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
};
};
spdif-2 {
spdifm2_tx: spdifm2-tx {
- rockchip,pins =
- <0 2 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
};
};
sdmmc0-0 {
sdmmc0m0_pwren: sdmmc0m0-pwren {
- rockchip,pins =
- <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
};
sdmmc0m0_gpio: sdmmc0m0-gpio {
- rockchip,pins =
- <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
sdmmc0-1 {
sdmmc0m1_pwren: sdmmc0m1-pwren {
- rockchip,pins =
- <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
};
sdmmc0m1_gpio: sdmmc0m1-gpio {
- rockchip,pins =
- <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
- rockchip,pins =
- <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
};
sdmmc0_cmd: sdmmc0-cmd {
- rockchip,pins =
- <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
};
sdmmc0_dectn: sdmmc0-dectn {
- rockchip,pins =
- <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
};
sdmmc0_wrprt: sdmmc0-wrprt {
- rockchip,pins =
- <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
};
sdmmc0_bus1: sdmmc0-bus1 {
- rockchip,pins =
- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
};
sdmmc0_bus4: sdmmc0-bus4 {
- rockchip,pins =
- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
- <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
- <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
- <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
+ <1 RK_PA1 1 &pcfg_pull_up_8ma>,
+ <1 RK_PA2 1 &pcfg_pull_up_8ma>,
+ <1 RK_PA3 1 &pcfg_pull_up_8ma>;
};
sdmmc0_gpio: sdmmc0-gpio {
rockchip,pins =
- <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
sdmmc0ext {
sdmmc0ext_clk: sdmmc0ext-clk {
- rockchip,pins =
- <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
+ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
};
sdmmc0ext_cmd: sdmmc0ext-cmd {
- rockchip,pins =
- <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
};
sdmmc0ext_wrprt: sdmmc0ext-wrprt {
- rockchip,pins =
- <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
};
sdmmc0ext_dectn: sdmmc0ext-dectn {
- rockchip,pins =
- <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
};
sdmmc0ext_bus1: sdmmc0ext-bus1 {
- rockchip,pins =
- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
};
sdmmc0ext_bus4: sdmmc0ext-bus4 {
rockchip,pins =
- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
- <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
- <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
- <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ <3 RK_PA4 3 &pcfg_pull_up_4ma>,
+ <3 RK_PA5 3 &pcfg_pull_up_4ma>,
+ <3 RK_PA6 3 &pcfg_pull_up_4ma>,
+ <3 RK_PA7 3 &pcfg_pull_up_4ma>;
};
sdmmc0ext_gpio: sdmmc0ext-gpio {
rockchip,pins =
- <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
sdmmc1 {
sdmmc1_clk: sdmmc1-clk {
- rockchip,pins =
- <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
+ rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
};
sdmmc1_cmd: sdmmc1-cmd {
- rockchip,pins =
- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
};
sdmmc1_pwren: sdmmc1-pwren {
- rockchip,pins =
- <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
};
sdmmc1_wrprt: sdmmc1-wrprt {
- rockchip,pins =
- <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
};
sdmmc1_dectn: sdmmc1-dectn {
- rockchip,pins =
- <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
};
sdmmc1_bus1: sdmmc1-bus1 {
- rockchip,pins =
- <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
};
sdmmc1_bus4: sdmmc1-bus4 {
- rockchip,pins =
- <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
+ <1 RK_PB7 1 &pcfg_pull_up_8ma>,
+ <1 RK_PC0 1 &pcfg_pull_up_8ma>,
+ <1 RK_PC1 1 &pcfg_pull_up_8ma>;
};
sdmmc1_gpio: sdmmc1-gpio {
rockchip,pins =
- <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
emmc {
emmc_clk: emmc-clk {
- rockchip,pins =
- <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins =
- <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
};
emmc_pwren: emmc-pwren {
- rockchip,pins =
- <3 22 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
};
emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- <3 20 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
};
emmc_bus1: emmc-bus1 {
- rockchip,pins =
- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins =
- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD6 2 &pcfg_pull_up_12ma>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins =
- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
- <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD6 2 &pcfg_pull_up_12ma>,
+ <2 RK_PD7 2 &pcfg_pull_up_12ma>,
+ <3 RK_PC0 2 &pcfg_pull_up_12ma>,
+ <3 RK_PC1 2 &pcfg_pull_up_12ma>,
+ <3 RK_PC2 2 &pcfg_pull_up_12ma>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins =
- <2 4 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins =
- <2 5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
- rockchip,pins =
- <2 6 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
};
};
pwmir {
pwmir_pin: pwmir-pin {
- rockchip,pins =
- <2 2 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- gmac-0 {
- rgmiim0_pins: rgmiim0-pins {
- rockchip,pins =
- /* mac_txclk */
- <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_rxclk */
- <0 10 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdio */
- <0 11 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txen */
- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_clk */
- <0 24 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxdv */
- <0 25 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdc */
- <0 19 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <0 14 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <0 15 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd1 */
- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_rxd3 */
- <0 20 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd2 */
- <0 21 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd3 */
- <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd2 */
- <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
- };
-
- rmiim0_pins: rmiim0-pins {
- rockchip,pins =
- /* mac_mdio */
- <0 11 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txen */
- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_clk */
- <0 24 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxer */
- <0 13 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxdv */
- <0 25 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdc */
- <0 19 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <0 14 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <0 15 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd1 */
- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
};
};
@@ -1302,157 +1716,128 @@
rgmiim1_pins: rgmiim1-pins {
rockchip,pins =
/* mac_txclk */
- <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PB4 2 &pcfg_pull_none_8ma>,
/* mac_rxclk */
- <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB5 2 &pcfg_pull_none_4ma>,
/* mac_mdio */
- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC3 2 &pcfg_pull_none_4ma>,
/* mac_txen */
- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PD1 2 &pcfg_pull_none_8ma>,
/* mac_clk */
- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC5 2 &pcfg_pull_none_4ma>,
/* mac_rxdv */
- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC6 2 &pcfg_pull_none_4ma>,
/* mac_mdc */
- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC7 2 &pcfg_pull_none_4ma>,
/* mac_rxd1 */
- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB2 2 &pcfg_pull_none_4ma>,
/* mac_rxd0 */
- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB3 2 &pcfg_pull_none_4ma>,
/* mac_txd1 */
- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PB0 2 &pcfg_pull_none_8ma>,
/* mac_txd0 */
- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PB1 2 &pcfg_pull_none_8ma>,
/* mac_rxd3 */
- <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB6 2 &pcfg_pull_none_4ma>,
/* mac_rxd2 */
- <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB7 2 &pcfg_pull_none_4ma>,
/* mac_txd3 */
- <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PC0 2 &pcfg_pull_none_8ma>,
/* mac_txd2 */
- <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PC1 2 &pcfg_pull_none_8ma>,
/* mac_txclk */
- <0 8 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB0 1 &pcfg_pull_none_8ma>,
/* mac_txen */
- <0 12 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB4 1 &pcfg_pull_none_8ma>,
/* mac_clk */
- <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PD0 1 &pcfg_pull_none_4ma>,
/* mac_txd1 */
- <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC0 1 &pcfg_pull_none_8ma>,
/* mac_txd0 */
- <0 17 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC1 1 &pcfg_pull_none_8ma>,
/* mac_txd3 */
- <0 23 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC7 1 &pcfg_pull_none_8ma>,
/* mac_txd2 */
- <0 22 RK_FUNC_1 &pcfg_pull_none>;
+ <0 RK_PC6 1 &pcfg_pull_none_8ma>;
};
rmiim1_pins: rmiim1-pins {
rockchip,pins =
/* mac_mdio */
- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
/* mac_txen */
- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PD1 2 &pcfg_pull_none_12ma>,
/* mac_clk */
- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
/* mac_rxer */
- <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PD0 2 &pcfg_pull_none_2ma>,
/* mac_rxdv */
- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC6 2 &pcfg_pull_none_2ma>,
/* mac_mdc */
- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
/* mac_rxd1 */
- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB2 2 &pcfg_pull_none_2ma>,
/* mac_rxd0 */
- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ <1 RK_PB3 2 &pcfg_pull_none_2ma>,
/* mac_txd1 */
- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PB0 2 &pcfg_pull_none_12ma>,
/* mac_txd0 */
- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ <1 RK_PB1 2 &pcfg_pull_none_12ma>,
/* mac_mdio */
- <0 11 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB3 1 &pcfg_pull_none>,
/* mac_txen */
- <0 12 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB4 1 &pcfg_pull_none>,
/* mac_clk */
- <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PD0 1 &pcfg_pull_none>,
/* mac_mdc */
- <0 19 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC3 1 &pcfg_pull_none>,
/* mac_txd1 */
- <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC0 1 &pcfg_pull_none>,
/* mac_txd0 */
- <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ <0 RK_PC1 1 &pcfg_pull_none>;
};
};
gmac2phy {
- fephyled_speed100: fephyled-speed100 {
- rockchip,pins =
- <0 31 RK_FUNC_1 &pcfg_pull_none>;
- };
-
fephyled_speed10: fephyled-speed10 {
- rockchip,pins =
- <0 30 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
};
fephyled_duplex: fephyled-duplex {
- rockchip,pins =
- <0 30 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- fephyled_rxm0: fephyled-rxm0 {
- rockchip,pins =
- <0 29 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- fephyled_txm0: fephyled-txm0 {
- rockchip,pins =
- <0 29 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- fephyled_linkm0: fephyled-linkm0 {
- rockchip,pins =
- <0 28 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
};
fephyled_rxm1: fephyled-rxm1 {
- rockchip,pins =
- <2 25 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
};
fephyled_txm1: fephyled-txm1 {
- rockchip,pins =
- <2 25 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
};
fephyled_linkm1: fephyled-linkm1 {
- rockchip,pins =
- <2 24 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
};
};
tsadc_pin {
tsadc_int: tsadc-int {
- rockchip,pins =
- <2 13 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
};
tsadc_gpio: tsadc-gpio {
- rockchip,pins =
- <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi_pin {
hdmi_cec: hdmi-cec {
- rockchip,pins =
- <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
};
hdmi_hpd: hdmi-hpd {
- rockchip,pins =
- <0 4 RK_FUNC_1 &pcfg_pull_down>;
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
};
};
@@ -1460,29 +1845,29 @@
dvp_d2d9_m0:dvp-d2d9-m0 {
rockchip,pins =
/* cif_d0 */
- <3 4 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA4 2 &pcfg_pull_none>,
/* cif_d1 */
- <3 5 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA5 2 &pcfg_pull_none>,
/* cif_d2 */
- <3 6 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA6 2 &pcfg_pull_none>,
/* cif_d3 */
- <3 7 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA7 2 &pcfg_pull_none>,
/* cif_d4 */
- <3 8 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PB0 2 &pcfg_pull_none>,
/* cif_d5m0 */
- <3 9 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PB1 2 &pcfg_pull_none>,
/* cif_d6m0 */
- <3 10 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PB2 2 &pcfg_pull_none>,
/* cif_d7m0 */
- <3 11 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PB3 2 &pcfg_pull_none>,
/* cif_href */
- <3 1 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA1 2 &pcfg_pull_none>,
/* cif_vsync */
- <3 0 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA0 2 &pcfg_pull_none>,
/* cif_clkoutm0 */
- <3 3 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA3 2 &pcfg_pull_none>,
/* cif_clkin */
- <3 2 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PA2 2 &pcfg_pull_none>;
};
};
@@ -1490,29 +1875,29 @@
dvp_d2d9_m1:dvp-d2d9-m1 {
rockchip,pins =
/* cif_d0 */
- <3 4 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA4 2 &pcfg_pull_none>,
/* cif_d1 */
- <3 5 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA5 2 &pcfg_pull_none>,
/* cif_d2 */
- <3 6 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA6 2 &pcfg_pull_none>,
/* cif_d3 */
- <3 7 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA7 2 &pcfg_pull_none>,
/* cif_d4 */
- <3 8 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PB0 2 &pcfg_pull_none>,
/* cif_d5m1 */
- <2 16 RK_FUNC_4 &pcfg_pull_none>,
+ <2 RK_PC0 4 &pcfg_pull_none>,
/* cif_d6m1 */
- <2 17 RK_FUNC_4 &pcfg_pull_none>,
+ <2 RK_PC1 4 &pcfg_pull_none>,
/* cif_d7m1 */
- <2 18 RK_FUNC_4 &pcfg_pull_none>,
+ <2 RK_PC2 4 &pcfg_pull_none>,
/* cif_href */
- <3 1 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA1 2 &pcfg_pull_none>,
/* cif_vsync */
- <3 0 RK_FUNC_2 &pcfg_pull_none>,
+ <3 RK_PA0 2 &pcfg_pull_none>,
/* cif_clkoutm1 */
- <2 15 RK_FUNC_4 &pcfg_pull_none>,
+ <2 RK_PB7 4 &pcfg_pull_none>,
/* cif_clkin */
- <3 2 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PA2 2 &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index ccb33d34d1..e5659d7999 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -11,3 +11,15 @@
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};
+
+&rng {
+ status = "okay";
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&rk808 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 4129e902a8..694b0d08d6 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -1,86 +1,18 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
- "google,rk3399evb-rev2";
-
- chosen {
- stdout-path = &uart2;
- };
-
- vdd_center: vdd-center {
- compatible = "pwm-regulator";
- pwms = <&pwm3 0 25000 1>;
- regulator-name = "vdd_center";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-init-microvolt = <950000>;
- regulator-always-on;
- regulator-boot-on;
- status = "okay";
- };
-
- vccsys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vccsys";
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_host: vcc5v0-host-en {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
- };
-
- vcc5v0_typec0: vcc5v0-typec0-en {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_typec0";
- gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- vcc5v0_typec1: vcc5v0-typec1-en {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_typec1";
- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
+ compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
backlight: backlight {
compatible = "pwm-backlight";
- power-supply = <&vccsys>;
- enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
@@ -116,18 +48,98 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
pwms = <&pwm0 0 25000 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- pwm-delay-us = <10000>;
- status = "disabled";
};
- panel:panel {
- compatible = "simple-panel";
- power-supply = <&vcc33_lcd>;
+ edp_panel: edp-panel {
+ compatible ="lg,lp079qx1-sp0v";
backlight = <&backlight>;
- /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
- status = "disabled";
+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vcc3v3_s0>;
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vdd_center: vdd-center {
+ compatible = "pwm-regulator";
+ pwms = <&pwm3 0 25000 0>;
+ regulator-name = "vdd_center";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ status = "okay";
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+};
+
+&edp {
+ status = "okay";
+ force-hpd;
+
+ ports {
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
};
};
@@ -135,24 +147,253 @@
status = "okay";
};
-&pwm0 {
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
status = "okay";
};
-&pwm2 {
+&i2c0 {
status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_tp: LDO_REG2 {
+ regulator-name = "vcc3v0_tp";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sd: LDO_REG4 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
};
-&pwm3 {
+&pwm0 {
status = "okay";
};
-&saradc {
+&pwm2 {
status = "okay";
};
-&sdmmc {
- bus-width = <4>;
+&pwm3 {
status = "okay";
};
@@ -164,117 +405,76 @@
status = "okay";
};
-&uart2 {
- status = "okay";
+&pcie_phy {
+ status = "disabled";
};
-&usb_host0_ehci {
- status = "okay";
+&pcie0 {
+ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "disabled";
};
-&usb_host0_ohci {
+&u2phy0 {
status = "okay";
};
-&usbdrd3_0 {
- vbus-supply = <&vcc5v0_typec0>;
+&u2phy0_host {
+ phy-supply = <&vcc5v0_host>;
status = "okay";
};
-&usb_host1_ehci {
+&u2phy1 {
status = "okay";
};
-&usb_host1_ohci {
+&u2phy1_host {
+ phy-supply = <&vcc5v0_host>;
status = "okay";
};
-&usbdrd3_1 {
- vbus-supply = <&vcc5v0_typec1>;
+&uart2 {
status = "okay";
};
-&i2c0 {
+&usb_host0_ehci {
status = "okay";
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <100>;
- u-boot,dm-pre-reloc;
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- clock-output-names = "xin32k", "wifibt_32kin";
- interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- reg = <0x1b>;
- rockchip,system-power-controller;
- #clock-cells = <1>;
- u-boot,dm-pre-reloc;
- status = "okay";
+};
- vcc12-supply = <&vcc3v3_sys>;
+&usb_host0_ohci {
+ status = "okay";
+};
- regulators {
- vcc33_lcd: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc33_lcd";
- };
- };
- };
+&usb_host1_ehci {
+ status = "okay";
};
-&mipi_dsi {
- status = "disabled";
- rockchip,panel = <&panel>;
- display-timings {
- timing0 {
- bits-per-pixel = <24>;
- clock-frequency = <160000000>;
- hfront-porch = <120>;
- hsync-len = <20>;
- hback-porch = <21>;
- hactive = <1200>;
- vfront-porch = <21>;
- vsync-len = <3>;
- vback-porch = <18>;
- vactive = <1920>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
+&usb_host1_ohci {
+ status = "okay";
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
- <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
+ };
- pmic_dvs2: pmic-dvs2 {
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
- <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
-&gmac {
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
index 6b059bd7a0..ebe2ee77ba 100644
--- a/arch/arm/dts/rk3399-ficus.dts
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -146,6 +146,12 @@
};
};
+&spi1 {
+ /* On both Low speed and High speed expansion */
+ cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index 89c67fd24c..d63faf38cc 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -1,19 +1,20 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
/ {
model = "Firefly-RK3399 Board";
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
chosen {
- stdout-path = &uart2;
+ stdout-path = "serial2:1500000n8";
};
backlight: backlight {
@@ -63,6 +64,48 @@
#clock-cells = <0>;
};
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
rt5640-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,rt5640-codec";
@@ -102,15 +145,27 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie_drv>;
+ pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc3v3-sys {
@@ -120,32 +175,29 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
};
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
+ pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
+ vin-supply = <&vcc_sys>;
};
- vcc5v0_sys: vcc5v0-sys {
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
+ regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
+ vin-supply = <&dc_12v>;
};
vdd_log: vdd-log {
@@ -156,16 +208,7 @@
regulator-boot-on;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
- regulator-init-microvolt = <950000>;
- };
-
- vccadc_ref: vccadc-ref {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_sys>;
};
};
@@ -201,15 +244,22 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
- phy-supply = <&vcc_phy>;
+ phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x33>;
- rx_delay = <0x45>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
@@ -231,16 +281,16 @@
rockchip,system-power-controller;
wakeup-source;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
@@ -301,12 +351,12 @@
};
};
- vcc3v0_tp: LDO_REG2 {
- regulator-name = "vcc3v0_tp";
+ vcc2v8_dvp: LDO_REG2 {
+ regulator-name = "vcc2v8_dvp";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -324,8 +374,8 @@
};
};
- vcc_sd: LDO_REG4 {
- regulator-name = "vcc_sd";
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -382,7 +432,7 @@
};
};
- vcc3v3_s3: SWITCH_REG1 {
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
@@ -412,7 +462,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -429,7 +479,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -476,19 +526,16 @@
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
- #sound-dai-cells = <0>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
- #sound-dai-cells = <0>;
status = "okay";
};
&i2s2 {
- #sound-dai-cells = <0>;
status = "okay";
};
@@ -497,7 +544,7 @@
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sd>;
+ sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
@@ -509,7 +556,7 @@
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn>;
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
@@ -532,7 +579,7 @@
};
pcie {
- pcie_drv: pcie-drv {
+ pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -570,10 +617,26 @@
};
usb2 {
- host_vbus_drv: host-vbus-drv {
+ vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wifi {
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ work_led_gpio: work_led-gpio {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_gpio: diy_led-gpio {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm0 {
@@ -585,24 +648,70 @@
};
&saradc {
- vref-supply = <&vccadc_ref>;
+ vref-supply = <&vcca1v8_s3>;
status = "okay";
};
+&sdio0 {
+ /* WiFi & BT combo module Ampak AP6356S */
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+
+ /* Power supply */
+ vqmmc-supply = &vcc1v8_s3; /* IO line */
+ vmmc-supply = &vcc_sdio; /* card's power */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ brcm,drive-strength = <5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
&sdmmc {
bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
- keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
@@ -662,3 +771,37 @@
&usb_host1_ohci {
status = "okay";
};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts
index 1ee0dc0d9f..e6c1c94c8d 100644
--- a/arch/arm/dts/rk3399-gru-bob.dts
+++ b/arch/arm/dts/rk3399-gru-bob.dts
@@ -18,11 +18,11 @@
"google,bob", "google,gru", "rockchip,rk3399";
edp_panel: edp-panel {
- compatible = "boe,nv101wxmn51", "simple-panel";
+ compatible = "boe,nv101wxmn51";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
- ports {
+ port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@@ -68,12 +68,22 @@
&spi0 {
status = "okay";
+
+ cr50@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&h1_int_od_l>;
+ spi-max-frequency = <800000>;
+ };
};
&pinctrl {
tpm {
h1_int_od_l: h1-int-od-l {
- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi
index c6495adcca..1384dabbdf 100644
--- a/arch/arm/dts/rk3399-gru-chromebook.dtsi
+++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi
@@ -194,20 +194,25 @@
backlight: backlight {
compatible = "pwm-backlight";
- brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
- 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44
- 45 46 47 48 49 50 51 52 53 54 55 56 57 58
- 59 60 61 62 63 64 65 66 67 68 69 70 71 72
- 73 74 75 76 77 78 79 80 81 82 83 84 85 86
- 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
- default-brightness-level = <51>;
enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
power-supply = <&pp3300_disp>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwm-delay-us = <10000>;
};
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>;
+
+ wake_on_bt: wake-on-bt {
+ label = "Wake-on-Bluetooth";
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
};
&ppvar_bigcpu {
@@ -232,7 +237,6 @@
&edp {
status = "okay";
- rockchip,panel = <&edp_panel>;
ports {
edp_out: port@1 {
reg = <1>;
@@ -287,11 +291,9 @@ ap_i2c_tp: &i2c5 {
#pwm-cells = <1>;
};
- usbc_extcon1: extcon@1 {
+ usbc_extcon1: extcon1 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <1>;
-
- #extcon-cells = <0>;
};
};
@@ -361,27 +363,27 @@ ap_i2c_tp: &i2c5 {
&pinctrl {
discrete-regulators {
pp1500_en: pp1500-en {
- rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp1800_audio_en: pp1800-audio-en {
- rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_down>;
};
pp3000_en: pp3000-en {
- rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp3300_disp_en: pp3300-disp-en {
- rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
+ rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
&pcfg_pull_none>;
};
wlan_module_pd_l: wlan-module-pd-l {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
&pcfg_pull_down>;
};
};
@@ -389,10 +391,10 @@ ap_i2c_tp: &i2c5 {
&wifi {
wifi_perst_l: wifi-perst-l {
- rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_host_wake_l: wlan-host-wake-l {
- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts
index 2cc7c47d6a..2bbef9fcbe 100644
--- a/arch/arm/dts/rk3399-gru-kevin.dts
+++ b/arch/arm/dts/rk3399-gru-kevin.dts
@@ -39,11 +39,25 @@
};
edp_panel: edp-panel {
- compatible = "sharp,lq123p1jx31", "simple-panel";
+ compatible = "sharp,lq123p1jx31";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
- ports {
+ panel-timing {
+ clock-frequency = <266666667>;
+ hactive = <2400>;
+ hfront-porch = <48>;
+ hback-porch = <84>;
+ hsync-len = <32>;
+ hsync-active = <0>;
+ vactive = <1600>;
+ vfront-porch = <3>;
+ vback-porch = <120>;
+ vsync-len = <10>;
+ vsync-active = <0>;
+ };
+
+ port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@@ -118,13 +132,17 @@
map0 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
@@ -286,24 +304,24 @@ ap_i2c_dig: &i2c2 {
digitizer {
/* Has external pullup */
cpu1_dig_irq_l: cpu1-dig-irq-l {
- rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* Has external pullup */
cpu1_dig_pdct_l: cpu1-dig-pdct-l {
- rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
discrete-regulators {
cpu3_pen_pwr_en: cpu3-pen-pwr-en {
- rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pen {
cpu1_pen_eject: cpu1-pen-eject {
- rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi
index 0e2e047180..7ac88392f2 100644
--- a/arch/arm/dts/rk3399-gru.dtsi
+++ b/arch/arm/dts/rk3399-gru.dtsi
@@ -11,13 +11,7 @@
/ {
chosen {
- u-boot,dm-pre-reloc;
stdout-path = "serial2:115200n8";
- u-boot,spl-boot-order = &spi_flash;
- };
-
- config {
- u-boot,spl-payload-offset = <0x40000>;
};
/*
@@ -268,17 +262,11 @@
pp5000_usb_a_vbus: pp5000 {
};
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l>;
-
- wake_on_bt: wake-on-bt {
- label = "Wake-on-Bluetooth";
- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- wakeup-source;
- };
+ ap_rtc_clk: ap-rtc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
};
max98357a: max98357a {
@@ -549,8 +537,7 @@ ap_i2c_audio: &i2c8 {
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
- spi_flash: spiflash@0 {
- u-boot,dm-pre-reloc;
+ spiflash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
@@ -565,16 +552,12 @@ ap_i2c_audio: &i2c8 {
&spi5 {
status = "okay";
- spi-activate-delay = <100>;
- spi-max-frequency = <3000000>;
- spi-deactivate-delay = <200>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
@@ -586,11 +569,9 @@ ap_i2c_audio: &i2c8 {
#size-cells = <0>;
};
- usbc_extcon0: extcon@0 {
+ usbc_extcon0: extcon0 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
-
- #extcon-cells = <0>;
};
};
};
@@ -692,29 +673,29 @@ ap_i2c_audio: &i2c8 {
backlight-enable {
bl_en: bl-en {
- rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cros-ec {
ec_ap_int_l: ec-ap-int-l {
- rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
discrete-regulators {
sd_io_pwr_en: sd-io-pwr-en {
- rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_pwr_1800_sel: sd-pwr-1800-sel {
- rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_slot_pwr_en: sd-slot-pwr-en {
- rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
+ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
&pcfg_pull_none>;
};
};
@@ -722,17 +703,17 @@ ap_i2c_audio: &i2c8 {
codec {
/* Has external pullup */
headset_int_l: headset-int-l {
- rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
mic_int: mic-int {
- rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
max98357a {
sdmode_en: sdmode-en {
- rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
@@ -743,7 +724,7 @@ ap_i2c_audio: &i2c8 {
* to hack this as gpio, so the EP could be able to
* de-assert it along and make ClockPM(CPM) work.
*/
- rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -754,20 +735,20 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
- <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
- <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
- <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
- <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
+ <4 RK_PB0 1 &pcfg_pull_none_8ma>,
+ <4 RK_PB1 1 &pcfg_pull_none_8ma>,
+ <4 RK_PB2 1 &pcfg_pull_none_8ma>,
+ <4 RK_PB3 1 &pcfg_pull_none_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
- <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
+ <4 RK_PB4 1 &pcfg_pull_none_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
- <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
+ <4 RK_PB5 1 &pcfg_pull_none_8ma>;
};
/*
@@ -781,12 +762,12 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_cd: sdmmc-cd {
rockchip,pins =
- <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ <0 RK_PA7 1 &pcfg_pull_none>;
};
/* This is where we actually hook up CD; has external pull */
sdmmc_cd_gpio: sdmmc-cd-gpio {
- rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -796,47 +777,47 @@ ap_i2c_audio: &i2c8 {
* Pull down SPI1 CLK/CS/RX/TX during suspend, to
* prevent leakage.
*/
- rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 10 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 7 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 8 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
+ <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
+ <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
touchscreen {
touch_int_l: touch-int-l {
- rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
touch_reset_l: touch-reset-l {
- rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
trackpad {
ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
- rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
};
trackpad_int_l: trackpad-int-l {
- rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi: wifi {
wlan_module_reset_l: wlan-module-reset-l {
- rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
/* Kevin has an external pull up, but Gru does not */
- rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
write-protect {
ap_fw_wp: ap-fw-wp {
- rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi
index 4944d78a0a..e87a044774 100644
--- a/arch/arm/dts/rk3399-khadas-edge.dtsi
+++ b/arch/arm/dts/rk3399-khadas-edge.dtsi
@@ -654,9 +654,12 @@
sd-uhs-sdr104;
vqmmc-supply = <&vcc1v8_s3>;
vmmc-supply = <&vccio_sd>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
+ reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts
index 32baa57b94..73be38a537 100644
--- a/arch/arm/dts/rk3399-leez-p710.dts
+++ b/arch/arm/dts/rk3399-leez-p710.dts
@@ -42,14 +42,14 @@
regulator-max-microvolt = <5000000>;
};
- vcc5v0_sys: vcc5v0-sys {
+ vcc3v3_lan: vcc3v3-lan {
compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
+ regulator-name = "vcc3v3_lan";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc5v_adp>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vim-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@@ -83,14 +83,14 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc3v3_lan: vcc3v3-lan {
+ vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lan";
+ regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vim-supply = <&vcc3v3_sys>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc5v_adp>;
};
vdd_log: vdd-log {
@@ -510,6 +510,14 @@
};
};
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -522,14 +530,6 @@
status = "okay";
};
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
&tcphy0 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts
index 84433cf02b..e0d75617bb 100644
--- a/arch/arm/dts/rk3399-nanopc-t4.dts
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -52,13 +52,58 @@
pinctrl-names = "default";
pinctrl-0 = <&ir_rx>;
};
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /*
+ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
+ * work out to 0, ~1200, ~3000, and 5000RPM respectively.
+ */
+ cooling-levels = <0 12 18 255>;
+ #cooling-cells = <2>;
+ fan-supply = <&vcc12v0_sys>;
+ pwms = <&pwm1 0 50000 0>;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&pcie0 {
+ num-lanes = <4>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
};
&pinctrl {
ir {
ir_rx: ir-rx {
/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
- rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
new file mode 100644
index 0000000000..a2f9786473
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ * Copyright (C) 2020 Deepak Das <deepakdas.linux@gmail.com>
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
new file mode 100644
index 0000000000..60358ab8c7
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi M4";
+ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb2: vcc5v0-usb2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb2";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_usb1>;
+};
+
+&u2phy1_host {
+ phy-supply = <&vcc5v0_usb2>;
+};
+
+&vbus_typec {
+ regulator-always-on;
+ vin-supply = <&vdd_5v>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
index d325e11728..c88018a0ef 100644
--- a/arch/arm/dts/rk3399-nanopi4.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -48,7 +48,7 @@
};
/* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ vcc1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
@@ -71,6 +71,27 @@
vin-supply = <&vcc3v3_sys>;
};
+ /*
+ * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
+ * drives the enable pin, but we can't quite model that.
+ */
+ vcca0v9_s3: vcca0v9-s3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vcca0v9_s3";
+ vin-supply = <&vcc1v8_s3>;
+ };
+
+ /* As above, actually supplied by vcc3v3_sys */
+ vcca1v8_s3: vcca1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_s3";
+ vin-supply = <&vcc1v8_s3>;
+ };
+
vbus_typec: vbus-typec {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
@@ -148,15 +169,28 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+ phy-handle = <&rtl8211e>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_s3>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@1 {
+ reg = <1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&gpu {
@@ -171,6 +205,10 @@
status = "okay";
};
+&hdmi_sound {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
@@ -446,6 +484,10 @@
status = "okay";
};
+&i2s2 {
+ status = "okay";
+};
+
&io_domains {
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcca1v8_codec>;
@@ -464,7 +506,9 @@
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
- num-lanes = <4>;
+ num-lanes = <2>;
+ vpcie0v9-supply = <&vcca0v9_s3>;
+ vpcie1v8-supply = <&vcca1v8_s3>;
status = "okay";
};
@@ -481,6 +525,16 @@
};
};
+ phy {
+ phy_intb: phy-intb {
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rstb: phy-rstb {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts
index cf37b96a6b..f9f7246d4d 100644
--- a/arch/arm/dts/rk3399-orangepi.dts
+++ b/arch/arm/dts/rk3399-orangepi.dts
@@ -136,13 +136,13 @@
vin-supply = <&vcc_sys>;
};
- vcc5v0_typec0: vcc5v0-typec0-regulator {
+ vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec0_en>;
- regulator-name = "vcc5v0_typec0";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vbus_typec";
vin-supply = <&vcc_sys>;
};
@@ -202,14 +202,27 @@
clock_in_out = "input";
phy-supply = <&vcc3v3_s3>;
phy-mode = "rgmii";
+ phy-handle = <&rtl8211e>;
pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@1 {
+ reg = <1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&gpu {
@@ -419,6 +432,8 @@
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -436,6 +451,8 @@
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -472,6 +489,7 @@
compatible = "asahi-kasei,ak09911";
reg = <0x0c>;
vdd-supply = <&vcc3v3_s3>;
+ vid-supply = <&vcc3v3_s3>;
};
mpu6500@68 {
@@ -504,6 +522,16 @@
pinctrl-0 = <&light_int_l>;
vdd-supply = <&vcc3v3_s3>;
};
+
+ fusb302@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&chg_cc_int_l>;
+ vbus-supply = <&vbus_typec>;
+ };
};
&io_domains {
@@ -526,7 +554,25 @@
};
};
+ phy {
+ phy_intb: phy-intb {
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rstb: phy-rstb {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -536,7 +582,7 @@
sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins =
- <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -546,7 +592,7 @@
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
- vcc5v0_typec0_en: vcc5v0-typec0-en {
+ vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins =
<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -595,6 +641,12 @@
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ fusb302 {
+ chg_cc_int_l: chg-cc-int-l {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
};
&pwm0 {
@@ -631,9 +683,12 @@
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
+ reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
@@ -676,7 +731,7 @@
status = "okay";
u2phy0_otg: otg-port {
- phy-supply = <&vcc5v0_typec0>;
+ phy-supply = <&vbus_typec>;
status = "okay";
};
@@ -707,12 +762,14 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
- clock-names = "ext_clock";
+ clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
};
};
diff --git a/arch/arm/dts/rk3399-puma-u-boot.dtsi b/arch/arm/dts/rk3399-puma-u-boot.dtsi
index 52f62b5d39..3ad1139833 100644
--- a/arch/arm/dts/rk3399-puma-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-u-boot.dtsi
@@ -13,7 +13,7 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = \
- "same-as-spl", &spiflash, &sdhci, &sdmmc;
+ "same-as-spl", &norflash, &sdhci, &sdmmc;
};
aliases {
@@ -21,4 +21,33 @@
spi1 = &spi5;
};
+ /*
+ * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
+ * eMMC and SPI flash powered-down initially (in fact it keeps the
+ * reset signal asserted). Even though it is an enable signal, we
+ * model this as a regulator.
+ */
+ bios_enable: bios_enable {
+ compatible = "regulator-fixed";
+ u-boot,dm-pre-reloc;
+ regulator-name = "bios_enable";
+ enable-active-high;
+ gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&norflash {
+ u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index 558b6337df..07694b196f 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -1,30 +1,74 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
/ {
- model = "Theobroma Systems RK3399-Q7 SoM";
- compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_puma>;
+ pinctrl-0 = <&led_pin_module>;
- module_led {
+ module-led {
label = "module_led";
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
+ panic-indicator;
};
+ };
- sd_card_led {
- label = "sd_card_led";
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
+ /*
+ * Overwrite the opp-table for CPUB as this board uses a different
+ * regulator (FAN53555) that only allows 10mV steps and therefore
+ * can't reach the operation point target voltages from rk3399-opp.dtsi
+ */
+ /delete-node/ opp-table1;
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <830000>;
+ opp-suspend;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <880000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1030000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1230000>;
+ turbo-mode;
};
};
@@ -35,79 +79,14 @@
#clock-cells = <0>;
};
- dw_hdmi_audio: dw-hdmi-audio {
- status = "enabled";
- compatible = "rockchip,dw-hdmi-audio";
- #sound-dai-cells = <0>;
- };
-
- hdmi_codec: hdmi-codec {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "HDMI-CODEC";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s2>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
- };
- };
-
- hdmi_sound: hdmi-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "rockchip,hdmi";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s2>;
- };
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
- };
- };
-
- usbhub_enable: usbhub_enable {
- compatible = "regulator-fixed";
- regulator-name = "usbhub_enable";
- enable-active-low;
- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /*
- * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
- * eMMC and SPI flash powered-down initially (in fact it keeps the
- * reset signal asserted). Even though it is an enable signal, we
- * model this as a regulator.
- */
- bios_enable: bios_enable {
- compatible = "regulator-fixed";
- u-boot,dm-pre-reloc;
- regulator-name = "bios_enable";
- enable-active-high;
- gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vccadc_ref: vccadc-ref {
+ vcc1v2_phy: vcc1v2-phy {
compatible = "regulator-fixed";
- regulator-name = "vcc1v8_sys";
+ regulator-name = "vcc1v2_phy";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@@ -117,16 +96,18 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
};
- vcc5v0_otg: vcc5v0-otg-regulator {
+ vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ enable-active-low;
pinctrl-names = "default";
- pinctrl-0 = <&otg_vbus_drv>;
- regulator-name = "vcc5v0_otg";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys {
@@ -137,48 +118,55 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+};
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-init-microvolt = <950000>;
- };
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
};
&emmc_phy {
status = "okay";
+ drive-impedance-ohm = <33>;
};
&gmac {
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc1v2_phy>;
+ phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};
-&hdmi {
- #sound-dai-cells = <0>;
+&gpu {
+ mali-supply = <&vdd_gpu>;
status = "okay";
};
@@ -188,37 +176,17 @@
i2c-scl-falling-time-ns = <4>;
clock-frequency = <400000>;
- vdd_gpu: vdd_gpu {
- status = "okay";
- compatible = "fcs,fan53555";
- reg = <0x60>;
- vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "fan53555-reg";
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1230000>;
- regulator-ramp-delay = <1000>;
- fcs,suspend-voltage-selector = <1>;
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-state = <3>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
- interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt?
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@@ -235,44 +203,44 @@
regulators {
vdd_center: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_center";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
- regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
- regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -280,32 +248,32 @@
};
vcc_ldo1: LDO_REG1 {
- regulator-boot-on;
+ regulator-name = "vcc_ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_ldo1";
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_hdmi: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@@ -313,11 +281,11 @@
};
vcc_sd: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
- regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
@@ -325,79 +293,105 @@
};
vcc_ldo5: LDO_REG5 {
- regulator-boot-on;
+ regulator-name = "vcc_ldo5";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- regulator-name = "vcc_ldo5";
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo6: LDO_REG6 {
- regulator-boot-on;
+ regulator-name = "vcc_ldo6";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
- regulator-name = "vcc_ldo6";
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc0v9_hdmi: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc0v9_hdmi";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
- regulator-name = "vcc0v9_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_efuse: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_efuse";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_efuse";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s3: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc3v3_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
+
+ vdd_gpu: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1230000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #cooling-cells = <2>;
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
};
&i2c8 {
status = "okay";
clock-frequency = <400000>;
- vdd_cpu_b: vdd_cpu_b {
- status = "okay";
+ vdd_cpu_b: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
- vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
- regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
@@ -405,48 +399,36 @@
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
- regulator-initial-state = <3>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
};
};
&i2s0 {
+ pinctrl-0 = <&i2s0_2ch_bus>;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
status = "okay";
- rockchip,i2s-broken-burst-len;
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- #sound-dai-cells = <0>;
};
-&i2s2 {
- #sound-dai-cells = <0>;
- status = "okay";
+/*
+ * As Q7 does not specify neither a global nor a RX clock for I2S these
+ * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
+ * Therefore we have to redefine the i2s0_2ch_bus definition to prevent
+ * conflicts.
+ */
+&i2s0_2ch_bus {
+ rockchip,pins =
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>;
};
&io_domains {
status = "okay";
-
- bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */
- audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */
- sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
- gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */
-};
-
-&pcie0 {
- assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
- assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
- assigned-clock-rates = <100000000>;
- ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
+ bt656-supply = <&vcc_1v8>;
+ audio-supply = <&vcc_1v8>;
+ sdmmc-supply = <&vcc_sd>;
+ gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
@@ -454,195 +436,99 @@
pmu1830-supply = <&vcc_1v8>;
};
-&pwm0 {
- status = "okay";
-};
-
&pwm2 {
status = "okay";
};
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- supports-emmc;
- non-removable;
- keep-power-in-suspend;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- clock-frequency = <150000000>;
- max-frequency = <40000000>;
- supports-sd;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- num-slots = <1>;
- vqmmc-supply = <&vcc_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "disabled";
-};
-
-&usb_host0_ohci {
- status = "disabled";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "disabled";
-};
-
-&usb_host1_ohci {
- status = "disabled";
-};
-
-&usbdrd3_1 {
- status = "okay";
- tsd,usb-port-power = "usbhub_enable";
-};
-
-&vopb {
- status = "okay";
-};
-
-&gpio1 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
&pinctrl {
- /* Pins that are not explicitely used by any devices */
- pinctrl-names = "default";
- pinctrl-0 = <&puma_pin_hog>;
-
- hog {
- puma_pin_hog: puma_pin_hog {
+ i2c8 {
+ i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
- /* We need pull-ups on Q7 buttons */
- <RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
- <RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
- <RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
- <RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
+ <1 RK_PC4 1 &pcfg_pull_up>,
+ <1 RK_PC5 1 &pcfg_pull_up>;
};
};
- pmic {
- pmic_int_l: pmic-int-l {
+ leds {
+ led_pin_module: led-module-gpio {
rockchip,pins =
- <RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- leds_pins_puma: led_pins@0 {
- rockchip,pins =
- <RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
- <RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- usb2 {
- otg_vbus_drv: otg-vbus-drv {
- rockchip,pins =
- <RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- host_vbus_drv: host-vbus-drv {
+ pmic {
+ pmic_int_l: pmic-int-l {
rockchip,pins =
- <RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
- i2c8 {
- i2c8_xfer_a: i2c8-xfer {
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
- <RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
- <RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
-&i2c1 {
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
status = "okay";
- clock-frequency = <400000>;
};
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
+
+&sdmmc {
+ vqmmc-supply = <&vcc_sd>;
};
-&i2c4 {
+
+&spi1 {
status = "okay";
- clock-frequency = <400000>;
+
+ norflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
};
-&i2c6 {
+
+&tcphy1 {
status = "okay";
- clock-frequency = <400000>;
};
-&i2c6_xfer {
- /* Enable pull-ups, the pins would float otherwise. */
- rockchip,pins =
- <RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
- <RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
};
-&i2c7 {
+&u2phy1 {
status = "okay";
- clock-frequency = <400000>;
- rtc_twi: rtc@6f {
- compatible = "isil,isl1208";
- reg = <0x6f>;
+ u2phy1_otg: otg-port {
+ status = "okay";
};
- fan: fan@18 {
- compatible = "ti,amc6821";
- reg = <0x18>;
- cooling-min-state = <0>;
- cooling-max-state = <9>;
- #cooling-cells = <2>;
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
};
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
+&usbdrd3_1 {
status = "okay";
};
-
-&spi1 {
+&usbdrd_dwc3_1 {
status = "okay";
+ dr_mode = "host";
+};
- #address-cells = <1>;
- #size-cells = <0>;
-
- spiflash: w25q32dw@0 {
- u-boot,dm-pre-reloc;
-
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <49500000>;
- spi-cpol;
- spi-cpha;
- };
+&usb_host1_ehci {
+ status = "okay";
};
-&spi5 {
+&usb_host1_ohci {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi
new file mode 100644
index 0000000000..f50c18dd3d
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "rk3399-roc-pc-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts
new file mode 100644
index 0000000000..2acb3d500f
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
+ */
+
+/dts-v1/;
+#include "rk3399-roc-pc.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Mezzanine Board";
+ compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
+
+ vcc3v3_ngff: vcc3v3-ngff {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_ngff";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_ngff_en>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie_en>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_perst>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ vpcie1v8-supply = <&vcc1v8_pmu>;
+ vpcie0v9-supply = <&vcca_0v9>;
+ status = "okay";
+};
+
+&pinctrl {
+ ngff {
+ vcc3v3_ngff_en: vcc3v3-ngff-en {
+ rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ vcc3v3_pcie_en: vcc3v3-pcie-en {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_perst: pcie-perst {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_ngff>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index 5746442981..141dd0b306 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -14,9 +14,45 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
+
+ vcc_hub_en: vcc_hub_en-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hub_rst>;
+ regulator-name = "vcc_hub_en";
+ regulator-always-on;
+ };
+};
+
+/*
+ * should be placed inside mp8859, but not until mp8859 has
+ * its own dt-binding.
+ */
+&dc_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&vcc_vbus_typec0>;
};
&vdd_log {
regulator-min-microvolt = <430000>;
regulator-init-microvolt = <950000>;
};
+
+&vcc5v0_host {
+ regulator-always-on;
+};
+
+&vcc_sys {
+ regulator-always-on;
+};
+
+&vcc_sdio {
+ regulator-always-on;
+};
diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts
index 6a909e4eef..cd41954253 100644
--- a/arch/arm/dts/rk3399-roc-pc.dts
+++ b/arch/arm/dts/rk3399-roc-pc.dts
@@ -8,6 +8,5 @@
/ {
model = "Firefly ROC-RK3399-PC Board";
- compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc",
- "rockchip,rk3399";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
};
diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi
index 9a1ce3a4ae..9f225e9c3d 100644
--- a/arch/arm/dts/rk3399-roc-pc.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc.dtsi
@@ -110,20 +110,6 @@
regulator-max-microvolt = <5000000>;
};
- /*
- * should be placed inside mp8859, but not until mp8859 has
- * its own dt-binding.
- */
- dc_12v: mp8859-dcdc1 {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- vin-supply = <&vcc_vbus_typec0>;
- };
-
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@@ -176,7 +162,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
regulator-name = "vcc5v0_host";
- regulator-always-on;
vin-supply = <&vcc_sys>;
};
@@ -198,7 +183,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc_sys_en>;
regulator-name = "vcc_sys";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -392,7 +376,6 @@
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
@@ -549,6 +532,24 @@
vbus-supply = <&vcc_vbus_typec0>;
status = "okay";
};
+
+ mp8859: regulator@66 {
+ compatible = "mps,mp8859";
+ reg = <0x66>;
+ dc_12v: mp8859_dcdc {
+ regulator-name = "dc_12v";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_vbus_typec0>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <12000000>;
+ };
+ };
+ };
};
&i2s0 {
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts b/arch/arm/dts/rk3399-rock-pi-4.dts
index 4a543f2117..3923ec01ef 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4.dts
@@ -25,6 +25,15 @@
#clock-cells = <0>;
};
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -44,6 +53,16 @@
vin-supply = <&vcc12v_dcin>;
};
+ vcc_0v9: vcc-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -157,12 +176,22 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
+ ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
+&hdmi_sound {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
@@ -444,13 +473,60 @@
pmu1830-supply = <&vcc_3v0>;
};
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+ max-link-speed = <2>;
+ num-lanes = <4>;
+ pinctrl-0 = <&pcie_clkreqnb_cpm>;
+ pinctrl-names = "default";
+ vpcie0v9-supply = <&vcc_0v9>;
+ vpcie1v8-supply = <&vcc_1v8>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+ sdio0 {
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC5 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC6 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC7 1 &pcfg_pull_up_20ma>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -476,6 +552,16 @@
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pwm2 {
@@ -488,6 +574,32 @@
vref-supply = <&vcc_1v8>;
};
+&sdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@@ -551,6 +663,23 @@
};
};
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ };
+};
+
&uart2 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts
index 12285c51cc..437a75f31a 100644
--- a/arch/arm/dts/rk3399-rock960.dts
+++ b/arch/arm/dts/rk3399-rock960.dts
@@ -114,6 +114,55 @@
};
};
+&spi0 {
+ /* On Low speed expansion (LS-SPI0) */
+ status = "okay";
+};
+
+&spi4 {
+ /* On High speed expansion (HS-SPI1) */
+ status = "okay";
+};
+
+&thermal_zones {
+ cpu_thermal: cpu {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsadc 0>;
+ sustainable-power = <1550>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi
index c7d48d41e1..ba7c75c9f2 100644
--- a/arch/arm/dts/rk3399-rock960.dtsi
+++ b/arch/arm/dts/rk3399-rock960.dtsi
@@ -76,6 +76,15 @@
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc_0v9: vcc-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_0v9";
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
};
&cpu_l0 {
@@ -384,6 +393,8 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
+ vpcie0v9-supply = <&vcc_0v9>;
+ vpcie1v8-supply = <&vcca_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
@@ -531,7 +542,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
clock-frequency = <100000000>;
- clock-freq-min-max = <100000 100000000>;
+ max-frequency = <100000000>;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;
diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts
index e544deb61d..4b42717800 100644
--- a/arch/arm/dts/rk3399-rockpro64.dts
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -2,752 +2,29 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Katsuhiro Suzuki <katsuhiro@katsuster.net>
*/
/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
+#include "rk3399-rockpro64.dtsi"
/ {
- model = "Pine64 RockPro64";
- compatible = "pine64,rockpro64", "rockchip,rk3399";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
-
- work-led {
- label = "work";
- default-state = "on";
- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- diy-led {
- label = "diy";
- default-state = "off";
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- fan-supply = <&vcc12v_dcin>;
- pwms = <&pwm1 0 50000 0>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pwr_en>;
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_typec: vcc5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vcc5v0_typec";
- regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1700000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio3>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcca_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v0_touch: LDO_REG2 {
- regulator-name = "vcc3v0_touch";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
+ model = "Pine64 RockPro64 v2.1";
+ compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399";
};
&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vcc5v0_typec>;
- status = "okay";
- };
-};
+ es8316: codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pcie0 {
- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_perst>;
- vpcie12v-supply = <&vcc12v_dcin>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pinctrl {
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- fusb302x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- work_led_gpio: work_led-gpio {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_gpio: diy_led-gpio {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_perst: pcie-perst {
- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_pwr_en: pcie-pwr-en {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_gpio: vsel1-gpio {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_gpio: vsel2-gpio {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- vcc5v0_typec_en: vcc5v0_typec_en {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s1_p0_0>;
+ };
};
};
};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi
new file mode 100644
index 0000000000..9bca258012
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64.dtsi
@@ -0,0 +1,797 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ */
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ fan-supply = <&vcc12v_dcin>;
+ pwms = <&pwm1 0 50000 0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "rockchip,rk3399";
+ dais = <&i2s1_p0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1700000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca_1v8>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-name = "vcc3v0_touch";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8: LDO_REG3 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_gpio>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_gpio>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vcc5v0_typec>;
+ status = "okay";
+ };
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+
+ i2s1_p0: port {
+ i2s1_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc1v8_dvp>;
+ audio-supply = <&vcc_3v0>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie0 {
+ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_perst>;
+ vpcie12v-supply = <&vcc12v_dcin>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ fusb302x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ work_led_gpio: work_led-gpio {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_gpio: diy_led-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_perst: pcie-perst {
+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0_typec_en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 8b857ccfc7..9bb130a92a 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -25,6 +25,12 @@
clock-names = "pclk_ddr_mon";
};
+ rng: rng@ff8b8000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
+ status = "disabled";
+ };
+
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
@@ -79,6 +85,7 @@
};
&sdhci {
+ max-frequency = <200000000>;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6b7c136ab8..74f2c3d490 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rk3399-cru.h>
@@ -19,6 +19,7 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -67,53 +68,102 @@
cpu_l0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
- #cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <485>;
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <100>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu_l1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ capacity-dmips-mhz = <485>;
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <100>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu_l2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ capacity-dmips-mhz = <485>;
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <100>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu_l3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ capacity-dmips-mhz = <485>;
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <100>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu_b0: cpu@100 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
- #cooling-cells = <2>; /* min followed by max */
+ capacity-dmips-mhz = <1024>;
clocks = <&cru ARMCLKB>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <436>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu_b1: cpu@101 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
clocks = <&cru ARMCLKB>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <436>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+
+ CLUSTER_SLEEP: cluster-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <2000>;
+ };
+ };
+ };
+
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vopl_out>, <&vopb_out>;
};
pmu_a53 {
@@ -147,7 +197,7 @@
#clock-cells = <0>;
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -183,7 +233,7 @@
#size-cells = <2>;
#interrupt-cells = <1>;
aspm-no-l0s;
- bus-range = <0x0 0x1>;
+ bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
@@ -200,10 +250,12 @@
linux,pci-domain = <0>;
max-link-speed = <1>;
msi-map = <0x0 &its 0x0 0x1000>;
- phys = <&pcie_phy>;
- phy-names = "pcie-phy";
- ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
- 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+ phys = <&pcie_phy 0>, <&pcie_phy 1>,
+ <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1",
+ "pcie-phy-2", "pcie-phy-3";
+ ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
+ 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
@@ -236,10 +288,11 @@
resets = <&cru SRST_A_GMAC>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
+ snps,txpbl = <0x4>;
status = "disabled";
};
- sdio0: dwmmc@fe310000 {
+ sdio0: mmc@fe310000 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>;
@@ -255,12 +308,14 @@
status = "disabled";
};
- sdmmc: dwmmc@fe320000 {
+ sdmmc: mmc@fe320000 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
max-frequency = <150000000>;
+ assigned-clocks = <&cru HCLK_SD>;
+ assigned-clock-rates = <200000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -278,7 +333,6 @@
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
- max-frequency = <200000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "emmc_cardclock";
@@ -286,6 +340,7 @@
phys = <&emmc_phy>;
phy-names = "phy_arasan";
power-domains = <&power RK3399_PD_EMMC>;
+ disable-cqe-dcmd;
status = "disabled";
};
@@ -295,11 +350,8 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&u2phy0>;
- clock-names = "usbhost", "arbiter",
- "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
- power-domains = <&power RK3399_PD_PERIHP>;
status = "disabled";
};
@@ -309,11 +361,8 @@
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&u2phy0>;
- clock-names = "usbhost", "arbiter",
- "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
- power-domains = <&power RK3399_PD_PERIHP>;
status = "disabled";
};
@@ -323,11 +372,8 @@
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
<&u2phy1>;
- clock-names = "usbhost", "arbiter",
- "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
- power-domains = <&power RK3399_PD_PERIHP>;
status = "disabled";
};
@@ -337,15 +383,12 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
<&u2phy1>;
- clock-names = "usbhost", "arbiter",
- "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
- power-domains = <&power RK3399_PD_PERIHP>;
status = "disabled";
};
- usbdrd3_0: dwc3_typec0: usb@fe800000 {
+ usbdrd3_0: usb@fe800000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
#size-cells = <2>;
@@ -364,6 +407,9 @@
compatible = "snps,dwc3";
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
+ <&cru SCLK_USB3OTG0_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
phys = <&u2phy0_otg>, <&tcphy0_usb3>;
phy-names = "usb2-phy", "usb3-phy";
@@ -378,7 +424,7 @@
};
};
- dwc3_typec1: usbdrd3_1: usb@fe900000 {
+ usbdrd3_1: usb@fe900000 {
compatible = "rockchip,rk3399-dwc3";
#address-cells = <2>;
#size-cells = <2>;
@@ -397,6 +443,9 @@
compatible = "snps,dwc3";
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
+ <&cru SCLK_USB3OTG1_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
phys = <&u2phy1_otg>, <&tcphy1_usb3>;
phy-names = "usb2-phy", "usb3-phy";
@@ -464,6 +513,7 @@
its: interrupt-controller@fee20000 {
compatible = "arm,gic-v3-its";
msi-controller;
+ #msi-cells = <1>;
reg = <0x0 0xfee20000 0x0 0x20000>;
};
@@ -612,7 +662,6 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
- clock-frequency = <24000000>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -639,6 +688,8 @@
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dmac_peri 10>, <&dmac_peri 11>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
#address-cells = <1>;
@@ -652,6 +703,8 @@
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dmac_peri 12>, <&dmac_peri 13>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
#address-cells = <1>;
@@ -665,6 +718,8 @@
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dmac_peri 14>, <&dmac_peri 15>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
#address-cells = <1>;
@@ -678,6 +733,8 @@
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dmac_peri 18>, <&dmac_peri 19>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
#address-cells = <1>;
@@ -691,8 +748,11 @@
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dmac_bus 8>, <&dmac_bus 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
+ power-domains = <&power RK3399_PD_SDIOAUDIO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -727,13 +787,18 @@
map0 {
trip = <&cpu_alert0>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -761,7 +826,7 @@
map0 {
trip = <&gpu_alert0>;
cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -980,22 +1045,11 @@
<&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
};
- pd_perihp@RK3399_PD_PERIHP {
- reg = <RK3399_PD_PERIHP>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru ACLK_PERIHP>;
- pm_qos = <&qos_perihp>,
- <&qos_pcie>,
- <&qos_usb_host0>,
- <&qos_usb_host1>;
-
- pd_sd@RK3399_PD_SD {
- reg = <RK3399_PD_SD>;
- clocks = <&cru HCLK_SDMMC>,
- <&cru SCLK_SDMMC>;
- pm_qos = <&qos_sd>;
- };
+ pd_sd@RK3399_PD_SD {
+ reg = <RK3399_PD_SD>;
+ clocks = <&cru HCLK_SDMMC>,
+ <&cru SCLK_SDMMC>;
+ pm_qos = <&qos_sd>;
};
pd_sdioaudio@RK3399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
@@ -1070,6 +1124,8 @@
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
pmu_io_domains: io-domains {
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
@@ -1192,6 +1248,62 @@
status = "disabled";
};
+ vpu: video-codec@ff650000 {
+ compatible = "rockchip,rk3399-vpu";
+ reg = <0x0 0xff650000 0x0 0x800>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3399_PD_VCODEC>;
+ };
+
+ vpu_mmu: iommu@ff650800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3399_PD_VCODEC>;
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff670800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff670800 0x0 0x40>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rga: rga@ff680000 {
+ compatible = "rockchip,rk3399-rga";
+ reg = <0x0 0xff680000 0x0 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
+ reset-names = "core", "axi", "ahb";
+ power-domains = <&power RK3399_PD_RGA>;
+ };
+
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;
@@ -1342,8 +1454,9 @@
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
- #phy-cells = <0>;
+ #phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
+ drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
@@ -1592,11 +1705,11 @@
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
- clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+ clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3399_PD_ISP0>;
rockchip,disable-mmu-reset;
- status = "disabled";
};
isp1_mmu: iommu@ff924000 {
@@ -1604,11 +1717,11 @@
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
- clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+ clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3399_PD_ISP1>;
rockchip,disable-mmu-reset;
- status = "disabled";
};
hdmi_sound: hdmi-sound {
@@ -1660,21 +1773,29 @@
};
mipi_dsi: mipi@ff960000 {
- compatible = "rockchip,rk3399_mipi_dsi";
+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
- <&cru SCLK_DPHY_TX0_CFG>;
- clock-names = "ref", "pclk", "phy_cfg";
+ clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
+ clock-names = "ref", "pclk", "phy_cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ resets = <&cru SRST_P_MIPI_DSI0>;
+ reset-names = "apb";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+
ports {
- reg = <1>;
- mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -1698,6 +1819,8 @@
resets = <&cru SRST_P_MIPI_DSI1>;
reset-names = "apb";
rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
ports {
@@ -1765,6 +1888,7 @@
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "gpu", "job", "mmu";
clocks = <&cru ACLK_GPU>;
+ #cooling-cells = <2>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
@@ -1929,14 +2053,14 @@
clock {
clk_32k: clk-32k {
- rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
edp {
edp_hpd: edp-hpd {
rockchip,pins =
- <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
+ <4 RK_PC7 2 &pcfg_pull_none>;
};
};
@@ -1944,382 +2068,409 @@
rgmii_pins: rgmii-pins {
rockchip,pins =
/* mac_txclk */
- <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PC1 1 &pcfg_pull_none_13ma>,
/* mac_rxclk */
- <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB6 1 &pcfg_pull_none>,
/* mac_mdio */
- <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB5 1 &pcfg_pull_none>,
/* mac_txen */
- <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PB4 1 &pcfg_pull_none_13ma>,
/* mac_clk */
- <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB3 1 &pcfg_pull_none>,
/* mac_rxdv */
- <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB1 1 &pcfg_pull_none>,
/* mac_mdc */
- <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none>,
/* mac_rxd1 */
- <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA7 1 &pcfg_pull_none>,
/* mac_rxd0 */
- <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA6 1 &pcfg_pull_none>,
/* mac_txd1 */
- <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PA5 1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
- <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PA4 1 &pcfg_pull_none_13ma>,
/* mac_rxd3 */
- <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA3 1 &pcfg_pull_none>,
/* mac_rxd2 */
- <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA2 1 &pcfg_pull_none>,
/* mac_txd3 */
- <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PA1 1 &pcfg_pull_none_13ma>,
/* mac_txd2 */
- <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
+ <3 RK_PA0 1 &pcfg_pull_none_13ma>;
};
rmii_pins: rmii-pins {
rockchip,pins =
/* mac_mdio */
- <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB5 1 &pcfg_pull_none>,
/* mac_txen */
- <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PB4 1 &pcfg_pull_none_13ma>,
/* mac_clk */
- <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB3 1 &pcfg_pull_none>,
/* mac_rxer */
- <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB2 1 &pcfg_pull_none>,
/* mac_rxdv */
- <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB1 1 &pcfg_pull_none>,
/* mac_mdc */
- <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none>,
/* mac_rxd1 */
- <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA7 1 &pcfg_pull_none>,
/* mac_rxd0 */
- <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
+ <3 RK_PA6 1 &pcfg_pull_none>,
/* mac_txd1 */
- <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ <3 RK_PA5 1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
- <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
+ <3 RK_PA4 1 &pcfg_pull_none_13ma>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
- <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ <1 RK_PC0 2 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins =
- <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ <4 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins =
- <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
- <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ <2 RK_PA1 2 &pcfg_pull_none_12ma>,
+ <2 RK_PA0 2 &pcfg_pull_none_12ma>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins =
- <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC1 1 &pcfg_pull_none>,
+ <4 RK_PC0 1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins =
- <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
+ <1 RK_PB4 1 &pcfg_pull_none>,
+ <1 RK_PB3 1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins =
- <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
- <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ <3 RK_PB2 2 &pcfg_pull_none>;
};
};
i2c6 {
i2c6_xfer: i2c6-xfer {
rockchip,pins =
- <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
+ <2 RK_PB2 2 &pcfg_pull_none>,
+ <2 RK_PB1 2 &pcfg_pull_none>;
};
};
i2c7 {
i2c7_xfer: i2c7-xfer {
rockchip,pins =
- <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
+ <2 RK_PB0 2 &pcfg_pull_none>,
+ <2 RK_PA7 2 &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer: i2c8-xfer {
rockchip,pins =
- <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
- <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
+ <1 RK_PC5 1 &pcfg_pull_none>,
+ <1 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s0 {
+ i2s0_2ch_bus: i2s0-2ch-bus {
+ rockchip,pins =
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
- <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
- <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ <4 RK_PA0 1 &pcfg_pull_none>;
};
};
i2s1 {
i2s1_2ch_bus: i2s1-2ch-bus {
rockchip,pins =
- <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
- <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ <4 RK_PA7 1 &pcfg_pull_none>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins =
- <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PC4 1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
rockchip,pins =
- <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PC4 1 &pcfg_pull_up>,
+ <2 RK_PC5 1 &pcfg_pull_up>,
+ <2 RK_PC6 1 &pcfg_pull_up>,
+ <2 RK_PC7 1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins =
- <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PD0 1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
rockchip,pins =
- <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ <2 RK_PD1 1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
rockchip,pins =
- <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PD2 1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
rockchip,pins =
- <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PD3 1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
rockchip,pins =
- <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PD4 1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
rockchip,pins =
- <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+ <0 RK_PA3 1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
rockchip,pins =
- <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+ <0 RK_PA4 1 &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
- <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+ <4 RK_PB0 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
- <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
- <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
- <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
- <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
+ <4 RK_PB0 1 &pcfg_pull_up>,
+ <4 RK_PB1 1 &pcfg_pull_up>,
+ <4 RK_PB2 1 &pcfg_pull_up>,
+ <4 RK_PB3 1 &pcfg_pull_up>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
- <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PB4 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
- <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
+ <4 RK_PB5 1 &pcfg_pull_up>;
};
sdmmc_cd: sdmmc-cd {
rockchip,pins =
- <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+ <0 RK_PA7 1 &pcfg_pull_up>;
};
sdmmc_wp: sdmmc-wp {
rockchip,pins =
- <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+ <0 RK_PB0 1 &pcfg_pull_up>;
};
};
sleep {
ap_pwroff: ap-pwroff {
- rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
- rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
};
};
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
- <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC5 1 &pcfg_pull_none>;
};
spdif_bus_1: spdif-bus-1 {
rockchip,pins =
- <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+ <3 RK_PC0 3 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
- <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA6 2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins =
- <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA7 2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins =
- <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PB0 2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins =
- <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA5 2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins =
- <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA4 2 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins =
- <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
+ <1 RK_PB1 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins =
- <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
+ <1 RK_PB2 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins =
- <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
+ <1 RK_PA7 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins =
- <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
+ <1 RK_PB0 2 &pcfg_pull_up>;
};
};
spi2 {
spi2_clk: spi2-clk {
rockchip,pins =
- <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PB3 1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins =
- <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PB4 1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins =
- <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PB1 1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins =
- <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
+ <2 RK_PB2 1 &pcfg_pull_up>;
};
};
spi3 {
spi3_clk: spi3-clk {
rockchip,pins =
- <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
+ <1 RK_PC1 1 &pcfg_pull_up>;
};
spi3_cs0: spi3-cs0 {
rockchip,pins =
- <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
+ <1 RK_PC2 1 &pcfg_pull_up>;
};
spi3_rx: spi3-rx {
rockchip,pins =
- <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
+ <1 RK_PB7 1 &pcfg_pull_up>;
};
spi3_tx: spi3-tx {
rockchip,pins =
- <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
+ <1 RK_PC0 1 &pcfg_pull_up>;
};
};
spi4 {
spi4_clk: spi4-clk {
rockchip,pins =
- <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA2 2 &pcfg_pull_up>;
};
spi4_cs0: spi4-cs0 {
rockchip,pins =
- <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA3 2 &pcfg_pull_up>;
};
spi4_rx: spi4-rx {
rockchip,pins =
- <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA0 2 &pcfg_pull_up>;
};
spi4_tx: spi4-tx {
rockchip,pins =
- <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
+ <3 RK_PA1 2 &pcfg_pull_up>;
};
};
spi5 {
spi5_clk: spi5-clk {
rockchip,pins =
- <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
+ <2 RK_PC6 2 &pcfg_pull_up>;
};
spi5_cs0: spi5-cs0 {
rockchip,pins =
- <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
+ <2 RK_PC7 2 &pcfg_pull_up>;
};
spi5_rx: spi5-rx {
rockchip,pins =
- <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
+ <2 RK_PC4 2 &pcfg_pull_up>;
};
spi5_tx: spi5-tx {
rockchip,pins =
- <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
+ <2 RK_PC5 2 &pcfg_pull_up>;
+ };
+ };
+
+ testclk {
+ test_clkout0: test-clkout0 {
+ rockchip,pins =
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ test_clkout1: test-clkout1 {
+ rockchip,pins =
+ <2 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ test_clkout2: test-clkout2 {
+ rockchip,pins =
+ <0 RK_PB0 3 &pcfg_pull_none>;
};
};
@@ -2329,168 +2480,168 @@
};
otp_out: otp-out {
- rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
- <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
+ <2 RK_PC0 1 &pcfg_pull_up>,
+ <2 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins =
- <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
+ <2 RK_PC2 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins =
- <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
+ <2 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins =
- <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
- <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PB4 2 &pcfg_pull_up>,
+ <3 RK_PB5 2 &pcfg_pull_none>;
};
};
uart2a {
uart2a_xfer: uart2a-xfer {
rockchip,pins =
- <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
- <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
+ <4 RK_PB0 2 &pcfg_pull_up>,
+ <4 RK_PB1 2 &pcfg_pull_none>;
};
};
uart2b {
uart2b_xfer: uart2b-xfer {
rockchip,pins =
- <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
- <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
+ <4 RK_PC0 2 &pcfg_pull_up>,
+ <4 RK_PC1 2 &pcfg_pull_none>;
};
};
uart2c {
uart2c_xfer: uart2c-xfer {
rockchip,pins =
- <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
- <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC3 1 &pcfg_pull_up>,
+ <4 RK_PC4 1 &pcfg_pull_none>;
};
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins =
- <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
- <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PB6 2 &pcfg_pull_up>,
+ <3 RK_PB7 2 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins =
- <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PC0 2 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins =
- <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+ <3 RK_PC1 2 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins =
- <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
- <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
+ <1 RK_PA7 1 &pcfg_pull_up>,
+ <1 RK_PB0 1 &pcfg_pull_none>;
};
};
uarthdcp {
uarthdcp_xfer: uarthdcp-xfer {
rockchip,pins =
- <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
- <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
+ <4 RK_PC5 2 &pcfg_pull_up>,
+ <4 RK_PC6 2 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins =
- <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ pwm0_pin_pull_down: pwm0-pin-pull-down {
+ rockchip,pins =
+ <4 RK_PC2 1 &pcfg_pull_down>;
};
vop0_pwm_pin: vop0-pwm-pin {
rockchip,pins =
- <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ <4 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ vop1_pwm_pin: vop1-pwm-pin {
+ rockchip,pins =
+ <4 RK_PC2 3 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins =
- <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC6 1 &pcfg_pull_none>;
};
- vop1_pwm_pin: vop1-pwm-pin {
+ pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins =
- <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+ <4 RK_PC6 1 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins =
- <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
+ <1 RK_PC3 1 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins =
- <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
+ <1 RK_PC3 1 &pcfg_pull_down>;
};
};
pwm3a {
pwm3a_pin: pwm3a-pin {
rockchip,pins =
- <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ <0 RK_PA6 1 &pcfg_pull_none>;
};
};
pwm3b {
pwm3b_pin: pwm3b-pin {
rockchip,pins =
- <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
+ <1 RK_PB6 1 &pcfg_pull_none>;
};
};
hdmi {
hdmi_i2c_xfer: hdmi-i2c-xfer {
rockchip,pins =
- <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
- <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+ <4 RK_PC1 3 &pcfg_pull_none>,
+ <4 RK_PC0 3 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins =
- <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+ <4 RK_PC7 1 &pcfg_pull_none>;
};
};
pcie {
- pcie_clkreqn: pci-clkreqn {
- rockchip,pins =
- <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- pcie_clkreqnb: pci-clkreqnb {
- rockchip,pins =
- <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
- };
-
pcie_clkreqn_cpm: pci-clkreqn-cpm {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 5ade63665a..b52565473d 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -26,6 +26,8 @@
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
+#define MXC_CPU_IMX8MD 0x83 /* dummy ID */
+#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */
#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
@@ -33,6 +35,11 @@
#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
+#define MXC_CPU_IMX8MND 0x8c /* dummy ID */
+#define MXC_CPU_IMX8MNS 0x8d /* dummy ID */
+#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
+#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
+#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
#define MXC_CPU_IMX8MP 0x182/* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
index 8e1e9bbf43..c1a9c353ba 100644
--- a/arch/arm/include/asm/arch-imx8/sci/rpc.h
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -8,6 +8,11 @@
#define SC_RPC_H
/* Note: Check SCFW API Released DOC before you want to modify something */
+/* Defines */
+
+#define SCFW_API_VERSION_MAJOR 1U
+#define SCFW_API_VERSION_MINOR 15U
+
#define SC_RPC_VERSION 1U
#define SC_RPC_MAX_MSG 8U
@@ -17,9 +22,13 @@
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
+#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
+ (s64)(RPC_U32((MSG), (IDX) + 4U))
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
+#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
+ (u64)(RPC_U32((MSG), (IDX) + 4U))
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
@@ -76,6 +85,8 @@ struct sc_rpc_msg_s {
#define PM_FUNC_REBOOT 9U
#define PM_FUNC_REBOOT_PARTITION 12U
#define PM_FUNC_CPU_START 11U
+#define PM_FUNC_CPU_RESET 23U
+#define PM_FUNC_RESOURCE_RESET 29U
#define PM_FUNC_IS_PARTITION_STARTED 24U
/* MISC RPC */
@@ -160,26 +171,59 @@ struct sc_rpc_msg_s {
#define RM_FUNC_DUMP 27U
/* SECO RPC */
-#define SECO_FUNC_UNKNOWN 0
-#define SECO_FUNC_IMAGE_LOAD 1U
-#define SECO_FUNC_AUTHENTICATE 2U
-#define SECO_FUNC_FORWARD_LIFECYCLE 3U
-#define SECO_FUNC_RETURN_LIFECYCLE 4U
-#define SECO_FUNC_COMMIT 5U
-#define SECO_FUNC_ATTEST_MODE 6U
-#define SECO_FUNC_ATTEST 7U
-#define SECO_FUNC_GET_ATTEST_PKEY 8U
-#define SECO_FUNC_GET_ATTEST_SIGN 9U
-#define SECO_FUNC_ATTEST_VERIFY 10U
-#define SECO_FUNC_GEN_KEY_BLOB 11U
-#define SECO_FUNC_LOAD_KEY 12U
-#define SECO_FUNC_GET_MP_KEY 13U
-#define SECO_FUNC_UPDATE_MPMR 14U
-#define SECO_FUNC_GET_MP_SIGN 15U
-#define SECO_FUNC_BUILD_INFO 16U
-#define SECO_FUNC_CHIP_INFO 17U
-#define SECO_FUNC_ENABLE_DEBUG 18U
-#define SECO_FUNC_GET_EVENT 19U
-#define SECO_FUNC_FUSE_WRITE 20U
+#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
+#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
+#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
+#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
+#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
+#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
+#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
+#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
+#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
+#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
+#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
+#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
+#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
+#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
+#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
+#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
+#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
+#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
+#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
+#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
+#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
+#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
+#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
+#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
+#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
+#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
+#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */
+
+/* IRQ RPC */
+#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
+#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
+#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
+
+/* TIMER RPC */
+#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
#endif /* SC_RPC_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 14ee6f999b..05f736f14f 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -72,6 +72,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address);
sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
+int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
/* MISC API */
int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
@@ -108,6 +109,7 @@ int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
/* PAD API */
int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
+int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
/* SMMU API */
int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
@@ -122,5 +124,13 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
sc_faddr_t export_addr, u16 max_size);
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
+int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+ u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
+int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
+int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
+ u32 *data0, u32 *data1, u32 *data2, u32 *data3,
+ u32 *data4, u8 size);
#endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
index 905c56834e..df368e8c8b 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
@@ -6,6 +6,9 @@
#ifndef SC_PAD_API_H
#define SC_PAD_API_H
+/* Defines for type widths */
+#define SC_PAD_MUX_W 3U /* Width of mux parameter */
+
/* Defines for sc_pad_config_t */
#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
#define SC_PAD_CONFIG_OD 1U /* Open Drain */
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
index 9eadc88592..adfed13e33 100644
--- a/arch/arm/include/asm/arch-imx8/sci/types.h
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -32,6 +32,7 @@ typedef u64 sc_ipc_t;
#define SC_83MHZ 83333333U /* 83MHz */
#define SC_84MHZ 84375000U /* 84.37MHz */
#define SC_100MHZ 100000000U /* 100MHz */
+#define SC_114MHZ 114000000U /* 114MHz */
#define SC_125MHZ 125000000U /* 125MHz */
#define SC_133MHZ 133333333U /* 133MHz */
#define SC_135MHZ 135000000U /* 135MHz */
@@ -52,6 +53,7 @@ typedef u64 sc_ipc_t;
#define SC_372MHZ 372000000U /* 372MHz */
#define SC_375MHZ 375000000U /* 375MHz */
#define SC_400MHZ 400000000U /* 400MHz */
+#define SC_465MHZ 465000000U /* 465MHz */
#define SC_500MHZ 500000000U /* 500MHz */
#define SC_594MHZ 594000000U /* 594MHz */
#define SC_625MHZ 625000000U /* 625MHz */
@@ -75,6 +77,7 @@ typedef u64 sc_ipc_t;
#define SC_1500MHZ 1500000000U /* 1.5GHz */
#define SC_1600MHZ 1600000000U /* 1.6GHz */
#define SC_1800MHZ 1800000000U /* 1.8GHz */
+#define SC_1860MHZ 1860000000U /* 1.86GHz */
#define SC_2000MHZ 2000000000U /* 2.0GHz */
#define SC_2112MHZ 2112000000U /* 2.12GHz */
@@ -89,6 +92,7 @@ typedef u64 sc_ipc_t;
#define SC_144MHZ 144000000U /* 144MHz */
#define SC_192MHZ 192000000U /* 192MHz */
#define SC_211MHZ 211200000U /* 211.2MHz */
+#define SC_228MHZ 228000000U /* 233MHz */
#define SC_240MHZ 240000000U /* 240MHz */
#define SC_264MHZ 264000000U /* 264MHz */
#define SC_352MHZ 352000000U /* 352MHz */
@@ -96,11 +100,13 @@ typedef u64 sc_ipc_t;
#define SC_384MHZ 384000000U /* 384MHz */
#define SC_396MHZ 396000000U /* 396MHz */
#define SC_432MHZ 432000000U /* 432MHz */
+#define SC_456MHZ 456000000U /* 466MHz */
#define SC_480MHZ 480000000U /* 480MHz */
#define SC_600MHZ 600000000U /* 600MHz */
#define SC_744MHZ 744000000U /* 744MHz */
#define SC_792MHZ 792000000U /* 792MHz */
#define SC_864MHZ 864000000U /* 864MHz */
+#define SC_912MHZ 912000000U /* 912MHz */
#define SC_960MHZ 960000000U /* 960MHz */
#define SC_1056MHZ 1056000000U /* 1056MHz */
#define SC_1104MHZ 1104000000U /* 1104MHz */
diff --git a/arch/arm/include/asm/arch-imx8/snvs_security_sc.h b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
new file mode 100644
index 0000000000..0b7ded7ba6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _SNVS_SECURITY_SC_H
+#define _SNVS_SECURITY_SC_H
+
+int snvs_security_sc_init(void);
+
+#endif /* _SNVS_SECURITY_SC_H */
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index debed6bac7..140e8bbabd 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -19,7 +19,7 @@
#define LOCK_STATUS BIT(31)
#define LOCK_SEL_MASK BIT(29)
-#define CLKE_MASK BIT(11)
+#define CLKE_MASK BIT(13)
#define RST_MASK BIT(9)
#define BYPASS_MASK BIT(4)
#define MDIV_SHIFT 12
@@ -363,7 +363,8 @@ enum clk_root_src {
EXT_CLK_2,
EXT_CLK_3,
EXT_CLK_4,
- OSC_HDMI_CLK
+ OSC_HDMI_CLK,
+ ARM_A53_ALT_CLK,
};
enum clk_ccgr_index {
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 38a6f5966b..9dda6ddc8c 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -153,6 +153,7 @@ enum clk_root_src {
EXT_CLK_3,
EXT_CLK_4,
OSC_27M_CLK,
+ ARM_A53_ALT_CLK,
};
/* CCGR index */
@@ -419,7 +420,7 @@ enum clk_src_index {
enum frac_pll_out_val {
FRAC_PLL_OUT_1000M,
- FRAC_PLL_OUT_1600M,
+ FRAC_PLL_OUT_800M,
};
void init_nand_clk(void);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 35b39b1f86..2a997f280d 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -16,7 +16,7 @@
#define is_soc_rev(rev) (soc_rev() == rev)
/* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define cpu_type(rev) (((rev) >> 12) & 0x1ff)
#define soc_type(rev) (((rev) >> 12) & 0xf0)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
@@ -37,13 +37,15 @@
#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
-#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
-#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
+#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
+#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
@@ -53,7 +55,14 @@
#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
-#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN))
+#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
+ is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
+ is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
+#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
+#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
+#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
+#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
+#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8482f5446c..b839aa7a50 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -57,7 +57,7 @@ obj-y += interrupts_64.o
else
obj-y += interrupts.o
endif
-ifndef CONFIG_SYSRESET
+ifndef CONFIG_$(SPL_TPL_)SYSRESET
obj-y += reset.o
endif
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index bfa85c64c6..e83f6934cd 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -95,7 +95,17 @@ const char *get_imx_type(u32 imxtype)
case MXC_CPU_IMX8MP:
return "8MP"; /* Quad-core version of the imx8mp */
case MXC_CPU_IMX8MN:
- return "8MNano";/* Quad-core version of the imx8mn */
+ return "8MNano Quad"; /* Quad-core version */
+ case MXC_CPU_IMX8MND:
+ return "8MNano Dual"; /* Dual-core version */
+ case MXC_CPU_IMX8MNS:
+ return "8MNano Solo"; /* Single-core version */
+ case MXC_CPU_IMX8MNL:
+ return "8MNano QuadLite"; /* Quad-core Lite version */
+ case MXC_CPU_IMX8MNDL:
+ return "8MNano DualLite"; /* Dual-core Lite version */
+ case MXC_CPU_IMX8MNSL:
+ return "8MNano SoloLite"; /* Single-core Lite version */
case MXC_CPU_IMX8MM:
return "8MMQ"; /* Quad-core version of the imx8mm */
case MXC_CPU_IMX8MML:
@@ -109,7 +119,11 @@ const char *get_imx_type(u32 imxtype)
case MXC_CPU_IMX8MMSL:
return "8MMSL"; /* Single-core Lite version of the imx8mm */
case MXC_CPU_IMX8MQ:
- return "8MQ"; /* Quad-core version of the imx8m */
+ return "8MQ"; /* Quad-core version of the imx8mq */
+ case MXC_CPU_IMX8MQL:
+ return "8MQLite"; /* Quad-core Lite version of the imx8mq */
+ case MXC_CPU_IMX8MD:
+ return "8MD"; /* Dual-core version of the imx8mq */
case MXC_CPU_MX7S:
return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
@@ -314,6 +328,7 @@ enum cpu_speed {
OCOTP_TESTER3_SPEED_GRADE1,
OCOTP_TESTER3_SPEED_GRADE2,
OCOTP_TESTER3_SPEED_GRADE3,
+ OCOTP_TESTER3_SPEED_GRADE4,
};
u32 get_cpu_speed_grade_hz(void)
@@ -326,17 +341,28 @@ u32 get_cpu_speed_grade_hz(void)
val = readl(&fuse->tester3);
val >>= OCOTP_TESTER3_SPEED_SHIFT;
- val &= 0x3;
+
+ if (is_imx8mn() || is_imx8mp()) {
+ val &= 0xf;
+ return 2300000000 - val * 100000000;
+ }
+
+ if (is_imx8mm())
+ val &= 0x7;
+ else
+ val &= 0x3;
switch(val) {
case OCOTP_TESTER3_SPEED_GRADE0:
return 800000000;
case OCOTP_TESTER3_SPEED_GRADE1:
- return is_mx7() ? 500000000 : 1000000000;
+ return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
case OCOTP_TESTER3_SPEED_GRADE2:
- return is_mx7() ? 1000000000 : 1300000000;
+ return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
case OCOTP_TESTER3_SPEED_GRADE3:
- return is_mx7() ? 1200000000 : 1500000000;
+ return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
+ case OCOTP_TESTER3_SPEED_GRADE4:
+ return 2000000000;
}
return 0;
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 5827ab334f..1f8add015f 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -90,4 +90,17 @@ source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"
source "board/siemens/capricorn/Kconfig"
+config IMX_SNVS_SEC_SC
+ bool "Support SNVS configuration"
+ help
+ Allow to configure the SNVS via SCU API to configure tampers and secure
+ violation.
+
+config IMX_SNVS_SEC_SC_AUTO
+ bool "Support SNVS configuration command"
+ depends on IMX_SNVS_SEC_SC
+ help
+ This configuration will apply the selected configurations automatically
+ at boot.
+
endif
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 7ffb7e95b2..bbb41adbe4 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_AHAB_BOOT) += ahab.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
endif
+obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index cf3c7d762a..6d25abe5ce 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -75,7 +75,7 @@ int authenticate_os_container(ulong addr)
memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
- err = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+ err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (err) {
printf("Authenticate container hdr failed, return %d\n",
@@ -90,22 +90,21 @@ int authenticate_os_container(ulong addr)
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));
- debug("img %d, dst 0x%llx, src 0x%lx, size 0x%x\n",
- i, img->dst, img->offset + addr, img->size);
+ debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
+ i, (uint32_t) img->dst, img->offset + addr, img->size);
memcpy((void *)img->dst, (const void *)(img->offset + addr),
img->size);
s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE);
+ e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
flush_dcache_range(s, e);
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr, s, e);
if (err) {
- printf("Not found memreg for image: %d, error %d\n",
- i, err);
+ printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err);
ret = -ENOMEM;
goto exit;
}
@@ -123,7 +122,7 @@ int authenticate_os_container(ulong addr)
goto exit;
}
- err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+ err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
(1 << i));
if (err) {
printf("Authenticate img %d failed, return %d\n",
@@ -144,7 +143,7 @@ int authenticate_os_container(ulong addr)
}
exit:
- if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE)
+ if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE)
printf("Error: release container failed!\n");
return ret;
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
index 00fe4670bb..76d6571d8b 100644
--- a/arch/arm/mach-imx/imx8/misc.c
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -2,6 +2,7 @@
#include <common.h>
#include <asm/arch/sci/sci.h>
#include <asm/mach-imx/sys_proto.h>
+#include <imx_sip.h>
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
{
@@ -26,9 +27,6 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
return 0;
}
-#define FSL_SIP_BUILDINFO 0xC2000003
-#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
-
void build_info(void)
{
u32 seco_build = 0, seco_commit = 0;
@@ -51,8 +49,8 @@ void build_info(void)
}
/* Get ARM Trusted Firmware commit id */
- atf_commit = call_imx_sip(FSL_SIP_BUILDINFO,
- FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+ atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
+ IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
if (atf_commit == 0xffffffff) {
debug("ATF does not support build info\n");
atf_commit = 0x30; /* Display 0 */
diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c
index b57e68e412..cc8a51ad55 100644
--- a/arch/arm/mach-imx/imx8/parse-container.c
+++ b/arch/arm/mach-imx/imx8/parse-container.c
@@ -23,23 +23,23 @@ static int authenticate_image(struct boot_img_t *img, int image_index)
int err;
int ret = 0;
- debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
- image_index, img->dst, img->offset, img->size);
+ debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
+ image_index, (uint32_t)img->dst, img->offset, img->size);
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr,
img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
- ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE));
+ ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
if (err) {
- printf("can't find memreg for image: %d, err %d\n",
- image_index, err);
+ printf("can't find memreg for image %d load address 0x%x, error %d\n",
+ image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err);
return -ENOMEM;
}
err = sc_rm_get_memreg_info(-1, mr, &start, &end);
if (!err)
- debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+ debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_FULL);
@@ -49,7 +49,7 @@ static int authenticate_image(struct boot_img_t *img, int image_index)
return -EPERM;
}
- err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+ err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
1 << image_index);
if (err) {
printf("authenticate img %d failed, return %d\n",
@@ -168,7 +168,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
- ret = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+ ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (ret) {
printf("authenticate container hdr failed, return %d\n", ret);
@@ -194,7 +194,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
end_auth:
#ifdef CONFIG_AHAB_BOOT
- if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0))
+ if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
printf("Error: release container failed!\n");
#endif
return ret;
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
new file mode 100644
index 0000000000..73f5651161
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP.
+ */
+
+/*
+ * Configuration of the Tamper pins in different mode:
+ * - default (no tamper pins): _default_
+ * - passive mode expecting VCC on the line: "_passive_vcc_"
+ * - passive mode expecting VCC on the line: "_passive_gnd_"
+ * - active mode: "_active_"
+ */
+
+#include <command.h>
+#include <log.h>
+#include <stddef.h>
+#include <common.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch-imx8/imx8-pins.h>
+#include <asm/arch-imx8/snvs_security_sc.h>
+
+/* Access to gd */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SC_WRITE_CONF 1
+
+#define PGD_HEX_VALUE 0x41736166
+#define SRTC_EN 0x1
+#define DP_EN BIT(5)
+
+struct snvs_security_sc_conf {
+ struct snvs_hp_conf {
+ u32 lock; /* HPLR - HP Lock */
+ u32 __cmd; /* HPCOMR - HP Command */
+ u32 __ctl; /* HPCR - HP Control */
+ u32 secvio_intcfg; /* HPSICR - Security Violation Int
+ * Config
+ */
+ u32 secvio_ctl; /* HPSVCR - Security Violation Control*/
+ u32 status; /* HPSR - HP Status */
+ u32 secvio_status; /* HPSVSR - Security Violation Status */
+ u32 __ha_counteriv; /* High Assurance Counter IV */
+ u32 __ha_counter; /* High Assurance Counter */
+ u32 __rtc_msb; /* Real Time Clock/Counter MSB */
+ u32 __rtc_lsb; /* Real Time Counter LSB */
+ u32 __time_alarm_msb; /* Time Alarm MSB */
+ u32 __time_alarm_lsb; /* Time Alarm LSB */
+ } hp;
+ struct snvs_lp_conf {
+ u32 lock;
+ u32 __ctl;
+ u32 __mstr_key_ctl; /* Master Key Control */
+ u32 secvio_ctl; /* Security Violation Control */
+ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration*/
+ u32 tamper_det_cfg; /* Tamper Detectors Configuration */
+ u32 status;
+ u32 __srtc_msb; /* Secure Real Time Clock/Counter MSB */
+ u32 __srtc_lsb; /* Secure Real Time Clock/Counter LSB */
+ u32 __time_alarm; /* Time Alarm */
+ u32 __smc_msb; /* Secure Monotonic Counter MSB */
+ u32 __smc_lsb; /* Secure Monotonic Counter LSB */
+ u32 __pwr_glitch_det; /* Power Glitch Detector */
+ u32 __gen_purpose;
+ u8 __zmk[32]; /* Zeroizable Master Key */
+ u32 __rsvd0;
+ u32 __gen_purposes[4]; /* gp0_30 to gp0_33 */
+ u32 tamper_det_cfg2; /* Tamper Detectors Configuration2 */
+ u32 tamper_det_status; /* Tamper Detectors status */
+ u32 tamper_filt1_cfg; /* Tamper Glitch Filter1 Configuration*/
+ u32 tamper_filt2_cfg; /* Tamper Glitch Filter2 Configuration*/
+ u32 __rsvd1[4];
+ u32 act_tamper1_cfg; /* Active Tamper1 Configuration */
+ u32 act_tamper2_cfg; /* Active Tamper2 Configuration */
+ u32 act_tamper3_cfg; /* Active Tamper3 Configuration */
+ u32 act_tamper4_cfg; /* Active Tamper4 Configuration */
+ u32 act_tamper5_cfg; /* Active Tamper5 Configuration */
+ u32 __rsvd2[3];
+ u32 act_tamper_ctl; /* Active Tamper Control */
+ u32 act_tamper_clk_ctl; /* Active Tamper Clock Control */
+ u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
+ u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
+ } lp;
+};
+
+static struct snvs_security_sc_conf snvs_default_config = {
+ .hp = {
+ .lock = 0x1f0703ff,
+ .secvio_ctl = 0x3000007f,
+ },
+ .lp = {
+ .lock = 0x1f0003ff,
+ .secvio_ctl = 0x36,
+ .tamper_filt_cfg = 0,
+ .tamper_det_cfg = 0x76, /* analogic tampers
+ * + rollover tampers
+ */
+ .tamper_det_cfg2 = 0,
+ .tamper_filt1_cfg = 0,
+ .tamper_filt2_cfg = 0,
+ .act_tamper1_cfg = 0,
+ .act_tamper2_cfg = 0,
+ .act_tamper3_cfg = 0,
+ .act_tamper4_cfg = 0,
+ .act_tamper5_cfg = 0,
+ .act_tamper_ctl = 0,
+ .act_tamper_clk_ctl = 0,
+ .act_tamper_routing_ctl1 = 0,
+ .act_tamper_routing_ctl2 = 0,
+ }
+};
+
+static struct snvs_security_sc_conf snvs_passive_vcc_config = {
+ .hp = {
+ .lock = 0x1f0703ff,
+ .secvio_ctl = 0x3000007f,
+ },
+ .lp = {
+ .lock = 0x1f0003ff,
+ .secvio_ctl = 0x36,
+ .tamper_filt_cfg = 0,
+ .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+ * + analogic tampers
+ * + rollover tampers
+ */
+ .tamper_det_cfg2 = 0,
+ .tamper_filt1_cfg = 0,
+ .tamper_filt2_cfg = 0,
+ .act_tamper1_cfg = 0,
+ .act_tamper2_cfg = 0,
+ .act_tamper3_cfg = 0,
+ .act_tamper4_cfg = 0,
+ .act_tamper5_cfg = 0,
+ .act_tamper_ctl = 0,
+ .act_tamper_clk_ctl = 0,
+ .act_tamper_routing_ctl1 = 0,
+ .act_tamper_routing_ctl2 = 0,
+ }
+};
+
+static struct snvs_security_sc_conf snvs_passive_gnd_config = {
+ .hp = {
+ .lock = 0x1f0703ff,
+ .secvio_ctl = 0x3000007f,
+ },
+ .lp = {
+ .lock = 0x1f0003ff,
+ .secvio_ctl = 0x36,
+ .tamper_filt_cfg = 0,
+ .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+ * + analogic tampers
+ * + rollover tampers
+ */
+ .tamper_det_cfg2 = 0,
+ .tamper_filt1_cfg = 0,
+ .tamper_filt2_cfg = 0,
+ .act_tamper1_cfg = 0,
+ .act_tamper2_cfg = 0,
+ .act_tamper3_cfg = 0,
+ .act_tamper4_cfg = 0,
+ .act_tamper5_cfg = 0,
+ .act_tamper_ctl = 0,
+ .act_tamper_clk_ctl = 0,
+ .act_tamper_routing_ctl1 = 0,
+ .act_tamper_routing_ctl2 = 0,
+ }
+};
+
+static struct snvs_security_sc_conf snvs_active_config = {
+ .hp = {
+ .lock = 0x1f0703ff,
+ .secvio_ctl = 0x3000007f,
+ },
+ .lp = {
+ .lock = 0x1f0003ff,
+ .secvio_ctl = 0x36,
+ .tamper_filt_cfg = 0x00800000, /* Enable filtering */
+ .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+ * + rollover tampers
+ */
+ .tamper_det_cfg2 = 0,
+ .tamper_filt1_cfg = 0,
+ .tamper_filt2_cfg = 0,
+ .act_tamper1_cfg = 0x84001111,
+ .act_tamper2_cfg = 0,
+ .act_tamper3_cfg = 0,
+ .act_tamper4_cfg = 0,
+ .act_tamper5_cfg = 0,
+ .act_tamper_ctl = 0x00010001,
+ .act_tamper_clk_ctl = 0,
+ .act_tamper_routing_ctl1 = 0x1,
+ .act_tamper_routing_ctl2 = 0,
+ }
+};
+
+static struct snvs_security_sc_conf *get_snvs_config(void)
+{
+ return &snvs_default_config;
+}
+
+struct snvs_dgo_conf {
+ u32 tamper_offset_ctl;
+ u32 tamper_pull_ctl;
+ u32 tamper_ana_test_ctl;
+ u32 tamper_sensor_trim_ctl;
+ u32 tamper_misc_ctl;
+ u32 tamper_core_volt_mon_ctl;
+};
+
+static struct snvs_dgo_conf snvs_dgo_default_config = {
+ .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+ .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+ .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+ .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+ .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+ .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+ .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf snvs_dgo_active_config = {
+ .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+ .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf *get_snvs_dgo_config(void)
+{
+ return &snvs_dgo_default_config;
+}
+
+struct tamper_pin_cfg {
+ u32 pad;
+ u32 mux_conf;
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+ {SC_P_CSI_D00, 0}, /* Tamp_Out0 */
+ {SC_P_CSI_D01, 0}, /* Tamp_Out1 */
+ {SC_P_CSI_D02, 0}, /* Tamp_Out2 */
+ {SC_P_CSI_D03, 0}, /* Tamp_Out3 */
+ {SC_P_CSI_D04, 0}, /* Tamp_Out4 */
+ {SC_P_CSI_D05, 0}, /* Tamp_In0 */
+ {SC_P_CSI_D06, 0}, /* Tamp_In1 */
+ {SC_P_CSI_D07, 0}, /* Tamp_In2 */
+ {SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
+ {SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+ {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+ {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+ {SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
+ {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+#define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config
+
+static struct tamper_pin_cfg *get_tamper_pin_cfg_list(u32 *size)
+{
+ *size = sizeof(TAMPER_PIN_LIST_CHOSEN) /
+ sizeof(TAMPER_PIN_LIST_CHOSEN[0]);
+
+ return TAMPER_PIN_LIST_CHOSEN;
+}
+
+#define SC_CONF_OFFSET_OF(_field) \
+ (offsetof(struct snvs_security_sc_conf, _field))
+
+static u32 ptr_value(u32 *_p)
+{
+ return (_p) ? *_p : 0xdeadbeef;
+}
+
+static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
+ u32 *_p3, u32 *_p4, u32 *_p5,
+ u32 _cnt)
+{
+ int scierr = 0;
+ u32 d1 = ptr_value(_p1);
+ u32 d2 = ptr_value(_p2);
+ u32 d3 = ptr_value(_p3);
+ u32 d4 = ptr_value(_p4);
+ u32 d5 = ptr_value(_p5);
+
+ scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
+ &d4, &d4, _cnt);
+ if (scierr != SC_ERR_NONE) {
+ printf("Failed to set secvio configuration\n");
+ debug("Failed to set conf id 0x%x with values ", id);
+ debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
+ d1, d2, d3, d4, d5, _cnt);
+ goto exit;
+ }
+
+ if (_p1)
+ *(u32 *)_p1 = d1;
+ if (_p2)
+ *(u32 *)_p2 = d2;
+ if (_p3)
+ *(u32 *)_p3 = d3;
+ if (_p4)
+ *(u32 *)_p4 = d4;
+ if (_p5)
+ *(u32 *)_p5 = d5;
+
+exit:
+ return scierr;
+}
+
+#define SC_CHECK_WRITE1(id, _p1) \
+ check_write_secvio_config(id, _p1, NULL, NULL, NULL, NULL, 1)
+
+static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
+{
+ int scierr = 0;
+
+ debug("%s\n", __func__);
+
+ debug("Applying config:\n"
+ "\thp.lock = 0x%.8x\n"
+ "\thp.secvio_ctl = 0x%.8x\n"
+ "\tlp.lock = 0x%.8x\n"
+ "\tlp.secvio_ctl = 0x%.8x\n"
+ "\tlp.tamper_filt_cfg = 0x%.8x\n"
+ "\tlp.tamper_det_cfg = 0x%.8x\n"
+ "\tlp.tamper_det_cfg2 = 0x%.8x\n"
+ "\tlp.tamper_filt1_cfg = 0x%.8x\n"
+ "\tlp.tamper_filt2_cfg = 0x%.8x\n"
+ "\tlp.act_tamper1_cfg = 0x%.8x\n"
+ "\tlp.act_tamper2_cfg = 0x%.8x\n"
+ "\tlp.act_tamper3_cfg = 0x%.8x\n"
+ "\tlp.act_tamper4_cfg = 0x%.8x\n"
+ "\tlp.act_tamper5_cfg = 0x%.8x\n"
+ "\tlp.act_tamper_ctl = 0x%.8x\n"
+ "\tlp.act_tamper_clk_ctl = 0x%.8x\n"
+ "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n"
+ "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n",
+ cnf->hp.lock,
+ cnf->hp.secvio_ctl,
+ cnf->lp.lock,
+ cnf->lp.secvio_ctl,
+ cnf->lp.tamper_filt_cfg,
+ cnf->lp.tamper_det_cfg,
+ cnf->lp.tamper_det_cfg2,
+ cnf->lp.tamper_filt1_cfg,
+ cnf->lp.tamper_filt2_cfg,
+ cnf->lp.act_tamper1_cfg,
+ cnf->lp.act_tamper2_cfg,
+ cnf->lp.act_tamper3_cfg,
+ cnf->lp.act_tamper4_cfg,
+ cnf->lp.act_tamper5_cfg,
+ cnf->lp.act_tamper_ctl,
+ cnf->lp.act_tamper_clk_ctl,
+ cnf->lp.act_tamper_routing_ctl1,
+ cnf->lp.act_tamper_routing_ctl2);
+
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
+ &cnf->lp.tamper_filt_cfg,
+ &cnf->lp.tamper_filt1_cfg,
+ &cnf->lp.tamper_filt2_cfg, NULL,
+ NULL, 3);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Configure AT */
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
+ &cnf->lp.act_tamper1_cfg,
+ &cnf->lp.act_tamper2_cfg,
+ &cnf->lp.act_tamper2_cfg,
+ &cnf->lp.act_tamper2_cfg,
+ &cnf->lp.act_tamper2_cfg, 5);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Configure AT routing */
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
+ &cnf->lp.act_tamper_routing_ctl1,
+ &cnf->lp.act_tamper_routing_ctl2,
+ NULL, NULL, NULL, 2);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Configure AT frequency */
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
+ &cnf->lp.act_tamper_clk_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Activate the ATs */
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
+ &cnf->lp.act_tamper_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Activate the detectors */
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
+ &cnf->lp.tamper_det_cfg,
+ &cnf->lp.tamper_det_cfg2, NULL, NULL,
+ NULL, 2);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Configure LP secvio */
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
+ &cnf->lp.secvio_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Configure HP secvio */
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
+ &cnf->hp.secvio_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Lock access */
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+exit:
+ return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
+{
+ int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
+
+ if (scierr != SC_ERR_NONE) {
+ printf("Failed to set dgo configuration\n");
+ debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
+ }
+
+ return scierr;
+}
+
+static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
+{
+ int scierr = 0;
+
+ debug("%s\n", __func__);
+
+ debug("Applying config:\n"
+ "\ttamper_offset_ctl = 0x%.8x\n"
+ "\ttamper_pull_ctl = 0x%.8x\n"
+ "\ttamper_ana_test_ctl = 0x%.8x\n"
+ "\ttamper_sensor_trim_ctl = 0x%.8x\n"
+ "\ttamper_misc_ctl = 0x%.8x\n"
+ "\ttamper_core_volt_mon_ctl = 0x%.8x\n",
+ cnf->tamper_offset_ctl,
+ cnf->tamper_pull_ctl,
+ cnf->tamper_ana_test_ctl,
+ cnf->tamper_sensor_trim_ctl,
+ cnf->tamper_misc_ctl,
+ cnf->tamper_core_volt_mon_ctl);
+
+ dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ /* Last as it could lock the writes */
+ dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+exit:
+ return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+static int pad_write(u32 _pad, u32 _value)
+{
+ int scierr = sc_pad_set(-1, _pad, _value);
+
+ if (scierr != SC_ERR_NONE) {
+ printf("Failed to set pad configuration\n");
+ debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
+ }
+
+ return scierr;
+}
+
+static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
+{
+ int scierr = 0;
+ u32 idx;
+
+ debug("%s\n", __func__);
+
+ for (idx = 0; idx < size; idx++) {
+ debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
+ confs[idx].mux_conf);
+ pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+ }
+
+exit:
+ return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+int examples(void)
+{
+ u32 size;
+ struct snvs_security_sc_conf *snvs_conf;
+ struct snvs_dgo_conf *snvs_dgo_conf;
+ struct tamper_pin_cfg *tamper_pin_conf;
+
+ /* Caller */
+ snvs_conf = get_snvs_config();
+ snvs_dgo_conf = get_snvs_dgo_config();
+ tamper_pin_conf = get_tamper_pin_cfg_list(&size);
+
+ /* Default */
+ snvs_conf = &snvs_default_config;
+ snvs_dgo_conf = &snvs_dgo_default_config;
+ tamper_pin_conf = tamper_pin_list_default_config;
+
+ /* Passive tamper expecting VCC on the line */
+ snvs_conf = &snvs_passive_vcc_config;
+ snvs_dgo_conf = &snvs_dgo_passive_vcc_config;
+ tamper_pin_conf = tamper_pin_list_passive_vcc_config;
+
+ /* Passive tamper expecting GND on the line */
+ snvs_conf = &snvs_passive_gnd_config;
+ snvs_dgo_conf = &snvs_dgo_passive_gnd_config;
+ tamper_pin_conf = tamper_pin_list_passive_gnd_config;
+
+ /* Active tamper */
+ snvs_conf = &snvs_active_config;
+ snvs_dgo_conf = &snvs_dgo_active_config;
+ tamper_pin_conf = tamper_pin_list_active_config;
+
+ return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf;
+}
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+int snvs_security_sc_init(void)
+{
+ int err = 0;
+
+ struct snvs_security_sc_conf *snvs_conf;
+ struct snvs_dgo_conf *snvs_dgo_conf;
+ struct tamper_pin_cfg *tamper_pin_conf;
+ u32 size;
+
+ debug("%s\n", __func__);
+
+ snvs_conf = get_snvs_config();
+ snvs_dgo_conf = get_snvs_dgo_config();
+
+ tamper_pin_conf = get_tamper_pin_cfg_list(&size);
+
+ err = apply_tamper_pin_list_config(tamper_pin_conf, size);
+ if (err) {
+ debug("Failed to set pins\n");
+ goto exit;
+ }
+
+ err = apply_snvs_dgo_config(snvs_dgo_conf);
+ if (err) {
+ debug("Failed to set dgo\n");
+ goto exit;
+ }
+
+ err = apply_snvs_config(snvs_conf);
+ if (err) {
+ debug("Failed to set snvs\n");
+ goto exit;
+ }
+
+exit:
+ return err;
+}
+#endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */
+
+static char snvs_cfg_help_text[] =
+ "snvs_cfg\n"
+ "\thp.lock\n"
+ "\thp.secvio_ctl\n"
+ "\tlp.lock\n"
+ "\tlp.secvio_ctl\n"
+ "\tlp.tamper_filt_cfg\n"
+ "\tlp.tamper_det_cfg\n"
+ "\tlp.tamper_det_cfg2\n"
+ "\tlp.tamper_filt1_cfg\n"
+ "\tlp.tamper_filt2_cfg\n"
+ "\tlp.act_tamper1_cfg\n"
+ "\tlp.act_tamper2_cfg\n"
+ "\tlp.act_tamper3_cfg\n"
+ "\tlp.act_tamper4_cfg\n"
+ "\tlp.act_tamper5_cfg\n"
+ "\tlp.act_tamper_ctl\n"
+ "\tlp.act_tamper_clk_ctl\n"
+ "\tlp.act_tamper_routing_ctl1\n"
+ "\tlp.act_tamper_routing_ctl2\n"
+ "\n"
+ "ALL values should be in hexadecimal format";
+
+#define NB_REGISTERS 18
+static int do_snvs_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int err = 0;
+ u32 idx = 0;
+
+ struct snvs_security_sc_conf conf = {0};
+
+ if (argc != (NB_REGISTERS + 1))
+ return CMD_RET_USAGE;
+
+ conf.hp.lock = simple_strtoul(argv[++idx], NULL, 16);
+ conf.hp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.lock = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_filt_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_det_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_det_cfg2 = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_filt1_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_filt2_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper1_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper2_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper3_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper4_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper5_cfg = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper_clk_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper_routing_ctl1 = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.act_tamper_routing_ctl2 = simple_strtoul(argv[++idx], NULL, 16);
+
+ err = apply_snvs_config(&conf);
+
+ return err;
+}
+
+U_BOOT_CMD(snvs_cfg,
+ NB_REGISTERS + 1, 1, do_snvs_cfg,
+ "Security violation configuration",
+ snvs_cfg_help_text
+);
+
+static char snvs_dgo_cfg_help_text[] =
+ "snvs_dgo_cfg\n"
+ "\ttamper_offset_ctl\n"
+ "\ttamper_pull_ctl\n"
+ "\ttamper_ana_test_ctl\n"
+ "\ttamper_sensor_trim_ctl\n"
+ "\ttamper_misc_ctl\n"
+ "\ttamper_core_volt_mon_ctl\n"
+ "\n"
+ "ALL values should be in hexadecimal format";
+
+static int do_snvs_dgo_cfg(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err = 0;
+ u32 idx = 0;
+
+ struct snvs_dgo_conf conf = {0};
+
+ if (argc != (6 + 1))
+ return CMD_RET_USAGE;
+
+ conf.tamper_offset_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.tamper_pull_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.tamper_ana_test_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.tamper_sensor_trim_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.tamper_misc_ctl = simple_strtoul(argv[++idx], NULL, 16);
+ conf.tamper_core_volt_mon_ctl = simple_strtoul(argv[++idx], NULL, 16);
+
+ err = apply_snvs_dgo_config(&conf);
+
+ return err;
+}
+
+U_BOOT_CMD(snvs_dgo_cfg,
+ 7, 1, do_snvs_dgo_cfg,
+ "SNVS DGO configuration",
+ snvs_dgo_cfg_help_text
+);
+
+static char tamper_pin_cfg_help_text[] =
+ "snvs_dgo_cfg\n"
+ "\tpad\n"
+ "\tvalue\n"
+ "\n"
+ "ALL values should be in hexadecimal format";
+
+static int do_tamper_pin_cfg(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err = 0;
+ u32 idx = 0;
+
+ struct tamper_pin_cfg conf = {0};
+
+ if (argc != (2 + 1))
+ return CMD_RET_USAGE;
+
+ conf.pad = simple_strtoul(argv[++idx], NULL, 10);
+ conf.mux_conf = simple_strtoul(argv[++idx], NULL, 16);
+
+ err = apply_tamper_pin_list_config(&conf, 1);
+
+ return err;
+}
+
+U_BOOT_CMD(tamper_pin_cfg,
+ 3, 1, do_tamper_pin_cfg,
+ "tamper pin configuration",
+ tamper_pin_cfg_help_text
+);
+
+static char snvs_clear_status_help_text[] =
+ "snvs_clear_status\n"
+ "\tHPSR\n"
+ "\tHPSVSR\n"
+ "\tLPSR\n"
+ "\tLPTDSR\n"
+ "\n"
+ "Write the status registers with the value provided,"
+ " clearing the status";
+
+static int do_snvs_clear_status(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int scierr = 0;
+ u32 idx = 0;
+
+ struct snvs_security_sc_conf conf = {0};
+
+ if (argc != (2 + 1))
+ return CMD_RET_USAGE;
+
+ conf.lp.status = simple_strtoul(argv[++idx], NULL, 16);
+ conf.lp.tamper_det_status = simple_strtoul(argv[++idx], NULL, 16);
+
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
+ &conf.lp.status, NULL, NULL, NULL,
+ NULL, 1);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+ scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
+ &conf.lp.tamper_det_status, NULL,
+ NULL, NULL, NULL, 1);
+ if (scierr != SC_ERR_NONE)
+ goto exit;
+
+exit:
+ return (scierr == SC_ERR_NONE) ? 0 : 1;
+}
+
+U_BOOT_CMD(snvs_clear_status,
+ 3, 1, do_snvs_clear_status,
+ "snvs clear status",
+ snvs_clear_status_help_text
+);
+
+static char snvs_sec_status_help_text[] =
+ "snvs_sec_status\n"
+ "Display information about the security related to tamper and secvio";
+
+static int do_snvs_sec_status(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int scierr;
+ u32 idx;
+
+ u32 data[5];
+
+ u32 pads[] = {
+ SC_P_CSI_D00,
+ SC_P_CSI_D01,
+ SC_P_CSI_D02,
+ SC_P_CSI_D03,
+ SC_P_CSI_D04,
+ SC_P_CSI_D05,
+ SC_P_CSI_D06,
+ SC_P_CSI_D07,
+ SC_P_CSI_HSYNC,
+ SC_P_CSI_VSYNC,
+ };
+
+ u32 fuses[] = {
+ 14,
+ 30,
+ 31,
+ 260,
+ 261,
+ 262,
+ 263,
+ 768,
+ };
+
+ struct snvs_reg {
+ u32 id;
+ u32 nb;
+ } snvs[] = {
+ /* Locks */
+ {0x0, 1},
+ {0x34, 1},
+ /* Security violation */
+ {0xc, 1},
+ {0x10, 1},
+ {0x18, 1},
+ {0x40, 1},
+ /* Temper detectors */
+ {0x48, 2},
+ {0x4c, 1},
+ {0xa4, 1},
+ /* */
+ {0x44, 3},
+ {0xe0, 1},
+ {0xe4, 1},
+ {0xe8, 2},
+ /* Misc */
+ {0x3c, 1},
+ {0x5c, 2},
+ {0x64, 1},
+ {0xf8, 2},
+ };
+
+ u32 dgo[] = {
+ 0x0,
+ 0x10,
+ 0x20,
+ 0x30,
+ 0x40,
+ 0x50,
+ };
+
+ /* Pins */
+ printf("Pins:\n");
+ for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
+ u8 pad_id = pads[idx];
+
+ scierr = sc_pad_get(-1, pad_id, &data[0]);
+ if (scierr == 0)
+ printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
+ else
+ printf("Failed to read Pin %d\n", pad_id);
+ }
+
+ /* Fuses */
+ printf("Fuses:\n");
+ for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
+ u32 fuse_id = fuses[idx];
+
+ scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
+ if (scierr == 0)
+ printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
+ else
+ printf("Failed to read Fuse %d\n", fuse_id);
+ }
+
+ /* SNVS */
+ printf("SNVS:\n");
+ for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
+ struct snvs_reg *reg = &snvs[idx];
+
+ scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
+ &data[1], &data[2], &data[3],
+ &data[4], reg->nb);
+ if (scierr == 0) {
+ int subidx;
+
+ printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
+ for (subidx = 0; subidx < reg->nb; subidx++)
+ printf(" %.8x", data[subidx]);
+ printf("\n");
+ } else {
+ printf("Failed to read SNVS %d\n", reg->id);
+ }
+ }
+
+ /* DGO */
+ printf("DGO:\n");
+ for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
+ u8 dgo_id = dgo[idx];
+
+ scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
+ if (scierr == 0)
+ printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
+ else
+ printf("Failed to read DGO %d\n", dgo_id);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(snvs_sec_status,
+ 1, 1, do_snvs_sec_status,
+ "tamper pin configuration",
+ snvs_sec_status_help_text
+);
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 58f1758ab6..895f903780 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -32,6 +32,11 @@ config TARGET_IMX8MQ_EVK
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MQ_PHANBELL
+ bool "imx8mq_phanbell"
+ select IMX8MQ
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
select IMX8MM
@@ -62,6 +67,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
+source "board/google/imx8mq_phanbell/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index c423ac0058..91c827f6c0 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll)
}
/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
- if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+ if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
return 0;
- if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+ if ((pll_gnrl_ctl & RST_MASK) == 0)
return 0;
/*
* When BYPASS is equal to 1, PLL enters the bypass mode
* regardless of the values of RESETB
*/
- if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+ if (pll_gnrl_ctl & BYPASS_MASK)
return 24000000u;
- if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+ if (!(pll_gnrl_ctl & LOCK_STATUS)) {
puts("pll not locked\n");
return 0;
}
- if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
+ if (!(pll_gnrl_ctl & CLKE_MASK))
return 0;
- main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
- INTPLL_MAIN_DIV_SHIFT;
- pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
- INTPLL_PRE_DIV_SHIFT;
- post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
- INTPLL_POST_DIV_SHIFT;
+ main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
+ MDIV_SHIFT;
+ pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
+ PDIV_SHIFT;
+ post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
+ SDIV_SHIFT;
- k = pll_fdiv_ctl1 & GENMASK(15, 0);
+ k = pll_fdiv_ctl1 & KDIV_MASK;
return lldiv((main_div * 65536 + k) * 24000000ULL,
65536 * pre_div * (1 << post_div));
@@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ u32 enet1_ref;
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_SIM_ENET, 0);
+
+ /* set enet axi clock 266Mhz */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON |
+ ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+ /* enable clock */
+ clock_enable(CCGR_SIM_ENET, 1);
+ clock_enable(CCGR_ENET1, 1);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index aad9cf13ef..ee18cdee50 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -15,6 +15,8 @@
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+static u32 get_root_clk(enum clk_root_index clock_id);
+
static u32 decode_frac_pll(enum clk_root_src frac_pll)
{
u32 pll_cfg0, pll_cfg1, pllout;
@@ -275,6 +277,8 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
case SYSTEM_PLL2_50M_CLK:
case SYSTEM_PLL3_CLK:
return decode_sscg_pll(root_src);
+ case ARM_A53_ALT_CLK:
+ return get_root_clk(ARM_A53_CLK_ROOT);
default:
return 0;
}
@@ -322,13 +326,26 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
return 0;
}
+u32 get_arm_core_clk(void)
+{
+ enum clk_root_src root_src;
+ u32 root_src_clk;
+
+ if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ return root_src_clk;
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
u32 val;
- switch(clk) {
+ switch (clk) {
case MXC_ARM_CLK:
- return get_root_clk(ARM_A53_CLK_ROOT);
+ return get_arm_core_clk();
case MXC_IPG_CLK:
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
@@ -428,15 +445,13 @@ void init_clk_usdhc(u32 index)
case 0:
clock_enable(CCGR_USDHC1, 0);
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USDHC1, 1);
return;
case 1:
clock_enable(CCGR_USDHC2, 0);
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USDHC2, 1);
return;
default:
@@ -639,7 +654,7 @@ void dram_pll_init(ulong pll_val)
static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
{
void __iomem *pll_cfg0, __iomem *pll_cfg1;
- u32 val_cfg0, val_cfg1;
+ u32 val_cfg0, val_cfg1, divq;
int ret;
switch (pll) {
@@ -647,14 +662,17 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
pll_cfg0 = &ana_pll->arm_pll_cfg0;
pll_cfg1 = &ana_pll->arm_pll_cfg1;
- if (val == FRAC_PLL_OUT_1000M)
+ if (val == FRAC_PLL_OUT_1000M) {
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
- else
+ divq = 0;
+ } else {
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
+ divq = 1;
+ }
val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
FRAC_PLL_REFCLK_DIV_VAL(4) |
- FRAC_PLL_OUTPUT_DIV_VAL(0);
+ FRAC_PLL_OUTPUT_DIV_VAL(divq);
break;
default:
return -EINVAL;
@@ -690,17 +708,14 @@ int clock_init(void)
* We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
*/
grade = get_cpu_temp_grade(NULL, NULL);
- if (!grade) {
+ if (!grade)
frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
- clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
- } else {
- frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
- clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
- }
+ else
+ frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
+
+ /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
+ clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
+
/*
* According to ANAMIX SPEC
* sys pll1 fixed at 800MHz
@@ -747,6 +762,8 @@ static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
freq = decode_frac_pll(ARM_PLL_CLK);
printf("ARM_PLL %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(DRAM_PLL1_CLK);
+ printf("DRAM_PLL %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 8b7a4dad65..b5ed27a923 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -472,33 +472,111 @@ static struct clk_root_map root_array[] = {
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
- {DRAM_PLL1_CLK}
+ {ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
-#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
+#elif defined(CONFIG_IMX8MM)
static struct clk_root_map root_array[] = {
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
},
+ {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+ },
+ {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
+ {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ EXT_CLK_2, EXT_CLK_3}
+ },
+ {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
-#ifdef CONFIG_IMX8MM
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
-#endif
+ {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@@ -509,6 +587,146 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
+ {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+ {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+ },
+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ VIDEO_PLL_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+ {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+ },
+ {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
@@ -529,19 +747,546 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
+ {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
+ {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+ },
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
},
+ {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+ {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+ SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+ },
+ {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+ },
+ {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+ {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+ },
+ {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
+ {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
+ {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+ {ARM_A53_ALT_CLK, ARM_PLL_CLK}
+ },
+};
+#elif defined(CONFIG_IMX8MN)
+static struct clk_root_map root_array[] = {
+ {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+ },
+ {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+ },
+ {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+ },
+ {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+ },
+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ VIDEO_PLL_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+ {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+ {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+ },
+ {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+ {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+ {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+ {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+ {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+ },
+ {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+ {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+ {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+ SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+ },
+ {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+ },
+ {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+ {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+ },
+ {SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
+ {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+ {DRAM_PLL1_CLK}
+ },
+ {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+ {ARM_A53_ALT_CLK, ARM_PLL_CLK}
+ },
};
#elif defined(CONFIG_IMX8MP)
static struct clk_root_map root_array[] = {
@@ -580,6 +1325,26 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
+ {MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+ {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+ AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
+ },
+ {MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+ AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
+ },
+ {HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+ AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
+ },
+ {HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+ {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+ AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
+ },
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
@@ -605,6 +1370,11 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
+ {MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@@ -615,11 +1385,6 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
- {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6,
- {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
- SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
- SYSTEM_PLL1_133M_CLK}
- },
{I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
@@ -798,11 +1563,36 @@ static struct clk_root_map root_array[] = {
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
},
+ {HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
+ {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
},
+ {MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
+ {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
@@ -812,7 +1602,7 @@ static struct clk_root_map root_array[] = {
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
- {DRAM_PLL1_CLK}
+ {ARM_A53_ALT_CLK, ARM_PLL_CLK}
},
};
#endif
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7fcbd53f30..89229da3b6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -165,7 +165,13 @@ static u32 get_cpu_variant_type(u32 type)
u32 value = readl(&fuse->tester4);
- if (type == MXC_CPU_IMX8MM) {
+ if (type == MXC_CPU_IMX8MQ) {
+ if ((value & 0x3) == 0x2)
+ return MXC_CPU_IMX8MD;
+ else if (value & 0x200000)
+ return MXC_CPU_IMX8MQL;
+
+ } else if (type == MXC_CPU_IMX8MM) {
switch (value & 0x3) {
case 2:
if (value & 0x1c0000)
@@ -182,6 +188,23 @@ static u32 get_cpu_variant_type(u32 type)
return MXC_CPU_IMX8MML;
break;
}
+ } else if (type == MXC_CPU_IMX8MN) {
+ switch (value & 0x3) {
+ case 2:
+ if (value & 0x1000000)
+ return MXC_CPU_IMX8MNDL;
+ else
+ return MXC_CPU_IMX8MND;
+ case 3:
+ if (value & 0x1000000)
+ return MXC_CPU_IMX8MNSL;
+ else
+ return MXC_CPU_IMX8MNS;
+ default:
+ if (value & 0x1000000)
+ return MXC_CPU_IMX8MNL;
+ break;
+ }
}
return type;
@@ -202,7 +225,7 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX8MP << 12) | reg;
} else if (major_low == 0x42) {
/* iMX8MN */
- return (MXC_CPU_IMX8MN << 12) | reg;
+ type = get_cpu_variant_type(MXC_CPU_IMX8MN);
} else if (major_low == 0x41) {
type = get_cpu_variant_type(MXC_CPU_IMX8MM);
} else {
@@ -226,6 +249,8 @@ u32 get_cpu_rev(void)
}
}
}
+
+ type = get_cpu_variant_type(type);
}
return (type << 12) | reg;
@@ -364,16 +389,18 @@ int ft_system_setup(void *blob, bd_t *bd)
if (nodeoff < 0)
continue; /* Not found, skip it */
- printf("Found %s node\n", nodes_path[i]);
+ debug("Found %s node\n", nodes_path[i]);
rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
+ if (rc == -FDT_ERR_NOTFOUND)
+ continue;
if (rc) {
printf("Unable to update property %s:%s, err=%s\n",
nodes_path[i], "status", fdt_strerror(rc));
return rc;
}
- printf("Remove %s:%s\n", nodes_path[i],
+ debug("Remove %s:%s\n", nodes_path[i],
"cpu-idle-states");
}
}
@@ -382,21 +409,42 @@ int ft_system_setup(void *blob, bd_t *bd)
}
#endif
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(ulong addr)
{
- struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- if (!addr)
- wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+ /* Clear WDA to trigger WDOG_B immediately */
+ writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
- /* Clear WDA to trigger WDOG_B immediately */
- writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+ while (1) {
+ /*
+ * spin for .5 seconds before reset
+ */
+ }
+}
+#endif
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+static void acquire_buildinfo(void)
+{
+ u64 atf_commit = 0;
+
+ /* Get ARM Trusted Firmware commit id */
+ atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
+ IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+ if (atf_commit == 0xffffffff) {
+ debug("ATF does not support build info\n");
+ atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
+ }
- while (1) {
- /*
- * spin for .5 seconds before reset
- */
- }
+ printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
+}
+
+int arch_misc_init(void)
+{
+ acquire_buildinfo();
+
+ return 0;
}
#endif
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 49bb3b928d..fd3fa04600 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -197,52 +197,35 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
- break;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+ return MMCSD_MODE_FS;
+ else
+ return MMCSD_MODE_RAW;
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
- return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
- return MMCSD_MODE_EMMCBOOT;
-#else
- return MMCSD_MODE_RAW;
-#endif
- break;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+ return MMCSD_MODE_FS;
+ else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+ return MMCSD_MODE_EMMCBOOT;
+ else
+ return MMCSD_MODE_RAW;
default:
puts("spl: ERROR: unsupported device\n");
hang();
}
#else
-/*
- * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used
- * unconditionally to decide about device to use for booting.
- * This is crucial for falcon boot mode, when board boots up (i.e. ROM
- * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot
- * mode is used to load Linux OS from eMMC partition.
- */
-#ifdef CONFIG_SPL_FORCE_MMC_BOOT
switch (boot_device) {
-#else
- switch (spl_boot_device()) {
-#endif
/* for MMC return either RAW or FAT mode */
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
-#if defined(CONFIG_SPL_FS_FAT)
- return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
- return MMCSD_MODE_EMMCBOOT;
-#else
- return MMCSD_MODE_RAW;
-#endif
- break;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+ return MMCSD_MODE_FS;
+ else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+ return MMCSD_MODE_EMMCBOOT;
+ else
+ return MMCSD_MODE_RAW;
default:
puts("spl: ERROR: unsupported device\n");
hang();