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-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c1
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c2
-rw-r--r--arch/arm/cpu/armv8/start.S2
-rw-r--r--arch/arm/imx-common/cache.c9
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode.c2
5 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 595c951ed2..9b9b78eddd 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -237,4 +237,5 @@ void prcm_init()
enable_basic_clocks();
scale_vcores();
setup_dplls();
+ timer_init();
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d580a43b41..a9b12a43ad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
/*
* DDR controller 0 & 1 are on memory complex 0
- * DDR controler 2 is on memory complext 1
+ * DDR controller 2 is on memory complext 1
*/
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index deb44a895f..c3cc8199ca 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -214,7 +214,9 @@ WEAK(lowlevel_init)
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
+#endif
+#ifndef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, 2f
/*
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021cfed..b77548821d 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
/*
+ * Must disable the L2 before changing the latency parameters
+ * and auxiliary control register.
+ */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ /*
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
* accesses as Cacheable no-allocate.
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
}
#endif
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 48e478c5d1..b180f44ce8 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -114,7 +114,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
U_BOOT_CMD(
mmcsetn, 1, 1, do_mmcsetn,
- "Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment",
+ "Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
""
);
#endif