diff options
Diffstat (limited to 'arch/arm')
26 files changed, 466 insertions, 204 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b85635d54..0083bf9ef0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -868,6 +868,8 @@ config ARCH_UNIPHIER select PINCTRL select SPL select SPL_DM + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_PINCTRL select SUPPORT_SPL diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e7039919c7..1eedb39aa5 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -47,5 +47,53 @@ config ZYNQMP_USB config SYS_MALLOC_F_LEN default 0x600 +config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED + bool "Overwrite SPL bootmode" + depends on SPL + help + Overwrite bootmode selected via boot mode pins to tell SPL what should + be the next boot device. + +config SPL_ZYNQMP_ALT_BOOTMODE + hex + default 0x0 if JTAG_MODE + default 0x1 if QSPI_MODE_24BIT + default 0x2 if QSPI_MODE_32BIT + default 0x3 if SD_MODE + default 0x4 if NAND_MODE + default 0x5 if SD_MODE1 + default 0x6 if EMMC_MODE + default 0x7 if USB_MODE + +choice + prompt "Boot mode" + depends on ZYNQMP_ALT_BOOTMODE_ENABLED + default JTAG + +config JTAG_MODE + bool "JTAG_MODE" + +config QSPI_MODE_24BIT + bool "QSPI_MODE_24BIT" + +config QSPI_MODE_32BIT + bool "QSPI_MODE_32BIT" + +config SD_MODE + bool "SD_MODE" + +config SD_MODE1 + bool "SD_MODE1" + +config NAND_MODE + bool "NAND_MODE" + +config EMMC_MODE + bool "EMMC_MODE" + +config USB_MODE + bool "USB" + +endchoice endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 867d2b25a8..04e190537d 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -35,10 +35,29 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +static void ps_mode_reset(ulong mode) +{ + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); + udelay(5); + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | + mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); +} + +/* + * Set default PS_MODE1 which is used for USB ULPI phy reset + * Also other resets can be connected to this certain pin + */ +#ifndef MODE_RESET +# define MODE_RESET PS_MODE1 +#endif + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void) { preloader_console_init(); + ps_mode_reset(MODE_RESET); board_init(); } #endif @@ -48,6 +67,13 @@ u32 spl_boot_device(void) u32 reg = 0; u8 bootmode; +#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) + /* Change default boot mode at run-time */ + writel(BOOT_MODE_USE_ALT | + CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, + &crlapb_base->boot_mode); +#endif + reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; @@ -60,6 +86,10 @@ u32 spl_boot_device(void) case SD_MODE1: return BOOT_DEVICE_MMC1; #endif +#ifdef CONFIG_SPL_DFU_SUPPORT + case USB_MODE: + return BOOT_DEVICE_DFU; +#endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index b0b2b57bb9..e4410339eb 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -31,7 +31,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -41,7 +41,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -51,7 +51,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -61,7 +61,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -79,16 +79,33 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - /* specify compatible in each SoC DTSI */ + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; }; - peri: perictrl@59820000 { - /* specify compatible in each SoC DTSI */ + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - #clock-cells = <1>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; }; timer@60000200 { @@ -114,7 +131,8 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -124,12 +142,18 @@ }; }; - sysctrl: sysctrl@61840000 { - /* specify compatible in each SoC DTSI */ + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0x61840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; + }; }; nand: nand@68000000 { diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi index ffe04f5cb6..0bdbbddd9d 100644 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi @@ -54,12 +54,6 @@ clock-frequency = <25000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <58820000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -69,10 +63,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; }; soc { @@ -89,7 +83,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; clock-frequency = <58820000>; }; @@ -100,7 +94,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; clock-frequency = <58820000>; }; @@ -111,7 +105,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; clock-frequency = <58820000>; }; @@ -122,7 +116,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; clock-frequency = <58820000>; }; @@ -213,6 +207,22 @@ reg = <0x59801000 0x400>; }; + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld11-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld11-peri-reset"; + #reset-cells = <1>; + }; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -220,7 +230,7 @@ interrupts = <0 243 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -230,7 +240,7 @@ interrupts = <0 244 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -240,17 +250,29 @@ interrupts = <0 245 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; - mio: mioctrl@5b3e0000 { - compatible = "socionext,ph1-ld11-mioctrl"; + mioctrl@5b3e0000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x5b3e0000 0x800>; - #clock-cells = <1>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + resets = <&sys_rst 7>; + }; }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -273,6 +295,22 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi index 7497539467..7f97f8816a 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi @@ -78,12 +78,6 @@ clock-frequency = <25000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <58820000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -93,10 +87,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; }; soc { @@ -113,7 +107,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; clock-frequency = <58820000>; }; @@ -124,7 +118,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; clock-frequency = <58820000>; }; @@ -135,7 +129,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; clock-frequency = <58820000>; }; @@ -146,7 +140,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; clock-frequency = <58820000>; }; @@ -237,10 +231,36 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - compatible = "socionext,ph1-ld20-mioctrl"; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld20-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld20-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; }; sd: sdhc@5a400000 { @@ -250,12 +270,13 @@ interrupts = <0 76 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -278,6 +299,22 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld20-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 07f315a2b7..e4884b9516 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -30,12 +30,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -228,7 +222,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -240,7 +234,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -252,7 +246,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -262,7 +256,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -272,7 +266,7 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; aidet@61830000 { @@ -302,22 +296,30 @@ clock-frequency = <36864000>; }; -&mio { - compatible = "socionext,ph1-ld4-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-ld4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-ld4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-ld4-peri-clock"; }; -&peri { - compatible = "socionext,ph1-ld4-perictrl"; - clock-names = "uart", "i2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-ld4-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-ld4-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-ld4-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-ld4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-ld4-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts index 965fe08e38..3f178d239a 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts @@ -89,7 +89,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index e0b28b8291..192ce841e1 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -351,7 +351,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -363,7 +363,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -376,7 +376,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd1>; pinctrl-1 = <&pinctrl_sd1_1v8>; - clocks = <&mio 2>; + clocks = <&mio_clk 2>; bus-width = <4>; }; @@ -387,7 +387,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb3: usb@5a810100 { @@ -397,7 +397,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; aidet@5fc20000 { @@ -444,22 +444,30 @@ clock-frequency = <73728000>; }; -&mio { - compatible = "socionext,ph1-pro4-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-pro4-mio-clock"; }; -&peri { - compatible = "socionext,ph1-pro4-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&mio_rst { + compatible = "socionext,uniphier-pro4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro4-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-pro4-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pro4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro4-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 05f961f588..22a70b1a60 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -38,12 +38,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -367,7 +361,7 @@ interrupts = <0 78 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -380,7 +374,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -423,22 +417,30 @@ clock-frequency = <73728000>; }; -&mio { - compatible = "socionext,ph1-pro5-mioctrl"; - clock-names = "stdmac"; - clocks = <&sysctrl 10>; +&mio_clk { + compatible = "socionext,uniphier-pro5-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro5-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro5-peri-clock"; }; -&peri { - compatible = "socionext,ph1-pro5-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-pro5-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-pro5-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pro5-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro5-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index f3e76b3d1e..116e571e4e 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -86,10 +86,6 @@ u-boot,dm-pre-reloc; }; -&mio { - u-boot,dm-pre-reloc; -}; - &emmc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index d8c44b7a0d..a554b086e8 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -42,12 +42,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -92,7 +86,6 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -103,7 +96,6 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -114,7 +106,6 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -299,12 +290,22 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - compatible = "socionext,ph1-sld3-mioctrl"; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; }; emmc: sdhc@5a400000 { @@ -315,7 +316,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -328,7 +329,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -339,7 +340,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -349,7 +350,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -359,7 +360,7 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; usb3: usb@5a830100 { @@ -369,7 +370,7 @@ interrupts = <0 83 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio 7>, <&mio 6>; + clocks = <&mio_clk 7>, <&mio_clk 6>; }; soc-glue@5f800000 { @@ -388,12 +389,20 @@ reg = <0xf1830000 0x200>; }; - sysctrl: sysctrl@f1840000 { - compatible = "socionext,ph1-sld3-sysctrl"; + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0xf1840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; }; nand: nand@f8000000 { diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index e0376a1e96..1ecce5030f 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -30,12 +30,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -228,7 +222,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -240,7 +234,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -252,7 +246,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -262,7 +256,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -272,7 +266,7 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; aidet@61830000 { @@ -302,22 +296,30 @@ clock-frequency = <80000000>; }; -&mio { - compatible = "socionext,ph1-sld8-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-sld8-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-sld8-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-sld8-peri-clock"; }; -&peri { - compatible = "socionext,ph1-sld8-perictrl"; - clock-names = "uart", "i2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-sld8-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-sld8-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-sld8-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-sld8-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-sld8-reset"; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index 117570352f..7233dc67ab 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -69,7 +69,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 928a0928fd..30ea27034c 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -54,7 +54,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 23a6bfac87..609cbaa9d7 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -52,12 +52,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -366,7 +360,7 @@ interrupts = <0 78 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -379,7 +373,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -427,22 +421,30 @@ clock-frequency = <88900000>; }; -&mio { - compatible = "socionext,proxstream2-mioctrl"; - clock-names = "stdmac"; - clocks = <&sysctrl 10>; +&mio_clk { + compatible = "socionext,uniphier-pxs2-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pxs2-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pxs2-peri-clock"; }; -&peri { - compatible = "socionext,proxstream2-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-pxs2-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pxs2-pinctrl"; }; -&sysctrl { - compatible = "socionext,proxstream2-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pxs2-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pxs2-reset"; }; diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 35964d603b..456c1b0902 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,13 @@ #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 + +#define PS_MODE0 BIT(0) +#define PS_MODE1 BIT(1) +#define PS_MODE2 BIT(2) +#define PS_MODE3 BIT(3) struct crlapb_regs { u32 reserved0[36]; @@ -35,7 +42,9 @@ struct crlapb_regs { u32 boot_mode; /* 0x200 */ u32 reserved3[14]; u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[26]; + u32 reserved4[4]; + u32 boot_pin_ctrl; /* 0x250 */ + u32 reserved5[21]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) @@ -69,7 +78,10 @@ struct iou_scntr_secure { #define SD_MODE1 0x00000005 /* sd 1 */ #define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 #define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 19c38f4083..6f312d6652 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -28,6 +28,7 @@ enum { BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 2e824bb7b8..7bee6c7a29 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -1,20 +1,5 @@ if ARCH_UNIPHIER -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y if !ARCH_UNIPHIER_64BIT - -config SPL_NAND_SUPPORT - default y if !ARM64 - -config SPL_SERIAL_SUPPORT - default y - config SYS_CONFIG_NAME default "uniphier" diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index b57a33f299..b9be52f6cb 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -128,6 +128,7 @@ int board_init(void) sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ sg_set_iectrl(153); led_puts("U1"); + uniphier_ld11_pll_init(); uniphier_ld11_clk_init(); break; #endif diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index c8d59eabe3..95f433e87d 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o dpll-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o else @@ -23,9 +23,10 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o endif +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o diff --git a/arch/arm/mach-uniphier/clk/dpll-ld11.c b/arch/arm/mach-uniphier/clk/dpll-ld11.c new file mode 100644 index 0000000000..7f0677c0d4 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld11.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd) +{ + uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c new file mode 100644 index 0000000000..8a4a748cfd --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +void uniphier_ld11_pll_init(void) +{ + uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ + writel(SC_CA_GEARUPD, SC_CA53_GEARUPD); +} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 5c7cd6b6a4..4e3bee1cd3 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -87,6 +87,7 @@ int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); +int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); @@ -105,6 +106,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd); void uniphier_sld3_pll_init(void); void uniphier_ld4_pll_init(void); void uniphier_pro4_pll_init(void); +void uniphier_ld11_pll_init(void); int uniphier_ld20_pll_init(const struct uniphier_board_data *bd); void uniphier_ld4_clk_init(void); diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c index 758df8d269..e324c94700 100644 --- a/arch/arm/mach-uniphier/init/init-ld11.c +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -31,12 +31,14 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd) led_puts("L2"); - led_puts("L3"); - #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif + led_puts("L3"); + + uniphier_ld11_dpll_init(bd); + led_puts("L4"); { diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 1e52bb1ef1..780fdd176f 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -13,12 +13,14 @@ #define SC_BASE_ADDR 0x61840000 /* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD20: CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD20: misc */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD20: Video codec */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ @@ -61,4 +63,12 @@ #define SC_CLKCTRL7_UMC31 (1 << 1) #define SC_CLKCTRL7_UMC30 (1 << 0) +#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080) +#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084) +#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) +#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) +#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA_GEARUPD (1 << 0) + #endif /* SC64_REGS_H */ |