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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c10
-rw-r--r--arch/arm/cpu/u-boot-spl.lds6
-rw-r--r--arch/arm/include/asm/pl310.h3
-rw-r--r--arch/arm/mach-at91/arm926ejs/u-boot-spl.lds4
-rw-r--r--arch/arm/mach-omap2/am33xx/board.c31
-rw-r--r--arch/arm/mach-omap2/am33xx/ddr.c33
-rw-r--r--arch/arm/mach-rmobile/Kconfig3
-rw-r--r--arch/arm/mach-socfpga/misc.c16
9 files changed, 82 insertions, 25 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49f01f1ff1..5be959bf8b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -847,6 +847,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+ imply L2X0_CACHE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 038405173e..9ca397e73c 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -443,6 +443,7 @@ inline void flush_dcache_all(void)
debug("flushing dcache successfully.\n");
}
+#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
/*
* Invalidates range in all levels of D-cache/unified cache
*/
@@ -458,6 +459,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
{
__asm_flush_dcache_range(start, stop);
}
+#else
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
void dcache_enable(void)
{
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index a2aa93a735..97899a567f 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -79,16 +79,16 @@ SECTIONS
}
#if defined(IMAGE_MAX_SIZE)
-ASSERT(__image_copy_end - __image_copy_start < (IMAGE_MAX_SIZE), \
+ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
-ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
-ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
+#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index 3955bea23a..74f6355229 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -52,11 +52,11 @@ SECTIONS
}
#if defined(IMAGE_MAX_SIZE)
-ASSERT(__image_copy_end - __start < (IMAGE_MAX_SIZE), \
+ASSERT(__image_copy_end - __start <= (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
-ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 62158a9592..5507348981 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -38,6 +38,14 @@
#include <asm/omap_musb.h>
#include <asm/davinci_rtc.h>
+#define AM43XX_EMIF_BASE 0x4C000000
+#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
+#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
+#define AM43XX_SDRAM_TYPE_SHIFT 29
+#define AM43XX_SDRAM_TYPE_DDR3 3
+#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
+#define AM43XX_RDWRLVLFULL_START 0x80000000
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@@ -435,7 +443,7 @@ static void rtc_only(void)
struct prm_device_inst *prm_device =
(struct prm_device_inst *)PRM_DEVICE_INST;
- u32 scratch1;
+ u32 scratch1, sdrc;
void (*resume_func)(void);
scratch1 = readl(&rtc->scratch1);
@@ -473,8 +481,25 @@ static void rtc_only(void)
rtc_only_prcm_init();
sdram_init();
- /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
- writel(0, &prm_device->emif_ctrl);
+ /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
+ /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
+ sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
+
+ sdrc &= AM43XX_SDRAM_TYPE_MASK;
+ sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
+
+ if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
+ writel(AM43XX_RDWRLVLFULL_START,
+ AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ mdelay(1);
+
+am43xx_wait:
+ sdrc = readl(AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ if (sdrc == AM43XX_RDWRLVLFULL_START)
+ goto am43xx_wait;
+ }
resume_func = (void *)readl(&rtc->scratch0);
if (resume_func)
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index be6f4d72cc..3fd1d086ff 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -80,6 +80,11 @@ static void configure_mr(int nr, u32 cs)
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
+#ifdef CONFIG_AM43XX
+ struct prm_device_inst *prm_device =
+ (struct prm_device_inst *)PRM_DEVICE_INST;
+#endif
+
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
@@ -126,6 +131,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+#ifdef CONFIG_AM43XX
+ /*
+ * Disable EMIF_DEVOFF
+ * -> Cold Boot: This is just rewriting the default register value.
+ * -> RTC Resume: Must disable DEVOFF before leveling.
+ */
+ writel(0, &prm_device->emif_ctrl);
+#endif
+
/* Perform hardware leveling for DDR3 */
if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
@@ -138,6 +152,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
/* Enable read leveling */
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
/*
* Enable full read and write leveling. Wait for read and write
* leveling bit to clear RDWRLVLFULL_START bit 31
@@ -256,8 +273,16 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
* Enable hardware leveling on the EMIF. For details about these
* magic values please see the EMIF registers section of the TRM.
*/
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
+ /* PHY_INVERT_CLKOUT = 1 */
+ writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ } else {
+ /* PHY_INVERT_CLKOUT = 0 */
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ }
+
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
@@ -286,8 +311,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+ writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
/*
* Sequence to ensure that the PHY is again in a known state after
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index c6e5f75daf..babb5e9e84 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -13,6 +13,9 @@ config RCAR_GEN3
select ARM64
select PHY
select CMD_CACHE
+ select PINCTRL
+ select PINCONF
+ select PINCTRL_PFC
imply CMD_FS_UUID
imply CMD_GPT
imply CMD_UUID
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e1ea8eb73e..d887f0201f 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
- L310_AUX_CTRL_DATA_PREFETCH_MASK |
- L310_AUX_CTRL_INST_PREFETCH_MASK |
- L310_SHARED_ATT_OVERRIDE_ENABLE);
+ struct udevice *dev;
- /* Enable the L2 cache */
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+ pr_err("cache controller driver NOT found!\n");
}
void v7_outer_cache_disable(void)
generated by cgit (git 2.34.1) at 2025-01-15 01:59:52 +0000