diff options
Diffstat (limited to 'arch/arm')
26 files changed, 3079 insertions, 146 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 77d1b6021b..49d1faef32 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -551,6 +551,7 @@ dtb-$(CONFIG_MX6Q) += \ imx6q-tbs2910.dtb dtb-$(CONFIG_MX6QDL) += \ + imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ @@ -559,6 +560,7 @@ dtb-$(CONFIG_MX6QDL) += \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revb1.dtb \ imx6q-cm-fx6.dtb \ + imx6q-dhcom-pdk2.dtb \ imx6q-icore.dtb \ imx6q-icore-mipi.dtb \ imx6q-icore-rqs.dtb \ @@ -599,8 +601,7 @@ dtb-$(CONFIG_MX6ULL) += \ dtb-$(CONFIG_ARCH_MX6) += \ imx6-apalis.dtb \ - imx6-colibri.dtb \ - imx6q-dhcom-pdk2.dtb + imx6-colibri.dtb dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 715abb413d..0c33eee6d2 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/pads-imx8qxp.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> / { model = "Freescale i.MX8DX"; @@ -30,6 +31,14 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; }; memory@80000000 { @@ -543,6 +552,61 @@ power-domains = <&pd_conn_enet1>; status = "disabled"; }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + /* number of the temp sensor on the chip */ + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + status = "disabled"; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; }; &A35_0 { diff --git a/arch/arm/dts/imx28-pinfunc.h b/arch/arm/dts/imx28-pinfunc.h new file mode 100644 index 0000000000..e11f69ba0f --- /dev/null +++ b/arch/arm/dts/imx28-pinfunc.h @@ -0,0 +1,506 @@ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ +#define __DT_BINDINGS_MX28_PINCTRL_H__ + +#include "mxs-pinfunc.h" + +#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 +#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 +#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 +#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 +#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 +#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 +#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 +#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 +#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 +#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 +#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 +#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 +#define MX28_PAD_LCD_D00__LCD_D0 0x1000 +#define MX28_PAD_LCD_D01__LCD_D1 0x1010 +#define MX28_PAD_LCD_D02__LCD_D2 0x1020 +#define MX28_PAD_LCD_D03__LCD_D3 0x1030 +#define MX28_PAD_LCD_D04__LCD_D4 0x1040 +#define MX28_PAD_LCD_D05__LCD_D5 0x1050 +#define MX28_PAD_LCD_D06__LCD_D6 0x1060 +#define MX28_PAD_LCD_D07__LCD_D7 0x1070 +#define MX28_PAD_LCD_D08__LCD_D8 0x1080 +#define MX28_PAD_LCD_D09__LCD_D9 0x1090 +#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 +#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 +#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 +#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 +#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 +#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 +#define MX28_PAD_LCD_D16__LCD_D16 0x1100 +#define MX28_PAD_LCD_D17__LCD_D17 0x1110 +#define MX28_PAD_LCD_D18__LCD_D18 0x1120 +#define MX28_PAD_LCD_D19__LCD_D19 0x1130 +#define MX28_PAD_LCD_D20__LCD_D20 0x1140 +#define MX28_PAD_LCD_D21__LCD_D21 0x1150 +#define MX28_PAD_LCD_D22__LCD_D22 0x1160 +#define MX28_PAD_LCD_D23__LCD_D23 0x1170 +#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 +#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 +#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 +#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 +#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 +#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 +#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 +#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 +#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 +#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 +#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 +#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 +#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 +#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 +#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 +#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 +#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 +#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 +#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 +#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 +#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 +#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 +#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 +#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 +#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 +#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 +#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 +#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 +#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 +#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 +#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 +#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 +#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 +#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 +#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 +#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 +#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 +#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 +#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 +#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 +#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 +#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 +#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 +#define MX28_PAD_PWM0__PWM_0 0x3100 +#define MX28_PAD_PWM1__PWM_1 0x3110 +#define MX28_PAD_PWM2__PWM_2 0x3120 +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 +#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 +#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 +#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 +#define MX28_PAD_PWM3__PWM_3 0x31c0 +#define MX28_PAD_PWM4__PWM_4 0x31d0 +#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 +#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 +#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 +#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 +#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 +#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 +#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 +#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 +#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 +#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 +#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 +#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 +#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 +#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 +#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 +#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 +#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 +#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 +#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 +#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 +#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 +#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 +#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 +#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 +#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 +#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 +#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 +#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 +#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 +#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 +#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 +#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 +#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 +#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 +#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 +#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 +#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 +#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 +#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 +#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 +#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 +#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 +#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 +#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 +#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 +#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 +#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 +#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 +#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 +#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 +#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 +#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 +#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 +#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 +#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 +#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 +#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 +#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 +#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 +#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 +#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 +#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 +#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 +#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 +#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 +#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 +#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 +#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 +#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 +#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 +#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 +#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 +#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 +#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 +#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 +#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 +#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 +#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 +#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 +#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 +#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 +#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 +#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 +#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 +#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 +#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 +#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 +#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 +#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 +#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 +#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 +#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 +#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 +#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 +#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 +#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 +#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 +#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 +#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 +#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 +#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 +#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 +#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 +#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 +#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 +#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 +#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 +#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 +#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 +#define MX28_PAD_PWM0__I2C1_SCL 0x3101 +#define MX28_PAD_PWM1__I2C1_SDA 0x3111 +#define MX28_PAD_PWM2__USB0_ID 0x3121 +#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 +#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 +#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 +#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 +#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 +#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 +#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 +#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 +#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 +#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 +#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 +#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 +#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 +#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 +#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 +#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 +#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 +#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 +#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 +#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 +#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 +#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 +#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 +#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 +#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 +#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 +#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 +#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 +#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 +#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 +#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 +#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 +#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 +#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 +#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 +#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 +#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 +#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 +#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 +#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 +#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 +#define MX28_PAD_AUART1_RX__PWM_0 0x3042 +#define MX28_PAD_AUART1_TX__PWM_1 0x3052 +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 +#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 +#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 +#define MX28_PAD_PWM0__DUART_RX 0x3102 +#define MX28_PAD_PWM1__DUART_TX 0x3112 +#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 +#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 +#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 +#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 +#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 +#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 +#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 +#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 +#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 +#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 +#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 +#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 +#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 +#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 +#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 +#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 +#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 +#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 +#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 +#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 +#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 +#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 +#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 +#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 +#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 +#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 +#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 +#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 +#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 +#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 +#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 +#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 +#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 +#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 +#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 +#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 +#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 +#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 +#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 +#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 +#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 +#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 +#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 +#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 +#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 +#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 +#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 +#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 +#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 +#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 +#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 +#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 +#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 +#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 +#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 +#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 +#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 +#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 +#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 +#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 +#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 +#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 +#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 +#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 +#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 +#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 +#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 +#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 +#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 +#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 +#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 +#define MX28_PAD_PWM0__GPIO_3_16 0x3103 +#define MX28_PAD_PWM1__GPIO_3_17 0x3113 +#define MX28_PAD_PWM2__GPIO_3_18 0x3123 +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 +#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 +#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 +#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 +#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 +#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 +#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 +#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 +#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 +#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 +#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 + +#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/dts/imx28-u-boot.dtsi b/arch/arm/dts/imx28-u-boot.dtsi new file mode 100644 index 0000000000..d545b402a7 --- /dev/null +++ b/arch/arm/dts/imx28-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ +#include "imx28.dtsi" + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 29>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 29 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 61 28>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 89 31>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 0 120 21>; +}; diff --git a/arch/arm/dts/imx28.dtsi b/arch/arm/dts/imx28.dtsi new file mode 100644 index 0000000000..e14d8ef015 --- /dev/null +++ b/arch/arm/dts/imx28.dtsi @@ -0,0 +1,1330 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2012 Freescale Semiconductor, Inc. + +#include <dt-bindings/gpio/gpio.h> +#include "imx28-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&icoll>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + saif0 = &saif0; + saif1 = &saif1; + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; + spi0 = &ssp1; + spi1 = &ssp2; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + apb@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x80000>; + ranges; + + apbh@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x3c900>; + ranges; + + icoll: interrupt-controller@80000000 { + compatible = "fsl,imx28-icoll", "fsl,icoll"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x80000000 0x2000>; + }; + + hsadc: hsadc@80002000 { + reg = <0x80002000 0x2000>; + interrupts = <13>; + dmas = <&dma_apbh 12>; + dma-names = "rx"; + status = "disabled"; + }; + + dma_apbh: dma-apbh@80004000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x80004000 0x2000>; + interrupts = <82 83 84 85 + 88 88 88 88 + 88 88 88 88 + 87 86 0 0>; + interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", + "gpmi0", "gmpi1", "gpmi2", "gmpi3", + "gpmi4", "gmpi5", "gpmi6", "gmpi7", + "hsadc", "lcdif", "empty", "empty"; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks 25>; + }; + + perfmon: perfmon@80006000 { + reg = <0x80006000 0x800>; + interrupts = <27>; + status = "disabled"; + }; + + gpmi: gpmi-nand@8000c000 { + compatible = "fsl,imx28-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <41>; + interrupt-names = "bch"; + clocks = <&clks 50>; + clock-names = "gpmi_io"; + dmas = <&dma_apbh 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp0: spi@80010000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010000 0x2000>; + interrupts = <96>; + clocks = <&clks 46>; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp1: spi@80012000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80012000 0x2000>; + interrupts = <97>; + clocks = <&clks 47>; + dmas = <&dma_apbh 1>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp2: spi@80014000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80014000 0x2000>; + interrupts = <98>; + clocks = <&clks 48>; + dmas = <&dma_apbh 2>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + ssp3: spi@80016000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80016000 0x2000>; + interrupts = <99>; + clocks = <&clks 49>; + dmas = <&dma_apbh 3>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pinctrl: pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-pinctrl", "simple-bus"; + reg = <0x80018000 0x2000>; + + gpio0: gpio@0 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@3 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@4 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + duart_pins_a: duart@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__DUART_RX + MX28_PAD_PWM1__DUART_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + duart_pins_b: duart@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + duart_4pins_a: duart-4pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX + MX28_PAD_AUART0_RX__DUART_CTS + MX28_PAD_AUART0_TX__DUART_RTS + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPMI_D0 + MX28_PAD_GPMI_D01__GPMI_D1 + MX28_PAD_GPMI_D02__GPMI_D2 + MX28_PAD_GPMI_D03__GPMI_D3 + MX28_PAD_GPMI_D04__GPMI_D4 + MX28_PAD_GPMI_D05__GPMI_D5 + MX28_PAD_GPMI_D06__GPMI_D6 + MX28_PAD_GPMI_D07__GPMI_D7 + MX28_PAD_GPMI_CE0N__GPMI_CE0N + MX28_PAD_GPMI_RDY0__GPMI_READY0 + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_ALE__GPMI_ALE + MX28_PAD_GPMI_CLE__GPMI_CLE + MX28_PAD_GPMI_RESETN__GPMI_RESETN + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + gpmi_status_cfg: gpmi-status-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_RESETN__GPMI_RESETN + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX + MX28_PAD_AUART0_CTS__AUART0_CTS + MX28_PAD_AUART0_RTS__AUART0_RTS + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart1_pins_a: auart1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + MX28_PAD_AUART1_CTS__AUART1_CTS + MX28_PAD_AUART1_RTS__AUART1_RTS + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart2_2pins_a: auart2-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__AUART2_RX + MX28_PAD_SSP2_MOSI__AUART2_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart2_2pins_b: auart2-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart2_pins_a: auart2-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX + MX28_PAD_AUART2_CTS__AUART2_CTS + MX28_PAD_AUART2_RTS__AUART2_RTS + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart3_pins_a: auart3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX + MX28_PAD_AUART3_CTS__AUART3_CTS + MX28_PAD_AUART3_RTS__AUART3_RTS + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart3_2pins_a: auart3-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_MISO__AUART3_RX + MX28_PAD_SSP2_SS0__AUART3_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart3_2pins_b: auart3-2pins@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart4_2pins_a: auart4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_SCK__AUART4_TX + MX28_PAD_SSP3_MOSI__AUART4_RX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + auart4_2pins_b: auart4@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_CTS__AUART4_RX + MX28_PAD_AUART0_RTS__AUART4_TX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mac0_pins_a: mac0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mac0_pins_b: mac0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_RXD2__ENET0_RXD2 + MX28_PAD_ENET0_RXD3__ENET0_RXD3 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET0_TXD2__ENET0_TXD2 + MX28_PAD_ENET0_TXD3__ENET0_TXD3 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + MX28_PAD_ENET0_COL__ENET0_COL + MX28_PAD_ENET0_CRS__ENET0_CRS + MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK + MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mac1_pins_a: mac1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_CRS__ENET1_RX_EN + MX28_PAD_ENET0_RXD2__ENET1_RXD0 + MX28_PAD_ENET0_RXD3__ENET1_RXD1 + MX28_PAD_ENET0_COL__ENET1_TX_EN + MX28_PAD_ENET0_TXD2__ENET1_TXD0 + MX28_PAD_ENET0_TXD3__ENET1_TXD1 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc0_8bit_pins_a: mmc0-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_DATA4__SSP0_D4 + MX28_PAD_SSP0_DATA5__SSP0_D5 + MX28_PAD_SSP0_DATA6__SSP0_D6 + MX28_PAD_SSP0_DATA7__SSP0_D7 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc0_cd_cfg: mmc0-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + >; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc0_sck_cfg: mmc0-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc1_cd_cfg: mmc1-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + >; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc1_sck_cfg: mmc1-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + + mmc2_4bit_pins_a: mmc2-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP1_SCK__SSP2_D1 + MX28_PAD_SSP1_CMD__SSP2_D2 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc2_4bit_pins_b: mmc2-4bit@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__SSP2_D3 + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc2_cd_cfg: mmc2-cd-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + >; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc2_sck_cfg_a: mmc2-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc2_sck_cfg_b: mmc2-sck-cfg@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + i2c0_pins_a: i2c0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__I2C0_SCL + MX28_PAD_I2C0_SDA__I2C0_SDA + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RX__I2C0_SCL + MX28_PAD_AUART0_TX__I2C0_SDA + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__I2C1_SCL + MX28_PAD_PWM1__I2C1_SDA + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + i2c1_pins_b: i2c1@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_CTS__I2C1_SCL + MX28_PAD_AUART2_RTS__I2C1_SDA + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + saif0_pins_a: saif0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + saif0_pins_b: saif0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + saif1_pins_a: saif1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + pwm0_pins_a: pwm0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM0__PWM_0 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__PWM_2 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + pwm3_pins_a: pwm3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__PWM_3 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + pwm3_pins_b: pwm3@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__PWM_3 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM4__PWM_4 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + MX28_PAD_LCD_D18__LCD_D18 + MX28_PAD_LCD_D19__LCD_D19 + MX28_PAD_LCD_D20__LCD_D20 + MX28_PAD_LCD_D21__LCD_D21 + MX28_PAD_LCD_D22__LCD_D22 + MX28_PAD_LCD_D23__LCD_D23 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_18bit_pins_a: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_16bit_pins_a: lcdif-16bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_sync_pins_a: lcdif-sync@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + can0_pins_a: can0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY2__CAN0_TX + MX28_PAD_GPMI_RDY3__CAN0_RX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + can1_pins_a: can1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE2N__CAN1_TX + MX28_PAD_GPMI_CE3N__CAN1_RX + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__SSP2_D3 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + spi3_pins_a: spi3@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + spi3_pins_b: spi3@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + usb0_pins_a: usb0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS2__USB0_OVERCURRENT + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + usb0_pins_b: usb0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + usb1_pins_a: usb1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS1__USB1_OVERCURRENT + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + usb0_id_pins_a: usb0id@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RTS__USB0_ID + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + usb0_id_pins_b: usb0id1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM2__USB0_ID + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + }; + + digctl: digctl@8001c000 { + compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; + reg = <0x8001c000 0x2000>; + interrupts = <89>; + status = "disabled"; + }; + + etm: etm@80022000 { + reg = <0x80022000 0x2000>; + status = "disabled"; + }; + + dma_apbx: dma-apbx@80024000 { + compatible = "fsl,imx28-dma-apbx"; + reg = <0x80024000 0x2000>; + interrupts = <78 79 66 0 + 80 81 68 69 + 70 71 72 73 + 74 75 76 77>; + interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", + "saif0", "saif1", "i2c0", "i2c1", + "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", + "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks 26>; + }; + + dcp: dcp@80028000 { + compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; + reg = <0x80028000 0x2000>; + interrupts = <52 53 54>; + status = "okay"; + }; + + pxp: pxp@8002a000 { + reg = <0x8002a000 0x2000>; + interrupts = <39>; + status = "disabled"; + }; + + ocotp: ocotp@8002c000 { + compatible = "fsl,imx28-ocotp", "fsl,ocotp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8002c000 0x2000>; + clocks = <&clks 25>; + }; + + axi-ahb@8002e000 { + reg = <0x8002e000 0x2000>; + status = "disabled"; + }; + + lcdif: lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; + reg = <0x80030000 0x2000>; + interrupts = <38>; + clocks = <&clks 55>; + dmas = <&dma_apbh 13>; + dma-names = "rx"; + status = "disabled"; + }; + + can0: can@80032000 { + compatible = "fsl,imx28-flexcan"; + reg = <0x80032000 0x2000>; + interrupts = <8>; + clocks = <&clks 58>, <&clks 58>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@80034000 { + compatible = "fsl,imx28-flexcan"; + reg = <0x80034000 0x2000>; + interrupts = <9>; + clocks = <&clks 59>, <&clks 59>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + simdbg: simdbg@8003c000 { + reg = <0x8003c000 0x200>; + status = "disabled"; + }; + + simgpmisel: simgpmisel@8003c200 { + reg = <0x8003c200 0x100>; + status = "disabled"; + }; + + simsspsel: simsspsel@8003c300 { + reg = <0x8003c300 0x100>; + status = "disabled"; + }; + + simmemsel: simmemsel@8003c400 { + reg = <0x8003c400 0x100>; + status = "disabled"; + }; + + gpiomon: gpiomon@8003c500 { + reg = <0x8003c500 0x100>; + status = "disabled"; + }; + + simenet: simenet@8003c700 { + reg = <0x8003c700 0x100>; + status = "disabled"; + }; + + armjtag: armjtag@8003c800 { + reg = <0x8003c800 0x100>; + status = "disabled"; + }; + }; + + apbx@80040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80040000 0x40000>; + ranges; + + clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; + + saif0: saif@80042000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx28-saif"; + reg = <0x80042000 0x2000>; + interrupts = <59>; + #clock-cells = <0>; + clocks = <&clks 53>; + dmas = <&dma_apbx 4>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + power: power@80044000 { + reg = <0x80044000 0x2000>; + status = "disabled"; + }; + + saif1: saif@80046000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx28-saif"; + reg = <0x80046000 0x2000>; + interrupts = <58>; + clocks = <&clks 54>; + dmas = <&dma_apbx 5>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + lradc: lradc@80050000 { + compatible = "fsl,imx28-lradc"; + reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; + status = "disabled"; + clocks = <&clks 41>; + #io-channel-cells = <1>; + }; + + spdif: spdif@80054000 { + reg = <0x80054000 0x2000>; + interrupts = <45>; + dmas = <&dma_apbx 2>; + dma-names = "tx"; + status = "disabled"; + }; + + mxs_rtc: rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; + reg = <0x80056000 0x2000>; + interrupts = <29>; + }; + + i2c0: i2c@80058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x80058000 0x2000>; + interrupts = <111>; + clock-frequency = <100000>; + dmas = <&dma_apbx 6>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + i2c1: i2c@8005a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x8005a000 0x2000>; + interrupts = <110>; + clock-frequency = <100000>; + dmas = <&dma_apbx 7>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pwm: pwm@80064000 { + compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; + reg = <0x80064000 0x2000>; + clocks = <&clks 44>; + #pwm-cells = <2>; + fsl,pwm-number = <8>; + status = "disabled"; + }; + + timer: timrot@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; + reg = <0x80068000 0x2000>; + interrupts = <48 49 50 51>; + clocks = <&clks 26>; + }; + + auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart1: serial@8006c000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <113>; + dmas = <&dma_apbx 10>, <&dma_apbx 11>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart2: serial@8006e000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006e000 0x2000>; + interrupts = <114>; + dmas = <&dma_apbx 12>, <&dma_apbx 13>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart3: serial@80070000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80070000 0x2000>; + interrupts = <115>; + dmas = <&dma_apbx 14>, <&dma_apbx 15>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + auart4: serial@80072000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80072000 0x2000>; + interrupts = <116>; + dmas = <&dma_apbx 0>, <&dma_apbx 1>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + status = "disabled"; + }; + + duart: serial@80074000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80074000 0x1000>; + interrupts = <47>; + clocks = <&clks 45>, <&clks 26>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; + }; + + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007c000 0x2000>; + clocks = <&clks 62>; + status = "disabled"; + }; + + usbphy1: usbphy@8007e000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007e000 0x2000>; + clocks = <&clks 63>; + status = "disabled"; + }; + }; + }; + + ahb@80080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80080000 0x80000>; + ranges; + + usb0: usb@80080000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80080000 0x10000>; + interrupts = <93>; + clocks = <&clks 60>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usb1: usb@80090000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80090000 0x10000>; + interrupts = <92>; + clocks = <&clks 61>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + status = "disabled"; + }; + + dflpt: dflpt@800c0000 { + reg = <0x800c0000 0x10000>; + status = "disabled"; + }; + + mac0: ethernet@800f0000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f0000 0x4000>; + interrupts = <101>; + clocks = <&clks 57>, <&clks 57>, <&clks 64>; + clock-names = "ipg", "ahb", "enet_out"; + status = "disabled"; + }; + + mac1: ethernet@800f4000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f4000 0x4000>; + interrupts = <102>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; + status = "disabled"; + }; + + etn_switch: switch@800f8000 { + reg = <0x800f8000 0x8000>; + status = "disabled"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&lradc 8>; + }; +}; diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi index 329fa3b5e2..bc4b3483a6 100644 --- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -11,6 +11,11 @@ u-boot,dm-pre-reloc; }; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; }; &gpio1 { diff --git a/arch/arm/dts/imx6dl-dhcom-pdk2.dts b/arch/arm/dts/imx6dl-dhcom-pdk2.dts new file mode 100644 index 0000000000..a0b51bcf38 --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-pdk2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2019 DH electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-pdk2.dtsi" + +/ { + model = "Freescale i.MX6 Duallite/Solo DHCOM Premium Developer Kit (2)"; + compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-dhcom-pdk2.dts b/arch/arm/dts/imx6q-dhcom-pdk2.dts index 9c61e3be2d..5bab2db656 100644 --- a/arch/arm/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/dts/imx6q-dhcom-pdk2.dts @@ -1,151 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0+) /* - * Copyright (C) 2015 DH electronics GmbH + * Copyright (C) 2015-2019 DH electronics GmbH * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ /dts-v1/; -#include "imx6q-dhcom-som.dtsi" +#include "imx6q.dtsi" +#include "imx6qdl-dhcom-pdk2.dtsi" / { - model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)"; - compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q"; - - chosen { - stdout-path = &uart1; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_ext>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>; - - pinctrl_hog: hog-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0 - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0 - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0 - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0 - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0 - >; - }; - - pinctrl_audmux_ext: audmux-ext-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_enet_1G: enet-1G-grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 - >; - }; - - pinctrl_pcie: pcie-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; + model = "Freescale i.MX6 Quad/Dual DHCOM Premium Developer Kit (2)"; + compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom", "fsl,imx6q"; }; &sata { status = "okay"; }; -&usdhc3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi new file mode 100644 index 0000000000..b942218b7a --- /dev/null +++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/* + * The minimal augmentation DTS U-Boot file to allow UART5 + * configuration in the pre-relocation stage of U-Boot + * proper. + * + * As the same UART is already configured in SPL, we don't need + * setup pinmux for it again. + */ + +/ { + aliases { + mmc0 = &usdhc4; + }; + + soc { + u-boot,dm-pre-reloc; + + aips-bus@2100000 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &uart5; + }; +}; + +&i2c3 { + at24@50 { + u-boot,i2c-offset-len = <2>; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6q-display5.dts b/arch/arm/dts/imx6q-display5.dts index 50347ff26b..4e2aa363ed 100644 --- a/arch/arm/dts/imx6q-display5.dts +++ b/arch/arm/dts/imx6q-display5.dts @@ -10,9 +10,361 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "imx6q.dtsi" / { model = "Liebherr (LWN) display5 i.MX6 Quad Board"; compatible = "lwn,display5", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; + status = "okay"; + + s25fl256s: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partition@0 { + label = "SPL (spi)"; + reg = <0x0 0x20000>; + read-only; + }; + partition@1 { + label = "u-boot (spi)"; + reg = <0x20000 0x100000>; + read-only; + }; + partition@2 { + label = "uboot-env (spi)"; + reg = <0x120000 0x10000>; + }; + partition@3 { + label = "uboot-envr (spi)"; + reg = <0x130000 0x10000>; + }; + partition@4 { + label = "linux-recovery (spi)"; + reg = <0x140000 0x800000>; + }; + partition@5 { + label = "swupdate-fitImg (spi)"; + reg = <0x940000 0x400000>; + }; + partition@6 { + label = "swupdate-initramfs (spi)"; + reg = <0xD40000 0x800000>; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðernet_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { + compatible = "marvell,88E1510"; + device_type = "ethernet-phy"; + /* Set LED0 control: */ + /* On - Link, Blink - Activity, Off - No Link */ + marvell,reg-init = <3 0x10 0 0x1011>; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: tfa9879@6c { + #sound-dai-cells = <0>; + compatible = "nxp,tfa9879"; + reg = <0x6C>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + at24@50 { + compatible = "atmel,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_ecspi2_flwp: ecspi2flwpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3_cs: ecspi3csgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 + >; + }; + + pinctrl_ecspi3_flwp: ecspi3flwpgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 + >; + }; }; diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi new file mode 100644 index 0000000000..af4719aaeb --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2015-2019 DH electronics GmbH + * Copyright (C) 2018 Marek Vasut <marex@denx.de> + */ + +#include "imx6qdl-dhcom.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_ext>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>; + + pinctrl_hog: hog-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0 + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0 + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0 + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0 + >; + }; + + pinctrl_audmux_ext: audmux-ext-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_enet_1G: enet-1G-grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 + >; + }; + + pinctrl_pcie: pcie-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-dhcom-som.dtsi b/arch/arm/dts/imx6qdl-dhcom.dtsi index 524cd287c6..1141b6a562 100644 --- a/arch/arm/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom.dtsi @@ -1,10 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+) /* - * Copyright (C) 2015 DH electronics GmbH + * Copyright (C) 2015-2019 DH electronics GmbH * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ -#include "imx6q.dtsi" #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/imx6qdl-clock.h> diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi index 9f1fe683db..7cd8be24c8 100644 --- a/arch/arm/dts/imx7d-pico.dtsi +++ b/arch/arm/dts/imx7d-pico.dtsi @@ -10,6 +10,7 @@ / { aliases { mmc0 = &usdhc3; + usb0 = &usbotg1; }; /* Will be filled by the bootloader */ @@ -296,6 +297,7 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "peripheral"; status = "okay"; }; diff --git a/arch/arm/dts/mxs-pinfunc.h b/arch/arm/dts/mxs-pinfunc.h new file mode 100644 index 0000000000..c6da987b20 --- /dev/null +++ b/arch/arm/dts/mxs-pinfunc.h @@ -0,0 +1,31 @@ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ +#define __DT_BINDINGS_MXS_PINCTRL_H__ + +/* fsl,drive-strength property */ +#define MXS_DRIVE_4mA 0 +#define MXS_DRIVE_8mA 1 +#define MXS_DRIVE_12mA 2 +#define MXS_DRIVE_16mA 3 + +/* fsl,voltage property */ +#define MXS_VOLTAGE_LOW 0 +#define MXS_VOLTAGE_HIGH 1 + +/* fsl,pull-up property */ +#define MXS_PULL_DISABLE 0 +#define MXS_PULL_ENABLE 1 + +#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 97377697f0..901b90d705 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -72,6 +72,8 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); +int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + s16 *celsius, s8 *tenths); /* RM API */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h index 5d17b553d7..3629eb68d7 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -26,5 +26,6 @@ #define SC_MISC_REL_CONTAINER 2U /* Release container */ typedef u8 sc_misc_boot_status_t; +typedef u8 sc_misc_temp_t; #endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index 73ffaba7d5..b8d2a0b8f0 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include <asm/arch/sci/sci.h> #include <asm/mach-imx/sys_proto.h> #include <linux/types.h> @@ -15,5 +16,7 @@ struct pass_over_info_t { u32 g_ap_mu; }; +void build_info(void); enum boot_device get_boot_device(void); int print_bootinfo(void); +int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h new file mode 100644 index 0000000000..033659a038 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX_NAND_BCB_H_ +#define _IMX_NAND_BCB_H_ + +#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */ +#define FCB_VERSION_1 0x01000000 + +#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */ +#define DBBT_VERSION_1 0x01000000 + +struct dbbt_block { + u32 checksum; /* reserved on i.MX6 */ + u32 fingerprint; + u32 version; + u32 numberbb; /* reserved on i.MX6 */ + u32 dbbtpages; +}; + +struct fcb_block { + u32 checksum; /* First fingerprint in first byte */ + u32 fingerprint; /* 2nd fingerprint at byte 4 */ + u32 version; /* 3rd fingerprint at byte 8 */ + u8 datasetup; + u8 datahold; + u8 addr_setup; + u8 dsample_time; + + /* These are for application use only and not for ROM. */ + u8 nandtiming; + u8 rea; + u8 rloh; + u8 rhoh; + u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */ + u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */ + u32 sectors; /* Number of 2K sections per block */ + u32 nr_nand; /* Total Number of NANDs - not used by ROM */ + u32 nr_die; /* Number of separate chips in this NAND */ + u32 celltype; /* MLC or SLC */ + u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */ + u32 ecc_nr; /* Number of bytes for Block0 - BCH */ + + /* Block size in bytes for all blocks other than Block0 - BCH */ + u32 ecc_size; + u32 ecc_level; /* Ecc level for Block 0 - BCH */ + u32 meta_size; /* Metadata size - BCH */ + /* Number of blocks per page for ROM use - BCH */ + u32 nr_blocks; + u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */ + u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */ + /* Block size in bytes for all blocks other than Block0 - BCH */ + u32 ecc_size_sdk; + u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */ + /* Number of blocks per page for SDK use - BCH */ + u32 nr_blocks_sdk; + u32 meta_size_sdk; /* Metadata size - BCH */ + u32 erase_th; /* To set into BCH_MODE register */ + + /* + * 0: normal boot + * 1: to load patch starting next to FCB + */ + u32 bootpatch; + u32 patch_size; /* Size of patch in sectors */ + u32 fw1_start; /* Firmware image starts on this sector */ + u32 fw2_start; /* Secondary FW Image starting Sector */ + u32 fw1_pages; /* Number of sectors in firmware image */ + u32 fw2_pages; /* Number of sector in secondary FW image */ + u32 dbbt_start; /* Page address where dbbt search area begins */ + + /* + * Byte in page data that have manufacturer marked bad block marker, + * this will be swapped with metadata[0] to complete page data. + */ + u32 bb_byte; + + /* + * For BCH ECC sizes other than 8 and 16 the bad block marker does not + * start at 0th bit of bb_byte. This field is used to get to + * the start bit of bad block marker byte with in bb_byte + */ + u32 bb_start_bit; + + /* + * FCB value that gives byte offset for + * bad block marker on physical NAND page + */ + u32 phy_offset; + u32 bchtype; + + u32 readlatency; + u32 predelay; + u32 cedelay; + u32 postdelay; + u32 cmdaddpause; + u32 datapause; + u32 tmspeed; + u32 busytimeout; + + /* the flag to enable (1)/disable(0) bi swap */ + u32 disbbm; + + /* The swap position of main area in spare area */ + u32 spare_offset; +}; + +#endif /* _IMX_NAND_BCB_H_ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b6fd1595f0..aeb5493488 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -71,6 +71,17 @@ config CMD_HDMIDETECT This enables the 'hdmidet' command which detects if an HDMI monitor is connected. +config CMD_NANDBCB + bool "i.MX6 NAND Boot Control Block(BCB) command" + depends on NAND && CMD_MTDPARTS + default y if ARCH_MX6 && NAND_MXS + help + Unlike normal 'nand write/erase' commands, this command update + Boot Control Block(BCB) for i.MX6 platform NAND IP's. + + This is similar to kobs-ng, which is used in Linux as separate + rootfs package. + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 898478fc4a..08ee52edbf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -59,6 +59,7 @@ ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o +obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif PLUGIN = board/$(BOARDDIR)/plugin diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c new file mode 100644 index 0000000000..065b814b2e --- /dev/null +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -0,0 +1,369 @@ +/* + * i.MX6 nand boot control block(bcb). + * + * Based on the common/imx-bbu-nand-fcb.c from barebox and imx kobs-ng + * + * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> + * Copyright (C) 2016 Sergey Kubushyn <ksi@koi8.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> + +#include <asm/io.h> +#include <jffs2/jffs2.h> +#include <linux/mtd/mtd.h> + +#include <asm/mach-imx/imx-nandbcb.h> +#include <asm/mach-imx/imximage.cfg> +#include <mxs_nand.h> +#include <linux/mtd/mtd.h> +#include <nand.h> + +#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) +#define GETBIT(v, n) (((v) >> (n)) & 0x1) + +static u8 calculate_parity_13_8(u8 d) +{ + u8 p = 0; + + p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2)) << 0; + p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ + GETBIT(d, 1)) << 1; + p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ + GETBIT(d, 0)) << 2; + p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0)) << 3; + p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ + GETBIT(d, 1) ^ GETBIT(d, 0)) << 4; + + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + u8 *src = _src; + u8 *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static u32 calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) + chksum += bp[i]; + + return ~chksum; +} + +static void fill_fcb(struct fcb_block *fcb, struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + + fcb->fingerprint = FCB_FINGERPRINT; + fcb->version = FCB_VERSION_1; + fcb->pagesize = mtd->writesize; + fcb->oob_pagesize = mtd->writesize + mtd->oobsize; + fcb->sectors = mtd->erasesize / mtd->writesize; + + /* Divide ECC strength by two and save the value into FCB structure. */ + fcb->ecc_level = nand_info->bch_geometry.ecc_strength >> 1; + + fcb->ecc_type = fcb->ecc_level; + + /* Also hardcoded in kobs-ng */ + fcb->ecc_nr = 0x00000200; + fcb->ecc_size = 0x00000200; + fcb->datasetup = 80; + fcb->datahold = 60; + fcb->addr_setup = 25; + fcb->dsample_time = 6; + fcb->meta_size = 10; + + /* DBBT search area starts at second page on first block */ + fcb->dbbt_start = 1; + + fcb->bb_byte = nand_info->bch_geometry.block_mark_byte_offset; + fcb->bb_start_bit = nand_info->bch_geometry.block_mark_bit_offset; + + fcb->phy_offset = mtd->writesize; + + fcb->nr_blocks = mtd->writesize / fcb->ecc_nr - 1; + + fcb->checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4); +} + +static int dbbt_fill_data(struct mtd_info *mtd, void *buf, int num_blocks) +{ + int n, n_bad_blocks = 0; + u32 *bb = buf + 0x8; + u32 *n_bad_blocksp = buf + 0x4; + + for (n = 0; n < num_blocks; n++) { + loff_t offset = n * mtd->erasesize; + if (mtd_block_isbad(mtd, offset)) { + n_bad_blocks++; + *bb = n; + bb++; + } + } + + *n_bad_blocksp = n_bad_blocks; + + return n_bad_blocks; +} + +static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size, + size_t maxsize, const u_char *buf) +{ + nand_erase_options_t opts; + struct fcb_block *fcb; + struct dbbt_block *dbbt; + loff_t fw1_off; + void *fwbuf, *fcb_raw_page, *dbbt_page, *dbbt_data_page; + int nr_blks, nr_blks_fcb, fw1_blk; + size_t fwsize, dummy; + int i, ret; + + /* erase */ + memset(&opts, 0, sizeof(opts)); + opts.offset = off; + opts.length = maxsize - 1; + ret = nand_erase_opts(mtd, &opts); + if (ret) { + printf("%s: erase failed (ret = %d)\n", __func__, ret); + return ret; + } + + /* + * Reference documentation from i.MX6DQRM section 8.5.2.2 + * + * Nand Boot Control Block(BCB) contains two data structures, + * - Firmware Configuration Block(FCB) + * - Discovered Bad Block Table(DBBT) + * + * FCB contains, + * - nand timings + * - DBBT search page address, + * - start page address of primary firmware + * - start page address of secondary firmware + * + * setup fcb: + * - number of blocks = mtd partition size / mtd erasesize + * - two firmware blocks, primary and secondary + * - first 4 block for FCB/DBBT + * - rest split in half for primary and secondary firmware + * - same firmware will write two times + */ + nr_blks_fcb = 2; + nr_blks = maxsize / mtd->erasesize; + fw1_blk = nr_blks_fcb; + + /* write fw */ + fwsize = ALIGN(size + FLASH_OFFSET_STANDARD + mtd->writesize, + mtd->writesize); + fwbuf = kzalloc(fwsize, GFP_KERNEL); + if (!fwbuf) { + debug("failed to allocate fwbuf\n"); + ret = -ENOMEM; + goto err; + } + + memcpy(fwbuf + FLASH_OFFSET_STANDARD, buf, size); + fw1_off = fw1_blk * mtd->erasesize; + ret = nand_write_skip_bad(mtd, fw1_off, &fwsize, NULL, maxsize, + (u_char *)fwbuf, WITH_WR_VERIFY); + printf("NAND fw write: 0x%llx offset, 0x%x bytes written: %s\n", + fw1_off, fwsize, ret ? "ERROR" : "OK"); + if (ret) + goto fwbuf_err; + + /* fill fcb */ + fcb = kzalloc(sizeof(*fcb), GFP_KERNEL); + if (!fcb) { + debug("failed to allocate fcb\n"); + ret = -ENOMEM; + goto fwbuf_err; + } + + fcb->fw1_start = (fw1_blk * mtd->erasesize) / mtd->writesize; + fcb->fw1_pages = size / mtd->writesize + 1; + fill_fcb(fcb, mtd); + + /* fill dbbt */ + dbbt_page = kzalloc(mtd->writesize, GFP_KERNEL); + if (!dbbt_page) { + debug("failed to allocate dbbt_page\n"); + ret = -ENOMEM; + goto fcb_err; + } + + dbbt_data_page = kzalloc(mtd->writesize, GFP_KERNEL); + if (!dbbt_data_page) { + debug("failed to allocate dbbt_data_page\n"); + ret = -ENOMEM; + goto dbbt_page_err; + } + + dbbt = dbbt_page; + dbbt->checksum = 0; + dbbt->fingerprint = DBBT_FINGERPRINT2; + dbbt->version = DBBT_VERSION_1; + ret = dbbt_fill_data(mtd, dbbt_data_page, nr_blks); + if (ret < 0) + goto dbbt_data_page_err; + else if (ret > 0) + dbbt->dbbtpages = 1; + + /* write fcb/dbbt */ + fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); + if (!fcb_raw_page) { + debug("failed to allocate fcb_raw_page\n"); + ret = -ENOMEM; + goto dbbt_data_page_err; + } + + memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block)); + encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512); + /* + * Set the first and second byte of OOB data to 0xFF, not 0x00. These + * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since + * the FCB is mostly written to the first page in a block, a scan for + * factory bad blocks will detect these blocks as bad, e.g. when + * function nand_scan_bbt() is executed to build a new bad block table. + */ + memset(fcb_raw_page + mtd->writesize, 0xFF, 2); + + for (i = 0; i < nr_blks_fcb; i++) { + if (mtd_block_isbad(mtd, off)) { + printf("Block %d is bad, skipped\n", i); + continue; + } + + /* raw write */ + mtd_oob_ops_t ops = { + .datbuf = (u8 *)fcb_raw_page, + .oobbuf = ((u8 *)fcb_raw_page) + mtd->writesize, + .len = mtd->writesize, + .ooblen = mtd->oobsize, + .mode = MTD_OPS_RAW + }; + + ret = mtd_write_oob(mtd, mtd->erasesize * i, &ops); + if (ret) + goto fcb_raw_page_err; + debug("NAND fcb write: 0x%x offset, 0x%x bytes written: %s\n", + mtd->erasesize * i, ops.len, ret ? "ERROR" : "OK"); + + ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize, + mtd->writesize, &dummy, dbbt_page); + if (ret) + goto fcb_raw_page_err; + debug("NAND dbbt write: 0x%x offset, 0x%x bytes written: %s\n", + mtd->erasesize * i + mtd->writesize, dummy, + ret ? "ERROR" : "OK"); + + /* dbbtpages == 0 if no bad blocks */ + if (dbbt->dbbtpages > 0) { + loff_t to = (mtd->erasesize * i + mtd->writesize * 5); + + ret = mtd_write(mtd, to, mtd->writesize, &dummy, + dbbt_data_page); + if (ret) + goto fcb_raw_page_err; + } + } + +fcb_raw_page_err: + kfree(fcb_raw_page); +dbbt_data_page_err: + kfree(dbbt_data_page); +dbbt_page_err: + kfree(dbbt_page); +fcb_err: + kfree(fcb); +fwbuf_err: + kfree(fwbuf); +err: + return ret; +} + +static int do_nandbcb_update(int argc, char * const argv[]) +{ + struct mtd_info *mtd; + loff_t addr, offset, size, maxsize; + char *endp; + u_char *buf; + int dev; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + dev = nand_curr_device; + if (dev < 0) { + printf("failed to get nand_curr_device, run nand device"); + return CMD_RET_FAILURE; + } + + addr = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return CMD_RET_FAILURE; + + mtd = get_nand_dev_by_index(dev); + if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &offset, &size, + &maxsize, MTD_DEV_TYPE_NAND, mtd->size)) + return CMD_RET_FAILURE; + + buf = map_physmem(addr, size, MAP_WRBACK); + if (!buf) { + puts("failed to map physical memory\n"); + return CMD_RET_FAILURE; + } + + ret = nandbcb_update(mtd, offset, size, maxsize, buf); + + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} + +static int do_nandbcb(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *cmd; + int ret = 0; + + if (argc < 5) + goto usage; + + cmd = argv[1]; + --argc; + ++argv; + + if (strcmp(cmd, "update") == 0) { + ret = do_nandbcb_update(argc, argv); + goto done; + } + +done: + if (ret != -1) + return ret; +usage: + return CMD_RET_USAGE; +} + +static char nandbcb_help_text[] = + "update addr off|partition len - update 'len' bytes starting at\n" + " 'off|part' to memory address 'addr', skipping bad blocks"; + +U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb, + "i.MX6 Nand BCB", + nandbcb_help_text +); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 3a8cf30c06..6e9a175210 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -289,10 +289,12 @@ void arch_preboot_os(void) imx_pcie_remove(); #endif #if defined(CONFIG_SATA) - sata_remove(0); + if (!is_mx6sdl()) { + sata_remove(0); #if defined(CONFIG_MX6) - disable_sata_clock(); + disable_sata_clock(); #endif + } #endif #if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 31ad169ccf..92b5c56acb 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o +obj-y += cpu.o iomux.o misc.o diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c new file mode 100644 index 0000000000..fe73e29eee --- /dev/null +++ b/arch/arm/mach-imx/imx8/misc.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <asm/arch/sci/sci.h> + +int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) +{ + sc_pm_clock_rate_t rate = clk_rate; + int ret; + + /* Power up UARTn */ + ret = sc_pm_set_resource_power_mode(-1, uart_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + /* Set UARTn clock root to 'rate' MHz */ + ret = sc_pm_set_clock_rate(-1, uart_rsrc, SC_PM_CLK_PER, &rate); + if (ret) + return ret; + + /* Enable UARTn clock root */ + ret = sc_pm_clock_enable(-1, uart_rsrc, SC_PM_CLK_PER, true, false); + if (ret) + return ret; + + return 0; +} + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 if build info not supported */ + } + printf("Build: SCFW %x\n", sc_commit); +} diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e80f1d484b..4084ab7672 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -95,6 +95,11 @@ u32 get_cpu_rev(void) type = MXC_CPU_MX6DP; } reg &= 0xff; /* mx6 silicon revision */ + + /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/ + if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5)) + reg = 0x3; + return (type << 12) | (reg + (0x10 * (major + 1))); } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 9f1e0f6a72..1f230aca33 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -24,6 +24,7 @@ u32 spl_boot_device(void) { unsigned int bmode = readl(&src_base->sbmr2); u32 reg = imx6_src_get_boot_mode(); + u32 mmc_index = ((reg >> 11) & 0x03); /* * Check for BMODE if serial downloader is enabled @@ -84,11 +85,12 @@ u32 spl_boot_device(void) /* SD/eSD: 8.5.3, Table 8-15 */ case IMX6_BMODE_SD: case IMX6_BMODE_ESD: - return BOOT_DEVICE_MMC1; - /* MMC/eMMC: 8.5.3 */ case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: - return BOOT_DEVICE_MMC1; + if (mmc_index == 1) + return BOOT_DEVICE_MMC2; + else + return BOOT_DEVICE_MMC1; /* NAND Flash: 8.5.2, Table 8-10 */ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: return BOOT_DEVICE_NAND; |