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-rw-r--r--arch/arm/cpu/arm720t/start.S6
-rw-r--r--arch/arm/dts/rk3288-veyron-jerry.dts2
-rw-r--r--arch/arm/dts/tegra124-nyan-big-u-boot.dtsi9
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3288.h74
-rw-r--r--arch/arm/include/asm/arch-tegra/clock.h3
-rw-r--r--arch/arm/lib/cache-cp15.c13
-rw-r--r--arch/arm/mach-rockchip/rk3288-board.c39
-rw-r--r--arch/arm/mach-tegra/board2.c3
-rw-r--r--arch/arm/mach-tegra/clock.c10
-rw-r--r--arch/arm/mach-tegra/tegra124/clock.c18
10 files changed, 134 insertions, 43 deletions
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0bb3441fb8..365d8f08cb 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -38,7 +38,8 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
@@ -62,7 +63,8 @@ c_runtime_cpu_setup:
*************************************************************************
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
index 8aab607cc5..2e6272b81b 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -21,7 +21,7 @@
stdout-path = &uart2;
};
- panel_regulator: panel-regualtor {
+ panel_regulator: panel-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
index fff1d78169..65c3851aff 100644
--- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -12,4 +12,13 @@
u-boot,dm-pre-reloc;
};
};
+
+ spi@7000d400 {
+ spi-deactivate-delay = <200>;
+ spi-max-frequency = <3000000>;
+
+ cros_ec: cros-ec@0 {
+ ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ };
+ };
};
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d575f4a163..cb0a935edc 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
/* CRU_CLKSEL11_CON */
enum {
HSICPHY_DIV_SHIFT = 8,
- HSICPHY_DIV_MASK = 0x3f,
+ HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT,
MMC0_PLL_SHIFT = 6,
- MMC0_PLL_MASK = 3,
+ MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
MMC0_PLL_SELECT_CODEC = 0,
MMC0_PLL_SELECT_GENERAL,
MMC0_PLL_SELECT_24MHZ,
MMC0_DIV_SHIFT = 0,
- MMC0_DIV_MASK = 0x3f,
+ MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
};
/* CRU_CLKSEL12_CON */
enum {
EMMC_PLL_SHIFT = 0xe,
- EMMC_PLL_MASK = 3,
+ EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_PLL_SELECT_CODEC = 0,
EMMC_PLL_SELECT_GENERAL,
EMMC_PLL_SELECT_24MHZ,
EMMC_DIV_SHIFT = 8,
- EMMC_DIV_MASK = 0x3f,
+ EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT,
SDIO0_PLL_SHIFT = 6,
- SDIO0_PLL_MASK = 3,
+ SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT,
SDIO0_PLL_SELECT_CODEC = 0,
SDIO0_PLL_SELECT_GENERAL,
SDIO0_PLL_SELECT_24MHZ,
SDIO0_DIV_SHIFT = 0,
- SDIO0_DIV_MASK = 0x3f,
+ SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT,
};
/* CRU_CLKSEL21_CON */
enum {
- MAC_DIV_CON_SHIFT = 0xf,
- MAC_DIV_CON_MASK = 0x1f,
+ MAC_DIV_CON_SHIFT = 0xf,
+ MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT,
- RMII_EXTCLK_SHIFT = 4,
- RMII_EXTCLK_MASK = 1,
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT,
RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
RMII_EXTCLK_SELECT_EXT_CLK = 1,
- EMAC_PLL_SHIFT = 0,
- EMAC_PLL_MASK = 0x3,
- EMAC_PLL_SELECT_NEW = 0x0,
- EMAC_PLL_SELECT_CODEC = 0x1,
- EMAC_PLL_SELECT_GENERAL = 0x2,
+ EMAC_PLL_SHIFT = 0,
+ EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT,
+ EMAC_PLL_SELECT_NEW = 0x0,
+ EMAC_PLL_SELECT_CODEC = 0x1,
+ EMAC_PLL_SELECT_GENERAL = 0x2,
};
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,
- SPI1_PLL_MASK = 1,
+ SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT,
SPI1_PLL_SELECT_CODEC = 0,
SPI1_PLL_SELECT_GENERAL,
SPI1_DIV_SHIFT = 8,
- SPI1_DIV_MASK = 0x7f,
+ SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
SPI0_PLL_SHIFT = 7,
- SPI0_PLL_MASK = 1,
+ SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT,
SPI0_PLL_SELECT_CODEC = 0,
SPI0_PLL_SELECT_GENERAL,
SPI0_DIV_SHIFT = 0,
- SPI0_DIV_MASK = 0x7f,
+ SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT,
};
/* CRU_CLKSEL37_CON */
enum {
PCLK_CORE_DBG_DIV_SHIFT = 9,
- PCLK_CORE_DBG_DIV_MASK = 0x1f,
+ PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
ATCLK_CORE_DIV_CON_SHIFT = 4,
- ATCLK_CORE_DIV_CON_MASK = 0x1f,
+ ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
CLK_L2RAM_DIV_SHIFT = 0,
- CLK_L2RAM_DIV_MASK = 7,
+ CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT,
};
/* CRU_CLKSEL39_CON */
enum {
ACLK_HEVC_PLL_SHIFT = 0xe,
- ACLK_HEVC_PLL_MASK = 3,
+ ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT,
ACLK_HEVC_PLL_SELECT_CODEC = 0,
ACLK_HEVC_PLL_SELECT_GENERAL,
ACLK_HEVC_PLL_SELECT_NEW,
ACLK_HEVC_DIV_SHIFT = 8,
- ACLK_HEVC_DIV_MASK = 0x1f,
+ ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT,
SPI2_PLL_SHIFT = 7,
- SPI2_PLL_MASK = 1,
+ SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT,
SPI2_PLL_SELECT_CODEC = 0,
SPI2_PLL_SELECT_GENERAL,
SPI2_DIV_SHIFT = 0,
- SPI2_DIV_MASK = 0x7f,
+ SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT,
};
/* CRU_MODE_CON */
enum {
+ CRU_MODE_MASK = 3,
+
NPLL_MODE_SHIFT = 0xe,
- NPLL_MODE_MASK = 3,
+ NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT,
NPLL_MODE_SLOW = 0,
NPLL_MODE_NORMAL,
NPLL_MODE_DEEP,
GPLL_MODE_SHIFT = 0xc,
- GPLL_MODE_MASK = 3,
+ GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT,
GPLL_MODE_SLOW = 0,
GPLL_MODE_NORMAL,
GPLL_MODE_DEEP,
CPLL_MODE_SHIFT = 8,
- CPLL_MODE_MASK = 3,
+ CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT,
CPLL_MODE_SLOW = 0,
CPLL_MODE_NORMAL,
CPLL_MODE_DEEP,
DPLL_MODE_SHIFT = 4,
- DPLL_MODE_MASK = 3,
+ DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
DPLL_MODE_SLOW = 0,
DPLL_MODE_NORMAL,
DPLL_MODE_DEEP,
APLL_MODE_SHIFT = 0,
- APLL_MODE_MASK = 3,
+ APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
APLL_MODE_SLOW = 0,
APLL_MODE_NORMAL,
APLL_MODE_DEEP,
@@ -201,21 +203,21 @@ enum {
/* CRU_APLL_CON0 */
enum {
CLKR_SHIFT = 8,
- CLKR_MASK = 0x3f,
+ CLKR_MASK = 0x3f << CLKR_SHIFT,
CLKOD_SHIFT = 0,
- CLKOD_MASK = 0xf,
+ CLKOD_MASK = 0xf << CLKOD_SHIFT,
};
/* CRU_APLL_CON1 */
enum {
LOCK_SHIFT = 0x1f,
- LOCK_MASK = 1,
+ LOCK_MASK = 1 << LOCK_SHIFT,
LOCK_UNLOCK = 0,
LOCK_LOCK,
CLKF_SHIFT = 0,
- CLKF_MASK = 0x1fff,
+ CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
#endif
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 388afcb723..f62b2a4378 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -288,6 +288,9 @@ void clock_init(void);
/* Initialize the PLLs */
void clock_early_init(void);
+/* @return true if hardware indicates that clock_early_init() was called */
+bool clock_early_init_done(void);
+
/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id);
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9bbcf5122..cf852c061b 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -129,7 +129,7 @@ static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
-#ifdef CONFIG_ARMV7_LPAE
+#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
/* Set up 4 PTE entries pointing to our 4 1GB page tables */
for (i = 0; i < 4; i++) {
u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
@@ -147,7 +147,7 @@ static inline void mmu_setup(void)
#endif
if (is_hyp()) {
- /* Set HCTR to enable LPAE */
+ /* Set HTCR to enable LPAE */
asm volatile("mcr p15, 4, %0, c2, c0, 2"
: : "r" (reg) : "memory");
/* Set HTTBR0 */
@@ -172,6 +172,15 @@ static inline void mmu_setup(void)
: : "r" (MEMORY_ATTRIBUTES) : "memory");
}
#elif defined(CONFIG_CPU_V7)
+ if (is_hyp()) {
+ /* Set HTCR to disable LPAE */
+ asm volatile("mcr p15, 4, %0, c2, c0, 2"
+ : : "r" (0) : "memory");
+ } else {
+ /* Set TTBCR to disable LPAE */
+ asm volatile("mcr p15, 0, %0, c2, c0, 2"
+ : : "r" (0) : "memory");
+ }
/* Set TTBR0 */
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 9894a25e08..a354d992da 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -86,8 +86,10 @@ static int veyron_init(void)
int ret;
ret = regulator_get_by_platname("vdd_arm", &dev);
- if (ret)
+ if (ret) {
+ debug("Cannot set regulator name\n");
return ret;
+ }
/* Slowly raise to max CPU voltage to prevent overshoot */
ret = regulator_set_value(dev, 1200000);
@@ -307,3 +309,38 @@ U_BOOT_CMD(
"display information about clocks",
""
);
+
+#define GRF_SOC_CON2 0xff77024c
+
+int board_early_init_f(void)
+{
+ struct udevice *pinctrl;
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * This init is done in SPL, but when chain-loading U-Boot SPL will
+ * have been skipped. Allow the clock driver to check if it needs
+ * setting up.
+ */
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return ret;
+ }
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ return ret;
+ }
+
+ /* Enable debug UART */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+ if (ret) {
+ debug("%s: Failed to set up console UART\n", __func__);
+ return ret;
+ }
+ rk_setreg(GRF_SOC_CON2, 1 << 0);
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 84f1ee5035..1e627ba603 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -191,6 +191,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
int board_early_init_f(void)
{
+ if (!clock_early_init_done())
+ clock_early_init();
+
#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
#define USBCMD_FS2 (1 << 15)
{
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 3bb72331a4..bac42119cd 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
* return value doesn't help. In summary this clock driver is
* quite broken but I'm afraid I have no idea how to fix it
* without completely replacing it.
+ *
+ * Be careful to avoid a divide by zero error.
*/
- div -= 2;
+ if (div >= 1)
+ div -= 2;
break;
#endif
default:
@@ -825,3 +828,8 @@ int clock_external_output(int clk_id)
return 0;
}
+
+__weak bool clock_early_init_done(void)
+{
+ return true;
+}
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 5e4406102f..5ae718b342 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -891,6 +891,24 @@ void clock_early_init(void)
udelay(2);
}
+/*
+ * clock_early_init_done - Check if clock_early_init() has been called
+ *
+ * Check a register that we set up to see if clock_early_init() has already
+ * been called.
+ *
+ * @return true if clock_early_init() was called, false if not
+ */
+bool clock_early_init_done(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ val = readl(&clkrst->crc_sclk_brst_pol);
+
+ return val == 0x20002222;
+}
+
void arch_timer_init(void)
{
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
generated by cgit (git 2.34.1) at 2025-02-01 07:48:57 +0000