diff options
Diffstat (limited to 'arch/arm')
56 files changed, 3494 insertions, 3274 deletions
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index b2d30b1a72..35d8d387bd 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,3 +1,6 @@ obj-$(CONFIG_AT91FAMILY) += at91-common/ -obj-$(CONFIG_TEGRA) += $(SOC)-common/ +obj-$(CONFIG_TEGRA20) += tegra20-common/ +obj-$(CONFIG_TEGRA30) += tegra30-common/ +obj-$(CONFIG_TEGRA114) += tegra114-common/ +obj-$(CONFIG_TEGRA124) += tegra124-common/ obj-$(CONFIG_TEGRA) += tegra-common/ diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3e2358e132..1cfcca9fa6 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -15,48 +15,7 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -70,26 +29,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -152,195 +92,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: -#if !defined(CONFIG_SYS_ICACHE_OFF) - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache -#endif -#if !defined(CONFIG_SYS_DCACHE_OFF) - mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache -#endif - mov pc, lr @ back to caller -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ce620115d4..0704bdde27 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -25,48 +25,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - -.globl _start -_start: b reset -#ifndef CONFIG_SPL_BUILD - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq -_pad: - .word 0x12345678 /* now 16*4=64 */ -#else - . = _start + 64 -#endif - -.global _end_vect -_end_vect: - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -77,14 +35,7 @@ _end_vect: ************************************************************************* */ -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -182,150 +133,3 @@ skip_tcmdisable: c_runtime_cpu_setup: mov pc, lr - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - */ - - .macro bad_save_user_regs - /* carve out a frame on current user stack */ - sub sp, sp, #S_FRAME_SIZE - /* Save user registers (now in svc mode) r0-r12 */ - stmia sp, {r0 - r12} - - ldr r2, IRQ_STACK_START_IN - /* get values for "aborted" pc and cpsr (into parm regs) */ - ldmia r2, {r2 - r3} - /* grab pointer to old stack */ - add r0, sp, #S_FRAME_SIZE - - add r5, sp, #S_SP - mov r1, lr - /* save sp_SVC, lr_SVC, pc, cpsr */ - stmia r5, {r0 - r3} - /* save current stack into r0 (param register) */ - mov r0, sp - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - /* save caller lr in position 0 of saved stack */ - str lr, [r13] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r13, #4] - - /* prepare SVC-Mode */ - mov r13, #MODE_SVC - @ msr spsr_c, r13 - /* switch modes, make sure moves will execute */ - msr spsr, r13 - /* capture return pc */ - mov lr, pc - /* jump to next instruction & switch modes. */ - movs pc, lr - .endm - - .macro get_bad_stack_swi - /* space on current stack for scratch reg. */ - sub r13, r13, #4 - /* save R0's value. */ - str r0, [r13] - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - /* save caller lr in position 0 of saved stack */ - str lr, [r0] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r0, #4] - /* restore lr */ - ldr lr, [r0] - /* restore r0 */ - ldr r0, [r13] - /* pop stack entry */ - add r13, r13, #4 - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 1a34842690..01c85be64b 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -15,48 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from RAM! @@ -67,26 +25,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -139,169 +78,3 @@ cpu_init_crit: mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 168f525ec7..c6f3b029a1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, /* - * T30: 1.4 GHz + * T30: 600 MHz * * Register Field Bits Width * ------------------------------ @@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { * PLLX_MISC cpcon 11: 8 4 */ { - { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ - { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, /* * T114: 700 MHz diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index a80648389c..9003902e3f 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, ®->cnfg); } +#define TPS62366A_I2C_ADDR 0xC0 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) + +#define TPS62361B_I2C_ADDR 0xC0 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + #define TPS65911_I2C_ADDR 0x5A #define TPS65911_VDDCTRL_OP_REG 0x28 #define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) #define I2C_SEND_2_BYTES 0x0A02 @@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void) reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); + /* Set VDD_CORE to 1.200V. */ +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); +#endif +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); +#endif + udelay(1000); + /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.4V, then enable the VDD regulator. + * First set VDD to 1.0125V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 96994043e4..623a635208 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -16,7 +16,8 @@ SECTIONS .text : { *(.__image_copy_start) - arch/arm/cpu/arm920t/start.o (.text*) + *(.vectors) + arch/arm/cpu/arm920t/start.o (.text*) /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ . = 0x1000; LONG(0x53555243) diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 7bf094aec1..07404502c8 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -15,36 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b start_code - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (called from the ARM reset exception vector) * * do important init only if we don't start from memory! @@ -55,28 +25,9 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de + .globl reset -/* - * the actual start code - */ - -start_code: +reset: /* * set the cpu to SVC32 mode */ @@ -196,166 +147,3 @@ cpu_init_crit: mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC - mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - /* return & move spsr_svc into cpsr */ - subs pc, lr, #4 - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 34a0fcb462..9b60436539 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -27,70 +27,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_vt_reset: - .word _reset -_vt_undefined_instruction: - .word _hang -_vt_software_interrupt: - .word _hang -_vt_prefetch_abort: - .word _hang -_vt_data_abort: - .word _hang -_vt_not_used: - .word _reset -_vt_irq: - .word _hang -_vt_fiq: - .word _hang - -reset: - ldr pc, _vt_reset -undefined_instruction: - ldr pc, _vt_undefined_instruction -software_interrupt: - ldr pc, _vt_software_interrupt -prefetch_abort: - ldr pc, _vt_prefetch_abort -data_abort: - ldr pc, _vt_data_abort -not_used: - ldr pc, _vt_not_used -irq: - ldr pc, _vt_irq -fiq: - ldr pc, _vt_fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -101,28 +37,8 @@ fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -_reset: + .globl reset +reset: /* * If the CPU is configured in "Wait JTAG connection mode", the stack * pointer is not configured and is zero. This will cause crash when @@ -179,7 +95,3 @@ _reset: mov r0, #0 bx lr - -_hang: -1: - bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 7dbd5dbf99..290ac2e561 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -17,29 +17,6 @@ #include <config.h> -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: -_software_interrupt: -_prefetch_abort: -_data_abort: -_not_used: -_irq: -_fiq: - .word infinite_loop - -infinite_loop: - b infinite_loop - /* ************************************************************************* * @@ -53,9 +30,7 @@ infinite_loop: ************************************************************************* */ -/* - * the actual reset code - */ + .globl reset reset: /* diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index b6d0f65b66..c7ee19912f 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -21,6 +21,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/spear/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 0717327050..8eb249475e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -23,75 +23,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG -.globl _start -_start: -.globl _NOR_BOOT_CFG -_NOR_BOOT_CFG: - .word CONFIG_SYS_DV_NOR_BOOT_CFG - b reset -#else -.globl _start -_start: - b reset -#endif -#ifdef CONFIG_SPL_BUILD -/* No exception handlers in preloader */ - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang -/* pad to 64 byte boundary */ - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - -#endif /* CONFIG_SPL_BUILD */ - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -102,26 +33,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -198,175 +110,3 @@ flush_dcache: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: -1: - bl 1b /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index 0c8d92d737..e20e5a89aa 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -16,6 +16,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> static void cache_flush(void); @@ -51,3 +52,15 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } + +#ifndef CONFIG_INTEGRATOR + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + writew(0x0, 0xfffece10); + writew(0x8, 0xfffece10); + for (;;) + ; +} + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 7d50145836..41123716a7 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -22,45 +22,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -_vectors_end: - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -71,26 +32,7 @@ _vectors_end: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -157,189 +99,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -# ifdef CONFIG_INTEGRATOR - - /* Satisfied by general board level routine */ - -#else - - .align 5 -.globl reset_cpu -reset_cpu: - - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 - -#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 7404ea7348..c0c07b6a11 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -21,42 +21,6 @@ /* ************************************************************************* * - * Jump vector table - * - ************************************************************************* - */ - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -67,26 +31,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -132,174 +77,3 @@ cpu_init_crit: */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -.globl undefined_instruction -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -.globl software_interrupt -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -.globl prefetch_abort -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -.globl data_abort -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -.globl not_used -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - .align 5 -.globl irq -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -.globl fiq -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -.globl irq -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -.globl fiq -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 9edb47502c..ee7c2e5a4b 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -13,30 +13,23 @@ static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = EXYNOS5_GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5_GPIO_A14; count = 2; break; default: @@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral) return; } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static void exynos5420_uart_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5420_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS5420_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5420_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5420_GPIO_A14; count = 2; break; default: @@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral) } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; - gpio_func = GPIO_FUNC(0x2); + start = EXYNOS5_GPIO_C00; + start_ext = EXYNOS5_GPIO_C10; + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = EXYNOS5_GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; - gpio_func = GPIO_FUNC(0x3); + start = EXYNOS5_GPIO_C30; + start_ext = EXYNOS5_GPIO_C43; + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = EXYNOS5_GPIO_C40; + start_ext = 0; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = start; i < (start + 2); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags) static int exynos5420_mmc_config(int peripheral, int flags) { - struct exynos5420_gpio_part3 *gpio3 = - (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); - struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; - int i, start; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio3->c0; - bank_ext = &gpio3->c3; - start = 0; + start = EXYNOS5420_GPIO_C00; + start_ext = EXYNOS5420_GPIO_C30; break; case PERIPH_ID_SDMMC1: - bank = &gpio3->c1; - bank_ext = &gpio3->d1; - start = 4; + start = EXYNOS5420_GPIO_C10; + start_ext = EXYNOS5420_GPIO_D14; break; case PERIPH_ID_SDMMC2: - bank = &gpio3->c2; - bank_ext = NULL; - start = 0; + start = EXYNOS5420_GPIO_C20; + start_ext = 0; break; default: start = 0; @@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags) return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 3; i++) { + for (i = start; i < (start + 3); i++) { /* * MMC0 is intended to be used for eMMC. The * card detect pin is used as a VDDEN signal to * power on the eMMC. The 5420 iROM makes * this same assumption. */ - if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { - s5p_gpio_set_value(bank, i, 1); - s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { + gpio_set_value(i, 1); + gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { - - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; } } static void exynos5420_i2c_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C8: - s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C9: - s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C10: - s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); break; } } @@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5_gpio_part4 *gpio4 = - (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_I2S0: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); break; case PERIPH_ID_I2S1: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); break; } } @@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral) void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + cfg = S5P_GPIO_FUNC(0x5); + pin = EXYNOS5_GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } } void exynos5420_spi_config(int peripheral) { int cfg, pin, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5420_gpio_part4 *gpio4 = - (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_A20; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + pin = EXYNOS5420_GPIO_A24; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + pin = EXYNOS5420_GPIO_B11; + cfg = S5P_GPIO_FUNC(0x5); break; case PERIPH_ID_SPI3: - bank = &gpio4->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_F10; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI4: cfg = 0; @@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral) if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } else { for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, + S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, + S5P_GPIO_FUNC(0x4)); } } } @@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags) static void exynos4_i2c_config(int peripheral, int flags) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); break; } } static int exynos4_mmc_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; break; case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start = EXYNOS4_GPIO_K20; + start_ext = EXYNOS4_GPIO_K33; break; default: return -1; } - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } @@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags) static void exynos4_uart_config(int peripheral) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS4_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS4_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS4_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS4_GPIO_A14; count = 2; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return; } - for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + +static void exynos4x12_i2c_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4x12_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS4X12_GPIO_K20; + start_ext = EXYNOS4X12_GPIO_K33; + break; + default: + return -1; } + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) + continue; + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + return 0; } + +static void exynos4x12_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS4X12_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS4X12_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS4X12_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS4X12_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags) return 0; } +static int exynos4x12_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4x12_uart_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4x12_i2c_config(peripheral, flags); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: + return exynos4x12_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + debug("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { @@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags) else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { - return exynos4_pinmux_config(peripheral, flags); - } else { - debug("pinmux functionality not supported\n"); + if (proid_is_exynos4412()) + return exynos4x12_pinmux_config(peripheral, flags); + else + return exynos4_pinmux_config(peripheral, flags); } + debug("pinmux functionality not supported\n"); + return -1; } @@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node) return exynos5_pinmux_decode_periph_id(blob, node); else if (cpu_is_exynos4()) return exynos4_pinmux_decode_periph_id(blob, node); - else - return PERIPH_ID_NONE; + + return PERIPH_ID_NONE; } #endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index 1caaa2759f..2f2e9fcc7c 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -10,20 +10,7 @@ /* Save the parameter pass in by previous boot loader */ .global save_boot_params save_boot_params: - /* save the parameter here */ - - /* - * Setup stack for exception, which is located - * at the end of on-chip RAM. We don't expect exception prior to - * relocation and if that happens, we won't worry -- it will overide - * global data region as the code will goto reset. After relocation, - * this region won't be used by other part of program. - * Hence it is safe. - */ - ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - ldr r1, =IRQ_STACK_START_IN - str r0, [r1] - + /* no parameter to save */ bx lr diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 27be451a89..fedd7c8f7e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -19,46 +19,6 @@ #include <asm/system.h> #include <linux/linkage.h> -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -.globl _undefined_instruction -_undefined_instruction: .word undefined_instruction -.globl _software_interrupt -_software_interrupt: .word software_interrupt -.globl _prefetch_abort -_prefetch_abort: .word prefetch_abort -.globl _data_abort -_data_abort: .word data_abort -.globl _not_used -_not_used: .word not_used -.globl _irq -_irq: .word irq -.globl _fiq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /************************************************************************* * * Startup Code (reset vector) @@ -70,26 +30,7 @@ _end_vect: * *************************************************************************/ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: bl save_boot_params @@ -250,195 +191,3 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current - @ user stack - stmia sp, {r0 - r12} @ Save user registers (now in - @ svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort - @ stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc - @ and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 - @ (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! - @ a reserved stack spot would - @ be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into - @ cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter - @ in banked mode) - - str lr, [r13] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of - @ saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure - @ moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & - @ switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for - @ scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - @ spots for abort stack - str lr, [r0] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of - @ saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effective fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif /* CONFIG_USE_IRQ */ -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index f2a5965988..69500a64e2 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS } /* - * Zynq needs to discard more sections because the user + * Zynq needs to discard these sections because the user * is expected to pass this image on to tools for boot.bin * generation that require them to be dropped. */ diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 9d16079956..17d8be5b5b 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -11,6 +11,12 @@ #include <errno.h> #include <linux/compiler.h> +#ifdef CONFIG_CPU_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif + #define CPU_MASK_PXA_PRODID 0x000003f0 #define CPU_MASK_PXA_REVID 0x0000000f diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ae0d13ce8f..c77d51e6d8 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -23,54 +23,6 @@ #include <config.h> #include <version.h> -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) -#error "Init SP address must be set to 0xfffff800 for PXA250" -#endif -#endif - -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -84,26 +36,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -174,190 +107,6 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -#endif /* CONFIG_SPL_BUILD */ - - /* * Enable MMU to use DCache as DRAM. * diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 6651898de2..4c9752a1c8 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -17,6 +17,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -52,3 +53,16 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } + +#define RST_BASE 0x90030000 +#define RSRR 0x00 +#define RCSR 0x04 + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + /* repeat endlessly */ + while (1) { + writel(0, RST_BASE + RCSR); + writel(1, RST_BASE + RSRR); + } +} diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index bf80937a7c..78e0cb8868 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -16,36 +16,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -56,26 +26,7 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -173,177 +124,3 @@ cpu_init_crit: mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RSRR] @ and perform reset - b reset_cpu @ silly, but repeat endlessly diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c index d62618cd0f..6e3ab0c14c 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -86,12 +86,31 @@ #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* This register/field only exists on Tegra114 and later */ +#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 +#define CLAMP_INPUTS_WHEN_TRISTATED 1 + +void pinmux_set_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + u32 val; + + val = readl(reg); + val |= CLAMP_INPUTS_WHEN_TRISTATED; + writel(val, reg); +} +#endif + void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) { u32 *reg = MUX_REG(pin); int i, mux = -1; u32 val; + if (func == PMUX_FUNC_DEFAULT) + return; + /* Error check on pin and func */ assert(pmux_pingrp_isvalid(pin)); assert(pmux_func_isvalid(func)); diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index 8209f7661a..ec95d7ceb1 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c @@ -19,74 +19,6 @@ enum security_op { SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ }; -static void debug_print_vector(char *name, u32 num_bytes, u8 *data) -{ - u32 i; - - debug("%s [%d] @0x%08x", name, num_bytes, (u32)data); - for (i = 0; i < num_bytes; i++) { - if (i % 16 == 0) - debug(" = "); - debug("%02x", data[i]); - if ((i+1) % 16 != 0) - debug(" "); - } - debug("\n"); -} - -/** - * Apply chain data to the destination using EOR - * - * Each array is of length AES_AES_KEY_LENGTH. - * - * \param cbc_chain_data Chain data - * \param src Source data - * \param dst Destination data, which is modified here - */ -static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst) -{ - int i; - - for (i = 0; i < 16; i++) - *dst++ = *src++ ^ *cbc_chain_data++; -} - -/** - * Encrypt some data with AES. - * - * \param key_schedule Expanded key to use - * \param src Source data to encrypt - * \param dst Destination buffer - * \param num_aes_blocks Number of AES blocks to encrypt - */ -static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst, - u32 num_aes_blocks) -{ - u8 tmp_data[AES_KEY_LENGTH]; - u8 *cbc_chain_data; - u32 i; - - cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ - - for (i = 0; i < num_aes_blocks; i++) { - debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES Src", AES_KEY_LENGTH, src); - - /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); - debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); - - /* encrypt the AES block */ - aes_encrypt(tmp_data, key_schedule, dst); - debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); - - /* Update pointers for next loop. */ - cbc_chain_data = dst; - src += AES_KEY_LENGTH; - dst += AES_KEY_LENGTH; - } -} - /** * Shift a vector left by one bit * @@ -129,39 +61,31 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, for (i = 0; i < AES_KEY_LENGTH; i++) tmp_data[i] = 0; - encrypt_object(key_schedule, tmp_data, left, 1); - debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left); + aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1); left_shift_vector(left, k1, sizeof(left)); - debug_print_vector("L", AES_KEY_LENGTH, left); if ((left[0] >> 7) != 0) /* get MSB of L */ k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; - debug_print_vector("K1", AES_KEY_LENGTH, k1); /* compute the AES-CMAC value */ for (i = 0; i < num_aes_blocks; i++) { /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); /* for the final block, XOR K1 into the IV */ if (i == num_aes_blocks - 1) - apply_cbc_chain_data(tmp_data, k1, tmp_data); + aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); /* encrypt the AES block */ aes_encrypt(tmp_data, key_schedule, dst); debug("sign_obj: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src); - debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data); - debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst); /* Update pointers for next loop. */ cbc_chain_data = dst; src += AES_KEY_LENGTH; } - - debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst); } /** @@ -180,7 +104,6 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, u8 key_schedule[AES_EXPAND_KEY_LENGTH]; debug("encrypt_and_sign: length = %d\n", length); - debug_print_vector("AES key", AES_KEY_LENGTH, key); /* * The only need for a key is for signing/checksum purposes, so @@ -193,7 +116,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, if (oper & SECURITY_ENCRYPT) { /* Perform this in place, resulting in src being encrypted. */ debug("encrypt_and_sign: begin encryption\n"); - encrypt_object(key_schedule, src, src, num_aes_blocks); + aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks); debug("encrypt_and_sign: end encryption\n"); } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 3e886680e8..4beddf08e7 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -18,6 +18,7 @@ SECTIONS .text : { __image_copy_start = .; + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 33c1f99fc0..a7728e0a2d 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 5c9d2aed68..15059d2202 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -36,10 +36,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x2008002 0>; + cd-gpios = <&gpio 0xA2 0>; }; sdhci@12540000 { status = "disabled"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 992e0234c9..0ff69393b7 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -101,7 +101,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -111,10 +111,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { status = "disabled"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 1cdd981d6d..6941906aaa 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -24,7 +24,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -34,7 +34,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index 7d32067fdd..1596f8328a 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -415,7 +415,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2004002 0>; + pwr-gpios = <&gpio 0xB2 0>; }; sdhci@12520000 { @@ -425,7 +425,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20C6004 0>; + cd-gpios = <&gpio 0x3BC 0>; }; sdhci@12540000 { diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts index a3c9c91f32..7af2a88fd0 100644 --- a/arch/arm/dts/imx6q-sabreauto.dts +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -1,9 +1,9 @@ /* - + * Copyright 2012 Freescale Semiconductor, Inc. - + * Copyright 2011 Linaro Ltd. - + * - + * SPDX-License-Identifier: GPL-2.0+ - + */ + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ /dts-v1/; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b04dfbbcb9..0e713952dc 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802830..6e46ea8dcd 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c new file mode 100644 index 0000000000..0121cd78f2 --- /dev/null +++ b/arch/arm/imx-common/video.c @@ -0,0 +1,65 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/imx-common/video.h> + +extern struct display_info_t const displays[]; +extern size_t display_count; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < display_count; i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < display_count; i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < display_count) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_IMX_HDMI +#include <asm/arch/mxc_hdmi.h> +#include <asm/io.h> +int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 7637457549..f00fad38fe 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -42,6 +42,8 @@ #define MODULE_CLKCTRL_IDLEST_DISABLED 3 /* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index fdf73b507a..ba717146f5 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -98,7 +98,7 @@ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_AUDIOSS_BASE 0x03810000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_GPIO_PART8_BASE 0x03860000 #define EXYNOS5_PRO_ID 0x10000000 #define EXYNOS5_CLOCK_BASE 0x10010000 #define EXYNOS5_POWER_BASE 0x10040000 @@ -108,9 +108,13 @@ #define EXYNOS5_WATCHDOG_BASE 0x101D0000 #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART5_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART6_BASE 0x10D10060 +#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_GPIO_PART2_BASE 0x114002E0 +#define EXYNOS5_GPIO_PART3_BASE 0x11400C00 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 #define EXYNOS5_USB3PHY_BASE 0x12100000 @@ -125,7 +129,7 @@ #define EXYNOS5_I2S_BASE 0x12D60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_GPIO_PART4_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 #define EXYNOS5_DP_BASE 0x145B0000 @@ -135,7 +139,7 @@ /* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -158,8 +162,9 @@ #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000 diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index d6868fa25d..be5113f0e2 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -19,328 +19,1515 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct exynos4_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank e2; - struct s5p_gpio_bank e3; - struct s5p_gpio_bank e4; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; -}; +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 -struct exynos4_gpio_part2 { - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum exynos4_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4_GPIO_A00, /* 0 */ + EXYNOS4_GPIO_A01, + EXYNOS4_GPIO_A02, + EXYNOS4_GPIO_A03, + EXYNOS4_GPIO_A04, + EXYNOS4_GPIO_A05, + EXYNOS4_GPIO_A06, + EXYNOS4_GPIO_A07, + EXYNOS4_GPIO_A10, /* 8 */ + EXYNOS4_GPIO_A11, + EXYNOS4_GPIO_A12, + EXYNOS4_GPIO_A13, + EXYNOS4_GPIO_A14, + EXYNOS4_GPIO_A15, + EXYNOS4_GPIO_A16, + EXYNOS4_GPIO_A17, + EXYNOS4_GPIO_B0, /* 16 0x10 */ + EXYNOS4_GPIO_B1, + EXYNOS4_GPIO_B2, + EXYNOS4_GPIO_B3, + EXYNOS4_GPIO_B4, + EXYNOS4_GPIO_B5, + EXYNOS4_GPIO_B6, + EXYNOS4_GPIO_B7, + EXYNOS4_GPIO_C00, /* 24 0x18 */ + EXYNOS4_GPIO_C01, + EXYNOS4_GPIO_C02, + EXYNOS4_GPIO_C03, + EXYNOS4_GPIO_C04, + EXYNOS4_GPIO_C05, + EXYNOS4_GPIO_C06, + EXYNOS4_GPIO_C07, + EXYNOS4_GPIO_C10, /* 32 0x20*/ + EXYNOS4_GPIO_C11, + EXYNOS4_GPIO_C12, + EXYNOS4_GPIO_C13, + EXYNOS4_GPIO_C14, + EXYNOS4_GPIO_C15, + EXYNOS4_GPIO_C16, + EXYNOS4_GPIO_C17, + EXYNOS4_GPIO_D00, /* 40 0x28 */ + EXYNOS4_GPIO_D01, + EXYNOS4_GPIO_D02, + EXYNOS4_GPIO_D03, + EXYNOS4_GPIO_D04, + EXYNOS4_GPIO_D05, + EXYNOS4_GPIO_D06, + EXYNOS4_GPIO_D07, + EXYNOS4_GPIO_D10, /* 48 0x30 */ + EXYNOS4_GPIO_D11, + EXYNOS4_GPIO_D12, + EXYNOS4_GPIO_D13, + EXYNOS4_GPIO_D14, + EXYNOS4_GPIO_D15, + EXYNOS4_GPIO_D16, + EXYNOS4_GPIO_D17, + EXYNOS4_GPIO_E00, /* 56 0x38 */ + EXYNOS4_GPIO_E01, + EXYNOS4_GPIO_E02, + EXYNOS4_GPIO_E03, + EXYNOS4_GPIO_E04, + EXYNOS4_GPIO_E05, + EXYNOS4_GPIO_E06, + EXYNOS4_GPIO_E07, + EXYNOS4_GPIO_E10, /* 64 0x40 */ + EXYNOS4_GPIO_E11, + EXYNOS4_GPIO_E12, + EXYNOS4_GPIO_E13, + EXYNOS4_GPIO_E14, + EXYNOS4_GPIO_E15, + EXYNOS4_GPIO_E16, + EXYNOS4_GPIO_E17, + EXYNOS4_GPIO_E20, /* 72 0x48 */ + EXYNOS4_GPIO_E21, + EXYNOS4_GPIO_E22, + EXYNOS4_GPIO_E23, + EXYNOS4_GPIO_E24, + EXYNOS4_GPIO_E25, + EXYNOS4_GPIO_E26, + EXYNOS4_GPIO_E27, + EXYNOS4_GPIO_E30, /* 80 0x50 */ + EXYNOS4_GPIO_E31, + EXYNOS4_GPIO_E32, + EXYNOS4_GPIO_E33, + EXYNOS4_GPIO_E34, + EXYNOS4_GPIO_E35, + EXYNOS4_GPIO_E36, + EXYNOS4_GPIO_E37, + EXYNOS4_GPIO_E40, /* 88 0x58 */ + EXYNOS4_GPIO_E41, + EXYNOS4_GPIO_E42, + EXYNOS4_GPIO_E43, + EXYNOS4_GPIO_E44, + EXYNOS4_GPIO_E45, + EXYNOS4_GPIO_E46, + EXYNOS4_GPIO_E47, + EXYNOS4_GPIO_F00, /* 96 0x60 */ + EXYNOS4_GPIO_F01, + EXYNOS4_GPIO_F02, + EXYNOS4_GPIO_F03, + EXYNOS4_GPIO_F04, + EXYNOS4_GPIO_F05, + EXYNOS4_GPIO_F06, + EXYNOS4_GPIO_F07, + EXYNOS4_GPIO_F10, /* 104 0x68 */ + EXYNOS4_GPIO_F11, + EXYNOS4_GPIO_F12, + EXYNOS4_GPIO_F13, + EXYNOS4_GPIO_F14, + EXYNOS4_GPIO_F15, + EXYNOS4_GPIO_F16, + EXYNOS4_GPIO_F17, + EXYNOS4_GPIO_F20, /* 112 0x70 */ + EXYNOS4_GPIO_F21, + EXYNOS4_GPIO_F22, + EXYNOS4_GPIO_F23, + EXYNOS4_GPIO_F24, + EXYNOS4_GPIO_F25, + EXYNOS4_GPIO_F26, + EXYNOS4_GPIO_F27, + EXYNOS4_GPIO_F30, /* 120 0x78 */ + EXYNOS4_GPIO_F31, + EXYNOS4_GPIO_F32, + EXYNOS4_GPIO_F33, + EXYNOS4_GPIO_F34, + EXYNOS4_GPIO_F35, + EXYNOS4_GPIO_F36, + EXYNOS4_GPIO_F37, -struct exynos4_gpio_part3 { - struct s5p_gpio_bank z; -}; + /* GPIO_PART2_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */ + EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1, + EXYNOS4_GPIO_J01, + EXYNOS4_GPIO_J02, + EXYNOS4_GPIO_J03, + EXYNOS4_GPIO_J04, + EXYNOS4_GPIO_J05, + EXYNOS4_GPIO_J06, + EXYNOS4_GPIO_J07, + EXYNOS4_GPIO_J10, /* 136 0x88 */ + EXYNOS4_GPIO_J11, + EXYNOS4_GPIO_J12, + EXYNOS4_GPIO_J13, + EXYNOS4_GPIO_J14, + EXYNOS4_GPIO_J15, + EXYNOS4_GPIO_J16, + EXYNOS4_GPIO_J17, + EXYNOS4_GPIO_K00, /* 144 0x90 */ + EXYNOS4_GPIO_K01, + EXYNOS4_GPIO_K02, + EXYNOS4_GPIO_K03, + EXYNOS4_GPIO_K04, + EXYNOS4_GPIO_K05, + EXYNOS4_GPIO_K06, + EXYNOS4_GPIO_K07, + EXYNOS4_GPIO_K10, /* 152 0x98 */ + EXYNOS4_GPIO_K11, + EXYNOS4_GPIO_K12, + EXYNOS4_GPIO_K13, + EXYNOS4_GPIO_K14, + EXYNOS4_GPIO_K15, + EXYNOS4_GPIO_K16, + EXYNOS4_GPIO_K17, + EXYNOS4_GPIO_K20, /* 160 0xA0 */ + EXYNOS4_GPIO_K21, + EXYNOS4_GPIO_K22, + EXYNOS4_GPIO_K23, + EXYNOS4_GPIO_K24, + EXYNOS4_GPIO_K25, + EXYNOS4_GPIO_K26, + EXYNOS4_GPIO_K27, + EXYNOS4_GPIO_K30, /* 168 0xA8 */ + EXYNOS4_GPIO_K31, + EXYNOS4_GPIO_K32, + EXYNOS4_GPIO_K33, + EXYNOS4_GPIO_K34, + EXYNOS4_GPIO_K35, + EXYNOS4_GPIO_K36, + EXYNOS4_GPIO_K37, + EXYNOS4_GPIO_L00, /* 176 0xB0 */ + EXYNOS4_GPIO_L01, + EXYNOS4_GPIO_L02, + EXYNOS4_GPIO_L03, + EXYNOS4_GPIO_L04, + EXYNOS4_GPIO_L05, + EXYNOS4_GPIO_L06, + EXYNOS4_GPIO_L07, + EXYNOS4_GPIO_L10, /* 184 0xB8 */ + EXYNOS4_GPIO_L11, + EXYNOS4_GPIO_L12, + EXYNOS4_GPIO_L13, + EXYNOS4_GPIO_L14, + EXYNOS4_GPIO_L15, + EXYNOS4_GPIO_L16, + EXYNOS4_GPIO_L17, + EXYNOS4_GPIO_L20, /* 192 0xC0 */ + EXYNOS4_GPIO_L21, + EXYNOS4_GPIO_L22, + EXYNOS4_GPIO_L23, + EXYNOS4_GPIO_L24, + EXYNOS4_GPIO_L25, + EXYNOS4_GPIO_L26, + EXYNOS4_GPIO_L27, + EXYNOS4_GPIO_Y00, /* 200 0xC8 */ + EXYNOS4_GPIO_Y01, + EXYNOS4_GPIO_Y02, + EXYNOS4_GPIO_Y03, + EXYNOS4_GPIO_Y04, + EXYNOS4_GPIO_Y05, + EXYNOS4_GPIO_Y06, + EXYNOS4_GPIO_Y07, + EXYNOS4_GPIO_Y10, /* 208 0xD0 */ + EXYNOS4_GPIO_Y11, + EXYNOS4_GPIO_Y12, + EXYNOS4_GPIO_Y13, + EXYNOS4_GPIO_Y14, + EXYNOS4_GPIO_Y15, + EXYNOS4_GPIO_Y16, + EXYNOS4_GPIO_Y17, + EXYNOS4_GPIO_Y20, /* 216 0xD8 */ + EXYNOS4_GPIO_Y21, + EXYNOS4_GPIO_Y22, + EXYNOS4_GPIO_Y23, + EXYNOS4_GPIO_Y24, + EXYNOS4_GPIO_Y25, + EXYNOS4_GPIO_Y26, + EXYNOS4_GPIO_Y27, + EXYNOS4_GPIO_Y30, /* 224 0xE0 */ + EXYNOS4_GPIO_Y31, + EXYNOS4_GPIO_Y32, + EXYNOS4_GPIO_Y33, + EXYNOS4_GPIO_Y34, + EXYNOS4_GPIO_Y35, + EXYNOS4_GPIO_Y36, + EXYNOS4_GPIO_Y37, + EXYNOS4_GPIO_Y40, /* 232 0xE8 */ + EXYNOS4_GPIO_Y41, + EXYNOS4_GPIO_Y42, + EXYNOS4_GPIO_Y43, + EXYNOS4_GPIO_Y44, + EXYNOS4_GPIO_Y45, + EXYNOS4_GPIO_Y46, + EXYNOS4_GPIO_Y47, + EXYNOS4_GPIO_Y50, /* 240 0xF0 */ + EXYNOS4_GPIO_Y51, + EXYNOS4_GPIO_Y52, + EXYNOS4_GPIO_Y53, + EXYNOS4_GPIO_Y54, + EXYNOS4_GPIO_Y55, + EXYNOS4_GPIO_Y56, + EXYNOS4_GPIO_Y57, + EXYNOS4_GPIO_Y60, /* 248 0xF8 */ + EXYNOS4_GPIO_Y61, + EXYNOS4_GPIO_Y62, + EXYNOS4_GPIO_Y63, + EXYNOS4_GPIO_Y64, + EXYNOS4_GPIO_Y65, + EXYNOS4_GPIO_Y66, + EXYNOS4_GPIO_Y67, + EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */ + EXYNOS4_GPIO_X01, + EXYNOS4_GPIO_X02, + EXYNOS4_GPIO_X03, + EXYNOS4_GPIO_X04, + EXYNOS4_GPIO_X05, + EXYNOS4_GPIO_X06, + EXYNOS4_GPIO_X07, + EXYNOS4_GPIO_X10, /* 904 0x388 */ + EXYNOS4_GPIO_X11, + EXYNOS4_GPIO_X12, + EXYNOS4_GPIO_X13, + EXYNOS4_GPIO_X14, + EXYNOS4_GPIO_X15, + EXYNOS4_GPIO_X16, + EXYNOS4_GPIO_X17, + EXYNOS4_GPIO_X20, /* 912 0x390 */ + EXYNOS4_GPIO_X21, + EXYNOS4_GPIO_X22, + EXYNOS4_GPIO_X23, + EXYNOS4_GPIO_X24, + EXYNOS4_GPIO_X25, + EXYNOS4_GPIO_X26, + EXYNOS4_GPIO_X27, + EXYNOS4_GPIO_X30, /* 920 0x398 */ + EXYNOS4_GPIO_X31, + EXYNOS4_GPIO_X32, + EXYNOS4_GPIO_X33, + EXYNOS4_GPIO_X34, + EXYNOS4_GPIO_X35, + EXYNOS4_GPIO_X36, + EXYNOS4_GPIO_X37, + + /* GPIO_PART3_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_Z1, + EXYNOS4_GPIO_Z2, + EXYNOS4_GPIO_Z3, + EXYNOS4_GPIO_Z4, + EXYNOS4_GPIO_Z5, + EXYNOS4_GPIO_Z6, + EXYNOS4_GPIO_Z7, -struct exynos4x12_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank res1[0x5]; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank res2[0x2]; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; + EXYNOS4_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part2 { - struct s5p_gpio_bank res1[0x2]; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res2[0x3]; - struct s5p_gpio_bank m0; - struct s5p_gpio_bank m1; - struct s5p_gpio_bank m2; - struct s5p_gpio_bank m3; - struct s5p_gpio_bank m4; - struct s5p_gpio_bank res3[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; +enum exynos4X12_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4X12_GPIO_A00, /* 0 */ + EXYNOS4X12_GPIO_A01, + EXYNOS4X12_GPIO_A02, + EXYNOS4X12_GPIO_A03, + EXYNOS4X12_GPIO_A04, + EXYNOS4X12_GPIO_A05, + EXYNOS4X12_GPIO_A06, + EXYNOS4X12_GPIO_A07, + EXYNOS4X12_GPIO_A10, /* 8 */ + EXYNOS4X12_GPIO_A11, + EXYNOS4X12_GPIO_A12, + EXYNOS4X12_GPIO_A13, + EXYNOS4X12_GPIO_A14, + EXYNOS4X12_GPIO_A15, + EXYNOS4X12_GPIO_A16, + EXYNOS4X12_GPIO_A17, + EXYNOS4X12_GPIO_B0, /* 16 0x10 */ + EXYNOS4X12_GPIO_B1, + EXYNOS4X12_GPIO_B2, + EXYNOS4X12_GPIO_B3, + EXYNOS4X12_GPIO_B4, + EXYNOS4X12_GPIO_B5, + EXYNOS4X12_GPIO_B6, + EXYNOS4X12_GPIO_B7, + EXYNOS4X12_GPIO_C00, /* 24 0x18 */ + EXYNOS4X12_GPIO_C01, + EXYNOS4X12_GPIO_C02, + EXYNOS4X12_GPIO_C03, + EXYNOS4X12_GPIO_C04, + EXYNOS4X12_GPIO_C05, + EXYNOS4X12_GPIO_C06, + EXYNOS4X12_GPIO_C07, + EXYNOS4X12_GPIO_C10, /* 32 0x20 */ + EXYNOS4X12_GPIO_C11, + EXYNOS4X12_GPIO_C12, + EXYNOS4X12_GPIO_C13, + EXYNOS4X12_GPIO_C14, + EXYNOS4X12_GPIO_C15, + EXYNOS4X12_GPIO_C16, + EXYNOS4X12_GPIO_C17, + EXYNOS4X12_GPIO_D00, /* 40 0x28 */ + EXYNOS4X12_GPIO_D01, + EXYNOS4X12_GPIO_D02, + EXYNOS4X12_GPIO_D03, + EXYNOS4X12_GPIO_D04, + EXYNOS4X12_GPIO_D05, + EXYNOS4X12_GPIO_D06, + EXYNOS4X12_GPIO_D07, + EXYNOS4X12_GPIO_D10, /* 48 0x30 */ + EXYNOS4X12_GPIO_D11, + EXYNOS4X12_GPIO_D12, + EXYNOS4X12_GPIO_D13, + EXYNOS4X12_GPIO_D14, + EXYNOS4X12_GPIO_D15, + EXYNOS4X12_GPIO_D16, + EXYNOS4X12_GPIO_D17, + EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */ + EXYNOS4X12_GPIO_F01, + EXYNOS4X12_GPIO_F02, + EXYNOS4X12_GPIO_F03, + EXYNOS4X12_GPIO_F04, + EXYNOS4X12_GPIO_F05, + EXYNOS4X12_GPIO_F06, + EXYNOS4X12_GPIO_F07, + EXYNOS4X12_GPIO_F10, /* 104 0x68 */ + EXYNOS4X12_GPIO_F11, + EXYNOS4X12_GPIO_F12, + EXYNOS4X12_GPIO_F13, + EXYNOS4X12_GPIO_F14, + EXYNOS4X12_GPIO_F15, + EXYNOS4X12_GPIO_F16, + EXYNOS4X12_GPIO_F17, + EXYNOS4X12_GPIO_F20, /* 112 0x70 */ + EXYNOS4X12_GPIO_F21, + EXYNOS4X12_GPIO_F22, + EXYNOS4X12_GPIO_F23, + EXYNOS4X12_GPIO_F24, + EXYNOS4X12_GPIO_F25, + EXYNOS4X12_GPIO_F26, + EXYNOS4X12_GPIO_F27, + EXYNOS4X12_GPIO_F30, /* 120 0x78 */ + EXYNOS4X12_GPIO_F31, + EXYNOS4X12_GPIO_F32, + EXYNOS4X12_GPIO_F33, + EXYNOS4X12_GPIO_F34, + EXYNOS4X12_GPIO_F35, + EXYNOS4X12_GPIO_F36, + EXYNOS4X12_GPIO_F37, + EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */ + EXYNOS4X12_GPIO_J01, + EXYNOS4X12_GPIO_J02, + EXYNOS4X12_GPIO_J03, + EXYNOS4X12_GPIO_J04, + EXYNOS4X12_GPIO_J05, + EXYNOS4X12_GPIO_J06, + EXYNOS4X12_GPIO_J07, + EXYNOS4X12_GPIO_J10, /* 152 0x98 */ + EXYNOS4X12_GPIO_J11, + EXYNOS4X12_GPIO_J12, + EXYNOS4X12_GPIO_J13, + EXYNOS4X12_GPIO_J14, + EXYNOS4X12_GPIO_J15, + EXYNOS4X12_GPIO_J16, + EXYNOS4X12_GPIO_J17, + + /* GPIO_PART2_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */ + EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */ + EXYNOS4X12_GPIO_K01, + EXYNOS4X12_GPIO_K02, + EXYNOS4X12_GPIO_K03, + EXYNOS4X12_GPIO_K04, + EXYNOS4X12_GPIO_K05, + EXYNOS4X12_GPIO_K06, + EXYNOS4X12_GPIO_K07, + EXYNOS4X12_GPIO_K10, /* 184 0xB8 */ + EXYNOS4X12_GPIO_K11, + EXYNOS4X12_GPIO_K12, + EXYNOS4X12_GPIO_K13, + EXYNOS4X12_GPIO_K14, + EXYNOS4X12_GPIO_K15, + EXYNOS4X12_GPIO_K16, + EXYNOS4X12_GPIO_K17, + EXYNOS4X12_GPIO_K20, /* 192 0xC0 */ + EXYNOS4X12_GPIO_K21, + EXYNOS4X12_GPIO_K22, + EXYNOS4X12_GPIO_K23, + EXYNOS4X12_GPIO_K24, + EXYNOS4X12_GPIO_K25, + EXYNOS4X12_GPIO_K26, + EXYNOS4X12_GPIO_K27, + EXYNOS4X12_GPIO_K30, /* 200 0xC8 */ + EXYNOS4X12_GPIO_K31, + EXYNOS4X12_GPIO_K32, + EXYNOS4X12_GPIO_K33, + EXYNOS4X12_GPIO_K34, + EXYNOS4X12_GPIO_K35, + EXYNOS4X12_GPIO_K36, + EXYNOS4X12_GPIO_K37, + EXYNOS4X12_GPIO_L00, /* 208 0xD0 */ + EXYNOS4X12_GPIO_L01, + EXYNOS4X12_GPIO_L02, + EXYNOS4X12_GPIO_L03, + EXYNOS4X12_GPIO_L04, + EXYNOS4X12_GPIO_L05, + EXYNOS4X12_GPIO_L06, + EXYNOS4X12_GPIO_L07, + EXYNOS4X12_GPIO_L10, /* 216 0xD8 */ + EXYNOS4X12_GPIO_L11, + EXYNOS4X12_GPIO_L12, + EXYNOS4X12_GPIO_L13, + EXYNOS4X12_GPIO_L14, + EXYNOS4X12_GPIO_L15, + EXYNOS4X12_GPIO_L16, + EXYNOS4X12_GPIO_L17, + EXYNOS4X12_GPIO_L20, /* 224 0xE0 */ + EXYNOS4X12_GPIO_L21, + EXYNOS4X12_GPIO_L22, + EXYNOS4X12_GPIO_L23, + EXYNOS4X12_GPIO_L24, + EXYNOS4X12_GPIO_L25, + EXYNOS4X12_GPIO_L26, + EXYNOS4X12_GPIO_L27, + EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */ + EXYNOS4X12_GPIO_Y01, + EXYNOS4X12_GPIO_Y02, + EXYNOS4X12_GPIO_Y03, + EXYNOS4X12_GPIO_Y04, + EXYNOS4X12_GPIO_Y05, + EXYNOS4X12_GPIO_Y06, + EXYNOS4X12_GPIO_Y07, + EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */ + EXYNOS4X12_GPIO_Y11, + EXYNOS4X12_GPIO_Y12, + EXYNOS4X12_GPIO_Y13, + EXYNOS4X12_GPIO_Y14, + EXYNOS4X12_GPIO_Y15, + EXYNOS4X12_GPIO_Y16, + EXYNOS4X12_GPIO_Y17, + EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */ + EXYNOS4X12_GPIO_Y21, + EXYNOS4X12_GPIO_Y22, + EXYNOS4X12_GPIO_Y23, + EXYNOS4X12_GPIO_Y24, + EXYNOS4X12_GPIO_Y25, + EXYNOS4X12_GPIO_Y26, + EXYNOS4X12_GPIO_Y27, + EXYNOS4X12_GPIO_Y30, /* 256 0x100 */ + EXYNOS4X12_GPIO_Y31, + EXYNOS4X12_GPIO_Y32, + EXYNOS4X12_GPIO_Y33, + EXYNOS4X12_GPIO_Y34, + EXYNOS4X12_GPIO_Y35, + EXYNOS4X12_GPIO_Y36, + EXYNOS4X12_GPIO_Y37, + EXYNOS4X12_GPIO_Y40, /* 264 0x108 */ + EXYNOS4X12_GPIO_Y41, + EXYNOS4X12_GPIO_Y42, + EXYNOS4X12_GPIO_Y43, + EXYNOS4X12_GPIO_Y44, + EXYNOS4X12_GPIO_Y45, + EXYNOS4X12_GPIO_Y46, + EXYNOS4X12_GPIO_Y47, + EXYNOS4X12_GPIO_Y50, /* 272 0x110 */ + EXYNOS4X12_GPIO_Y51, + EXYNOS4X12_GPIO_Y52, + EXYNOS4X12_GPIO_Y53, + EXYNOS4X12_GPIO_Y54, + EXYNOS4X12_GPIO_Y55, + EXYNOS4X12_GPIO_Y56, + EXYNOS4X12_GPIO_Y57, + EXYNOS4X12_GPIO_Y60, /* 280 0x118 */ + EXYNOS4X12_GPIO_Y61, + EXYNOS4X12_GPIO_Y62, + EXYNOS4X12_GPIO_Y63, + EXYNOS4X12_GPIO_Y64, + EXYNOS4X12_GPIO_Y65, + EXYNOS4X12_GPIO_Y66, + EXYNOS4X12_GPIO_Y67, + EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */ + EXYNOS4X12_GPIO_M01, + EXYNOS4X12_GPIO_M02, + EXYNOS4X12_GPIO_M03, + EXYNOS4X12_GPIO_M04, + EXYNOS4X12_GPIO_M05, + EXYNOS4X12_GPIO_M06, + EXYNOS4X12_GPIO_M07, + EXYNOS4X12_GPIO_M10, /* 320 0xF8 */ + EXYNOS4X12_GPIO_M11, + EXYNOS4X12_GPIO_M12, + EXYNOS4X12_GPIO_M13, + EXYNOS4X12_GPIO_M14, + EXYNOS4X12_GPIO_M15, + EXYNOS4X12_GPIO_M16, + EXYNOS4X12_GPIO_M17, + EXYNOS4X12_GPIO_M20, /* 328 0x100 */ + EXYNOS4X12_GPIO_M21, + EXYNOS4X12_GPIO_M22, + EXYNOS4X12_GPIO_M23, + EXYNOS4X12_GPIO_M24, + EXYNOS4X12_GPIO_M25, + EXYNOS4X12_GPIO_M26, + EXYNOS4X12_GPIO_M27, + EXYNOS4X12_GPIO_M30, /* 336 0x108 */ + EXYNOS4X12_GPIO_M31, + EXYNOS4X12_GPIO_M32, + EXYNOS4X12_GPIO_M33, + EXYNOS4X12_GPIO_M34, + EXYNOS4X12_GPIO_M35, + EXYNOS4X12_GPIO_M36, + EXYNOS4X12_GPIO_M37, + EXYNOS4X12_GPIO_M40, /* 344 0x110 */ + EXYNOS4X12_GPIO_M41, + EXYNOS4X12_GPIO_M42, + EXYNOS4X12_GPIO_M43, + EXYNOS4X12_GPIO_M44, + EXYNOS4X12_GPIO_M45, + EXYNOS4X12_GPIO_M46, + EXYNOS4X12_GPIO_M47, + EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */ + EXYNOS4X12_GPIO_X01, + EXYNOS4X12_GPIO_X02, + EXYNOS4X12_GPIO_X03, + EXYNOS4X12_GPIO_X04, + EXYNOS4X12_GPIO_X05, + EXYNOS4X12_GPIO_X06, + EXYNOS4X12_GPIO_X07, + EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */ + EXYNOS4X12_GPIO_X11, + EXYNOS4X12_GPIO_X12, + EXYNOS4X12_GPIO_X13, + EXYNOS4X12_GPIO_X14, + EXYNOS4X12_GPIO_X15, + EXYNOS4X12_GPIO_X16, + EXYNOS4X12_GPIO_X17, + EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */ + EXYNOS4X12_GPIO_X21, + EXYNOS4X12_GPIO_X22, + EXYNOS4X12_GPIO_X23, + EXYNOS4X12_GPIO_X24, + EXYNOS4X12_GPIO_X25, + EXYNOS4X12_GPIO_X26, + EXYNOS4X12_GPIO_X27, + EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */ + EXYNOS4X12_GPIO_X31, + EXYNOS4X12_GPIO_X32, + EXYNOS4X12_GPIO_X33, + EXYNOS4X12_GPIO_X34, + EXYNOS4X12_GPIO_X35, + EXYNOS4X12_GPIO_X36, + EXYNOS4X12_GPIO_X37, + + /* GPIO_PART3_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + EXYNOS4X12_GPIO_Z1, + EXYNOS4X12_GPIO_Z2, + EXYNOS4X12_GPIO_Z3, + EXYNOS4X12_GPIO_Z4, + EXYNOS4X12_GPIO_Z5, + EXYNOS4X12_GPIO_Z6, + EXYNOS4X12_GPIO_Z7, + + /* GPIO_PART4_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */ + EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, + EXYNOS4X12_GPIO_V01, + EXYNOS4X12_GPIO_V02, + EXYNOS4X12_GPIO_V03, + EXYNOS4X12_GPIO_V04, + EXYNOS4X12_GPIO_V05, + EXYNOS4X12_GPIO_V06, + EXYNOS4X12_GPIO_V07, + EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */ + EXYNOS4X12_GPIO_V11, + EXYNOS4X12_GPIO_V12, + EXYNOS4X12_GPIO_V13, + EXYNOS4X12_GPIO_V14, + EXYNOS4X12_GPIO_V15, + EXYNOS4X12_GPIO_V16, + EXYNOS4X12_GPIO_V17, + EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */ + EXYNOS4X12_GPIO_V21, + EXYNOS4X12_GPIO_V22, + EXYNOS4X12_GPIO_V23, + EXYNOS4X12_GPIO_V24, + EXYNOS4X12_GPIO_V25, + EXYNOS4X12_GPIO_V26, + EXYNOS4X12_GPIO_V27, + EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */ + EXYNOS4X12_GPIO_V31, + EXYNOS4X12_GPIO_V32, + EXYNOS4X12_GPIO_V33, + EXYNOS4X12_GPIO_V34, + EXYNOS4X12_GPIO_V35, + EXYNOS4X12_GPIO_V36, + EXYNOS4X12_GPIO_V37, + EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */ + EXYNOS4X12_GPIO_V41, + EXYNOS4X12_GPIO_V42, + EXYNOS4X12_GPIO_V43, + EXYNOS4X12_GPIO_V44, + EXYNOS4X12_GPIO_V45, + EXYNOS4X12_GPIO_V46, + EXYNOS4X12_GPIO_V47, + + EXYNOS4X12_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part3 { - struct s5p_gpio_bank z; +enum exynos5_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5_GPIO_A00, /* 0 */ + EXYNOS5_GPIO_A01, + EXYNOS5_GPIO_A02, + EXYNOS5_GPIO_A03, + EXYNOS5_GPIO_A04, + EXYNOS5_GPIO_A05, + EXYNOS5_GPIO_A06, + EXYNOS5_GPIO_A07, + EXYNOS5_GPIO_A10, /* 8 */ + EXYNOS5_GPIO_A11, + EXYNOS5_GPIO_A12, + EXYNOS5_GPIO_A13, + EXYNOS5_GPIO_A14, + EXYNOS5_GPIO_A15, + EXYNOS5_GPIO_A16, + EXYNOS5_GPIO_A17, + EXYNOS5_GPIO_A20, /* 16 0x10 */ + EXYNOS5_GPIO_A21, + EXYNOS5_GPIO_A22, + EXYNOS5_GPIO_A23, + EXYNOS5_GPIO_A24, + EXYNOS5_GPIO_A25, + EXYNOS5_GPIO_A26, + EXYNOS5_GPIO_A27, + EXYNOS5_GPIO_B00, /* 24 0x18 */ + EXYNOS5_GPIO_B01, + EXYNOS5_GPIO_B02, + EXYNOS5_GPIO_B03, + EXYNOS5_GPIO_B04, + EXYNOS5_GPIO_B05, + EXYNOS5_GPIO_B06, + EXYNOS5_GPIO_B07, + EXYNOS5_GPIO_B10, /* 32 0x20 */ + EXYNOS5_GPIO_B11, + EXYNOS5_GPIO_B12, + EXYNOS5_GPIO_B13, + EXYNOS5_GPIO_B14, + EXYNOS5_GPIO_B15, + EXYNOS5_GPIO_B16, + EXYNOS5_GPIO_B17, + EXYNOS5_GPIO_B20, /* 40 0x28 */ + EXYNOS5_GPIO_B21, + EXYNOS5_GPIO_B22, + EXYNOS5_GPIO_B23, + EXYNOS5_GPIO_B24, + EXYNOS5_GPIO_B25, + EXYNOS5_GPIO_B26, + EXYNOS5_GPIO_B27, + EXYNOS5_GPIO_B30, /* 48 0x39 */ + EXYNOS5_GPIO_B31, + EXYNOS5_GPIO_B32, + EXYNOS5_GPIO_B33, + EXYNOS5_GPIO_B34, + EXYNOS5_GPIO_B35, + EXYNOS5_GPIO_B36, + EXYNOS5_GPIO_B37, + EXYNOS5_GPIO_C00, /* 56 0x38 */ + EXYNOS5_GPIO_C01, + EXYNOS5_GPIO_C02, + EXYNOS5_GPIO_C03, + EXYNOS5_GPIO_C04, + EXYNOS5_GPIO_C05, + EXYNOS5_GPIO_C06, + EXYNOS5_GPIO_C07, + EXYNOS5_GPIO_C10, /* 64 0x40 */ + EXYNOS5_GPIO_C11, + EXYNOS5_GPIO_C12, + EXYNOS5_GPIO_C13, + EXYNOS5_GPIO_C14, + EXYNOS5_GPIO_C15, + EXYNOS5_GPIO_C16, + EXYNOS5_GPIO_C17, + EXYNOS5_GPIO_C20, /* 72 0x48 */ + EXYNOS5_GPIO_C21, + EXYNOS5_GPIO_C22, + EXYNOS5_GPIO_C23, + EXYNOS5_GPIO_C24, + EXYNOS5_GPIO_C25, + EXYNOS5_GPIO_C26, + EXYNOS5_GPIO_C27, + EXYNOS5_GPIO_C30, /* 80 0x50 */ + EXYNOS5_GPIO_C31, + EXYNOS5_GPIO_C32, + EXYNOS5_GPIO_C33, + EXYNOS5_GPIO_C34, + EXYNOS5_GPIO_C35, + EXYNOS5_GPIO_C36, + EXYNOS5_GPIO_C37, + EXYNOS5_GPIO_D00, /* 88 0x58 */ + EXYNOS5_GPIO_D01, + EXYNOS5_GPIO_D02, + EXYNOS5_GPIO_D03, + EXYNOS5_GPIO_D04, + EXYNOS5_GPIO_D05, + EXYNOS5_GPIO_D06, + EXYNOS5_GPIO_D07, + EXYNOS5_GPIO_D10, /* 96 0x60 */ + EXYNOS5_GPIO_D11, + EXYNOS5_GPIO_D12, + EXYNOS5_GPIO_D13, + EXYNOS5_GPIO_D14, + EXYNOS5_GPIO_D15, + EXYNOS5_GPIO_D16, + EXYNOS5_GPIO_D17, + EXYNOS5_GPIO_Y00, /* 104 0x68 */ + EXYNOS5_GPIO_Y01, + EXYNOS5_GPIO_Y02, + EXYNOS5_GPIO_Y03, + EXYNOS5_GPIO_Y04, + EXYNOS5_GPIO_Y05, + EXYNOS5_GPIO_Y06, + EXYNOS5_GPIO_Y07, + EXYNOS5_GPIO_Y10, /* 112 0x70 */ + EXYNOS5_GPIO_Y11, + EXYNOS5_GPIO_Y12, + EXYNOS5_GPIO_Y13, + EXYNOS5_GPIO_Y14, + EXYNOS5_GPIO_Y15, + EXYNOS5_GPIO_Y16, + EXYNOS5_GPIO_Y17, + EXYNOS5_GPIO_Y20, /* 120 0x78 */ + EXYNOS5_GPIO_Y21, + EXYNOS5_GPIO_Y22, + EXYNOS5_GPIO_Y23, + EXYNOS5_GPIO_Y24, + EXYNOS5_GPIO_Y25, + EXYNOS5_GPIO_Y26, + EXYNOS5_GPIO_Y27, + EXYNOS5_GPIO_Y30, /* 128 0x80 */ + EXYNOS5_GPIO_Y31, + EXYNOS5_GPIO_Y32, + EXYNOS5_GPIO_Y33, + EXYNOS5_GPIO_Y34, + EXYNOS5_GPIO_Y35, + EXYNOS5_GPIO_Y36, + EXYNOS5_GPIO_Y37, + EXYNOS5_GPIO_Y40, /* 136 0x88 */ + EXYNOS5_GPIO_Y41, + EXYNOS5_GPIO_Y42, + EXYNOS5_GPIO_Y43, + EXYNOS5_GPIO_Y44, + EXYNOS5_GPIO_Y45, + EXYNOS5_GPIO_Y46, + EXYNOS5_GPIO_Y47, + EXYNOS5_GPIO_Y50, /* 144 0x90 */ + EXYNOS5_GPIO_Y51, + EXYNOS5_GPIO_Y52, + EXYNOS5_GPIO_Y53, + EXYNOS5_GPIO_Y54, + EXYNOS5_GPIO_Y55, + EXYNOS5_GPIO_Y56, + EXYNOS5_GPIO_Y57, + EXYNOS5_GPIO_Y60, /* 152 0x98 */ + EXYNOS5_GPIO_Y61, + EXYNOS5_GPIO_Y62, + EXYNOS5_GPIO_Y63, + EXYNOS5_GPIO_Y64, + EXYNOS5_GPIO_Y65, + EXYNOS5_GPIO_Y66, + EXYNOS5_GPIO_Y67, + + /* GPIO_PART2_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */ + EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1, + EXYNOS5_GPIO_C41, + EXYNOS5_GPIO_C42, + EXYNOS5_GPIO_C43, + EXYNOS5_GPIO_C44, + EXYNOS5_GPIO_C45, + EXYNOS5_GPIO_C46, + EXYNOS5_GPIO_C47, + + /* GPIO_PART3_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */ + EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2, + EXYNOS5_GPIO_X01, + EXYNOS5_GPIO_X02, + EXYNOS5_GPIO_X03, + EXYNOS5_GPIO_X04, + EXYNOS5_GPIO_X05, + EXYNOS5_GPIO_X06, + EXYNOS5_GPIO_X07, + EXYNOS5_GPIO_X10, /* 176 0xb0 */ + EXYNOS5_GPIO_X11, + EXYNOS5_GPIO_X12, + EXYNOS5_GPIO_X13, + EXYNOS5_GPIO_X14, + EXYNOS5_GPIO_X15, + EXYNOS5_GPIO_X16, + EXYNOS5_GPIO_X17, + EXYNOS5_GPIO_X20, /* 184 0xb8 */ + EXYNOS5_GPIO_X21, + EXYNOS5_GPIO_X22, + EXYNOS5_GPIO_X23, + EXYNOS5_GPIO_X24, + EXYNOS5_GPIO_X25, + EXYNOS5_GPIO_X26, + EXYNOS5_GPIO_X27, + EXYNOS5_GPIO_X30, /* 192 0xc0 */ + EXYNOS5_GPIO_X31, + EXYNOS5_GPIO_X32, + EXYNOS5_GPIO_X33, + EXYNOS5_GPIO_X34, + EXYNOS5_GPIO_X35, + EXYNOS5_GPIO_X36, + EXYNOS5_GPIO_X37, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */ + EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3, + EXYNOS5_GPIO_E01, + EXYNOS5_GPIO_E02, + EXYNOS5_GPIO_E03, + EXYNOS5_GPIO_E04, + EXYNOS5_GPIO_E05, + EXYNOS5_GPIO_E06, + EXYNOS5_GPIO_E07, + EXYNOS5_GPIO_E10, /* 208 0xd0 */ + EXYNOS5_GPIO_E11, + EXYNOS5_GPIO_E12, + EXYNOS5_GPIO_E13, + EXYNOS5_GPIO_E14, + EXYNOS5_GPIO_E15, + EXYNOS5_GPIO_E16, + EXYNOS5_GPIO_E17, + EXYNOS5_GPIO_F00, /* 216 0xd8 */ + EXYNOS5_GPIO_F01, + EXYNOS5_GPIO_F02, + EXYNOS5_GPIO_F03, + EXYNOS5_GPIO_F04, + EXYNOS5_GPIO_F05, + EXYNOS5_GPIO_F06, + EXYNOS5_GPIO_F07, + EXYNOS5_GPIO_F10, /* 224 0xe0 */ + EXYNOS5_GPIO_F11, + EXYNOS5_GPIO_F12, + EXYNOS5_GPIO_F13, + EXYNOS5_GPIO_F14, + EXYNOS5_GPIO_F15, + EXYNOS5_GPIO_F16, + EXYNOS5_GPIO_F17, + EXYNOS5_GPIO_G00, /* 232 0xe8 */ + EXYNOS5_GPIO_G01, + EXYNOS5_GPIO_G02, + EXYNOS5_GPIO_G03, + EXYNOS5_GPIO_G04, + EXYNOS5_GPIO_G05, + EXYNOS5_GPIO_G06, + EXYNOS5_GPIO_G07, + EXYNOS5_GPIO_G10, /* 240 0xf0 */ + EXYNOS5_GPIO_G11, + EXYNOS5_GPIO_G12, + EXYNOS5_GPIO_G13, + EXYNOS5_GPIO_G14, + EXYNOS5_GPIO_G15, + EXYNOS5_GPIO_G16, + EXYNOS5_GPIO_G17, + EXYNOS5_GPIO_G20, /* 248 0xf8 */ + EXYNOS5_GPIO_G21, + EXYNOS5_GPIO_G22, + EXYNOS5_GPIO_G23, + EXYNOS5_GPIO_G24, + EXYNOS5_GPIO_G25, + EXYNOS5_GPIO_G26, + EXYNOS5_GPIO_G27, + EXYNOS5_GPIO_H00, /* 256 0x100 */ + EXYNOS5_GPIO_H01, + EXYNOS5_GPIO_H02, + EXYNOS5_GPIO_H03, + EXYNOS5_GPIO_H04, + EXYNOS5_GPIO_H05, + EXYNOS5_GPIO_H06, + EXYNOS5_GPIO_H07, + EXYNOS5_GPIO_H10, /* 264 0x108 */ + EXYNOS5_GPIO_H11, + EXYNOS5_GPIO_H12, + EXYNOS5_GPIO_H13, + EXYNOS5_GPIO_H14, + EXYNOS5_GPIO_H15, + EXYNOS5_GPIO_H16, + EXYNOS5_GPIO_H17, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */ + EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4, + EXYNOS5_GPIO_V01, + EXYNOS5_GPIO_V02, + EXYNOS5_GPIO_V03, + EXYNOS5_GPIO_V04, + EXYNOS5_GPIO_V05, + EXYNOS5_GPIO_V06, + EXYNOS5_GPIO_V07, + EXYNOS5_GPIO_V10, /* 280 0x118 */ + EXYNOS5_GPIO_V11, + EXYNOS5_GPIO_V12, + EXYNOS5_GPIO_V13, + EXYNOS5_GPIO_V14, + EXYNOS5_GPIO_V15, + EXYNOS5_GPIO_V16, + EXYNOS5_GPIO_V17, + + /* GPIO_PART5_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */ + EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5, + EXYNOS5_GPIO_V21, + EXYNOS5_GPIO_V22, + EXYNOS5_GPIO_V23, + EXYNOS5_GPIO_V24, + EXYNOS5_GPIO_V25, + EXYNOS5_GPIO_V26, + EXYNOS5_GPIO_V27, + EXYNOS5_GPIO_V30, /* 296 0x128 */ + EXYNOS5_GPIO_V31, + EXYNOS5_GPIO_V32, + EXYNOS5_GPIO_V33, + EXYNOS5_GPIO_V34, + EXYNOS5_GPIO_V35, + EXYNOS5_GPIO_V36, + EXYNOS5_GPIO_V37, + + /* GPIO_PART6_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */ + EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6, + EXYNOS5_GPIO_V41, + EXYNOS5_GPIO_V42, + EXYNOS5_GPIO_V43, + EXYNOS5_GPIO_V44, + EXYNOS5_GPIO_V45, + EXYNOS5_GPIO_V46, + EXYNOS5_GPIO_V47, + + /* GPIO_PART7_STARTS */ /* 312 0x138 */ + EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z1, + EXYNOS5_GPIO_Z2, + EXYNOS5_GPIO_Z3, + EXYNOS5_GPIO_Z4, + EXYNOS5_GPIO_Z5, + EXYNOS5_GPIO_Z6, + EXYNOS5_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part4 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +enum exynos5420_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5420_GPIO_A00, /* 0 */ + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, /* 8 */ + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, /* 16 0x10 */ + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, /* 24 0x18 */ + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, /* 32 0x20 */ + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, /* 40 0x28 */ + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, /* 48 0x30 */ + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, /* 56 0x38 */ + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, /* 64 0x40 */ + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + /* GPIO PART 2 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ + EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y71, + EXYNOS5420_GPIO_Y72, + EXYNOS5420_GPIO_Y73, + EXYNOS5420_GPIO_Y74, + EXYNOS5420_GPIO_Y75, + EXYNOS5420_GPIO_Y76, + EXYNOS5420_GPIO_Y77, + + /* GPIO PART 3 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ + EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X01, + EXYNOS5420_GPIO_X02, + EXYNOS5420_GPIO_X03, + EXYNOS5420_GPIO_X04, + EXYNOS5420_GPIO_X05, + EXYNOS5420_GPIO_X06, + EXYNOS5420_GPIO_X07, + EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X11, + EXYNOS5420_GPIO_X12, + EXYNOS5420_GPIO_X13, + EXYNOS5420_GPIO_X14, + EXYNOS5420_GPIO_X15, + EXYNOS5420_GPIO_X16, + EXYNOS5420_GPIO_X17, + EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X21, + EXYNOS5420_GPIO_X22, + EXYNOS5420_GPIO_X23, + EXYNOS5420_GPIO_X24, + EXYNOS5420_GPIO_X25, + EXYNOS5420_GPIO_X26, + EXYNOS5420_GPIO_X27, + EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X31, + EXYNOS5420_GPIO_X32, + EXYNOS5420_GPIO_X33, + EXYNOS5420_GPIO_X34, + EXYNOS5420_GPIO_X35, + EXYNOS5420_GPIO_X36, + EXYNOS5420_GPIO_X37, + + /* GPIO PART 4 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_C01, + EXYNOS5420_GPIO_C02, + EXYNOS5420_GPIO_C03, + EXYNOS5420_GPIO_C04, + EXYNOS5420_GPIO_C05, + EXYNOS5420_GPIO_C06, + EXYNOS5420_GPIO_C07, + EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C11, + EXYNOS5420_GPIO_C12, + EXYNOS5420_GPIO_C13, + EXYNOS5420_GPIO_C14, + EXYNOS5420_GPIO_C15, + EXYNOS5420_GPIO_C16, + EXYNOS5420_GPIO_C17, + EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C21, + EXYNOS5420_GPIO_C22, + EXYNOS5420_GPIO_C23, + EXYNOS5420_GPIO_C24, + EXYNOS5420_GPIO_C25, + EXYNOS5420_GPIO_C26, + EXYNOS5420_GPIO_C27, + EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C31, + EXYNOS5420_GPIO_C32, + EXYNOS5420_GPIO_C33, + EXYNOS5420_GPIO_C34, + EXYNOS5420_GPIO_C35, + EXYNOS5420_GPIO_C36, + EXYNOS5420_GPIO_C37, + EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C41, + EXYNOS5420_GPIO_C42, + EXYNOS5420_GPIO_C43, + EXYNOS5420_GPIO_C44, + EXYNOS5420_GPIO_C45, + EXYNOS5420_GPIO_C46, + EXYNOS5420_GPIO_C47, + EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D11, + EXYNOS5420_GPIO_D12, + EXYNOS5420_GPIO_D13, + EXYNOS5420_GPIO_D14, + EXYNOS5420_GPIO_D15, + EXYNOS5420_GPIO_D16, + EXYNOS5420_GPIO_D17, + EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y01, + EXYNOS5420_GPIO_Y02, + EXYNOS5420_GPIO_Y03, + EXYNOS5420_GPIO_Y04, + EXYNOS5420_GPIO_Y05, + EXYNOS5420_GPIO_Y06, + EXYNOS5420_GPIO_Y07, + EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y11, + EXYNOS5420_GPIO_Y12, + EXYNOS5420_GPIO_Y13, + EXYNOS5420_GPIO_Y14, + EXYNOS5420_GPIO_Y15, + EXYNOS5420_GPIO_Y16, + EXYNOS5420_GPIO_Y17, + EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y21, + EXYNOS5420_GPIO_Y22, + EXYNOS5420_GPIO_Y23, + EXYNOS5420_GPIO_Y24, + EXYNOS5420_GPIO_Y25, + EXYNOS5420_GPIO_Y26, + EXYNOS5420_GPIO_Y27, + EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y31, + EXYNOS5420_GPIO_Y32, + EXYNOS5420_GPIO_Y33, + EXYNOS5420_GPIO_Y34, + EXYNOS5420_GPIO_Y35, + EXYNOS5420_GPIO_Y36, + EXYNOS5420_GPIO_Y37, + EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y41, + EXYNOS5420_GPIO_Y42, + EXYNOS5420_GPIO_Y43, + EXYNOS5420_GPIO_Y44, + EXYNOS5420_GPIO_Y45, + EXYNOS5420_GPIO_Y46, + EXYNOS5420_GPIO_Y47, + EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y51, + EXYNOS5420_GPIO_Y52, + EXYNOS5420_GPIO_Y53, + EXYNOS5420_GPIO_Y54, + EXYNOS5420_GPIO_Y55, + EXYNOS5420_GPIO_Y56, + EXYNOS5420_GPIO_Y57, + EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y61, + EXYNOS5420_GPIO_Y62, + EXYNOS5420_GPIO_Y63, + EXYNOS5420_GPIO_Y64, + EXYNOS5420_GPIO_Y65, + EXYNOS5420_GPIO_Y66, + EXYNOS5420_GPIO_Y67, + + /* GPIO_PART5_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_E01, + EXYNOS5420_GPIO_E02, + EXYNOS5420_GPIO_E03, + EXYNOS5420_GPIO_E04, + EXYNOS5420_GPIO_E05, + EXYNOS5420_GPIO_E06, + EXYNOS5420_GPIO_E07, + EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E11, + EXYNOS5420_GPIO_E12, + EXYNOS5420_GPIO_E13, + EXYNOS5420_GPIO_E14, + EXYNOS5420_GPIO_E15, + EXYNOS5420_GPIO_E16, + EXYNOS5420_GPIO_E17, + EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F01, + EXYNOS5420_GPIO_F02, + EXYNOS5420_GPIO_F03, + EXYNOS5420_GPIO_F04, + EXYNOS5420_GPIO_F05, + EXYNOS5420_GPIO_F06, + EXYNOS5420_GPIO_F07, + EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F11, + EXYNOS5420_GPIO_F12, + EXYNOS5420_GPIO_F13, + EXYNOS5420_GPIO_F14, + EXYNOS5420_GPIO_F15, + EXYNOS5420_GPIO_F16, + EXYNOS5420_GPIO_F17, + EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G01, + EXYNOS5420_GPIO_G02, + EXYNOS5420_GPIO_G03, + EXYNOS5420_GPIO_G04, + EXYNOS5420_GPIO_G05, + EXYNOS5420_GPIO_G06, + EXYNOS5420_GPIO_G07, + EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G11, + EXYNOS5420_GPIO_G12, + EXYNOS5420_GPIO_G13, + EXYNOS5420_GPIO_G14, + EXYNOS5420_GPIO_G15, + EXYNOS5420_GPIO_G16, + EXYNOS5420_GPIO_G17, + EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G21, + EXYNOS5420_GPIO_G22, + EXYNOS5420_GPIO_G23, + EXYNOS5420_GPIO_G24, + EXYNOS5420_GPIO_G25, + EXYNOS5420_GPIO_G26, + EXYNOS5420_GPIO_G27, + EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J41, + EXYNOS5420_GPIO_J42, + EXYNOS5420_GPIO_J43, + EXYNOS5420_GPIO_J44, + EXYNOS5420_GPIO_J45, + EXYNOS5420_GPIO_J46, + EXYNOS5420_GPIO_J47, + + /* GPIO_PART6_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_Z1, + EXYNOS5420_GPIO_Z2, + EXYNOS5420_GPIO_Z3, + EXYNOS5420_GPIO_Z4, + EXYNOS5420_GPIO_Z5, + EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT }; -struct exynos5420_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank b4; - struct s5p_gpio_bank h0; +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ }; -struct exynos5420_gpio_part2 { - struct s5p_gpio_bank y7; /* 0x1340_0000 */ - struct s5p_gpio_bank res[0x5f]; /* */ - struct s5p_gpio_bank x0; /* 0x1340_0C00 */ - struct s5p_gpio_bank x1; /* 0x1340_0C20 */ - struct s5p_gpio_bank x2; /* 0x1340_0C40 */ - struct s5p_gpio_bank x3; /* 0x1340_0C60 */ +#define EXYNOS4_GPIO_NUM_PARTS 3 +static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { + { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part3 { - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; +#define EXYNOS4X12_GPIO_NUM_PARTS 4 +static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { + { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, + { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part4 { - struct s5p_gpio_bank e0; /* 0x1400_0000 */ - struct s5p_gpio_bank e1; /* 0x1400_0020 */ - struct s5p_gpio_bank f0; /* 0x1400_0040 */ - struct s5p_gpio_bank f1; /* 0x1400_0060 */ - struct s5p_gpio_bank g0; /* 0x1400_0080 */ - struct s5p_gpio_bank g1; /* 0x1400_00A0 */ - struct s5p_gpio_bank g2; /* 0x1400_00C0 */ - struct s5p_gpio_bank j4; /* 0x1400_00E0 */ +#define EXYNOS5_GPIO_NUM_PARTS 8 +static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { + { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 }, + { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 }, + { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part5 { - struct s5p_gpio_bank z0; /* 0x0386_0000 */ +#define EXYNOS5420_GPIO_NUM_PARTS 6 +static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { + { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; -struct exynos5_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x3]; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank res2[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; +static inline struct gpio_info *get_gpio_data(void) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_gpio_data; + else + return exynos5_gpio_data; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return exynos4x12_gpio_data; + else + return exynos4_gpio_data; + } + + return NULL; +} + +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return EXYNOS5420_GPIO_NUM_PARTS; + else + return EXYNOS5_GPIO_NUM_PARTS; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return EXYNOS4X12_GPIO_NUM_PARTS; + else + return EXYNOS4_GPIO_NUM_PARTS; + } + + return 0; +} + +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p]<bank><set><bit>, where + * p is optional + * <bank> - a single character bank name, as defined by the SOC + * <set> - a single digit set number + * <bit> - bit number within the set (in 0..7 range). + * + * <set><bit> essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + unsigned int bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ }; -struct exynos5_gpio_part2 { - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table exynos4_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0), + { 0 } }; -struct exynos5_gpio_part3 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +static const struct gpio_name_num_table exynos4x12_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0), + GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0), + { 0 } }; -struct exynos5_gpio_part4 { - struct s5p_gpio_bank z; +static const struct gpio_name_num_table exynos5_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0), + GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0), + { 0 } }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +static const struct gpio_name_num_table exynos5420_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), + { 0 } +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) - -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) - -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) - -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) - -#define EXYNOS4_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4_gpio_part##part *) \ - EXYNOS4_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ - EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4X12_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5420_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define exynos4_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos4x12_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5420_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5420_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -static inline unsigned int s5p_gpio_base(int gpio) -{ - unsigned gpio_part = S5P_GPIO_GET_PART(gpio); - - switch (gpio_part) { - case 1: - return samsung_get_base_gpio_part1(); - case 2: - return samsung_get_base_gpio_part2(); - case 3: - return samsung_get_base_gpio_part3(); - case 4: - return samsung_get_base_gpio_part4(); - default: - return 0; - } -} +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x3 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index a17f828342..3dffa4a396 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -161,6 +161,126 @@ struct aips_regs { u32 mpr_0_7; u32 mpr_8_15; }; +/* LCD controller registers */ +struct lcdc_regs { + u32 lssar; /* Screen Start Address */ + u32 lsr; /* Size */ + u32 lvpwr; /* Virtual Page Width */ + u32 lcpr; /* Cursor Position */ + u32 lcwhb; /* Cursor Width Height and Blink */ + u32 lccmr; /* Color Cursor Mapping */ + u32 lpcr; /* Panel Configuration */ + u32 lhcr; /* Horizontal Configuration */ + u32 lvcr; /* Vertical Configuration */ + u32 lpor; /* Panning Offset */ + u32 lscr; /* Sharp Configuration */ + u32 lpccr; /* PWM Contrast Control */ + u32 ldcr; /* DMA Control */ + u32 lrmcr; /* Refresh Mode Control */ + u32 licr; /* Interrupt Configuration */ + u32 lier; /* Interrupt Enable */ + u32 lisr; /* Interrupt Status */ + u32 res0[3]; + u32 lgwsar; /* Graphic Window Start Address */ + u32 lgwsr; /* Graphic Window Size */ + u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ + u32 lgwpor; /* Graphic Window Panning Offset */ + u32 lgwpr; /* Graphic Window Position */ + u32 lgwcr; /* Graphic Window Control */ + u32 lgwdcr; /* Graphic Window DMA Control */ + u32 res1[5]; + u32 lauscr; /* AUS Mode Control */ + u32 lausccr; /* AUS mode Cursor Control */ + u32 res2[31 + 64*7]; + u32 bglut; /* Background Lookup Table */ + u32 gwlut; /* Graphic Window Lookup Table */ +}; + +/* Wireless External Interface Module Registers */ +struct weim_regs { + u32 cscr0u; /* Chip Select 0 Upper Register */ + u32 cscr0l; /* Chip Select 0 Lower Register */ + u32 cscr0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cscr1u; /* Chip Select 1 Upper Register */ + u32 cscr1l; /* Chip Select 1 Lower Register */ + u32 cscr1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cscr2u; /* Chip Select 2 Upper Register */ + u32 cscr2l; /* Chip Select 2 Lower Register */ + u32 cscr2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cscr3u; /* Chip Select 3 Upper Register */ + u32 cscr3l; /* Chip Select 3 Lower Register */ + u32 cscr3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cscr4u; /* Chip Select 4 Upper Register */ + u32 cscr4l; /* Chip Select 4 Lower Register */ + u32 cscr4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cscr5u; /* Chip Select 5 Upper Register */ + u32 cscr5l; /* Chip Select 5 Lower Register */ + u32 cscr5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 wcr; /* WEIM Configuration Register */ +}; + +/* Multi-Master Memory Interface */ +struct m3if_regs { + u32 ctl; /* Control Register */ + u32 wcfg0; /* Watermark Configuration Register 0 */ + u32 wcfg1; /* Watermark Configuration Register1 */ + u32 wcfg2; /* Watermark Configuration Register2 */ + u32 wcfg3; /* Watermark Configuration Register 3 */ + u32 wcfg4; /* Watermark Configuration Register 4 */ + u32 wcfg5; /* Watermark Configuration Register 5 */ + u32 wcfg6; /* Watermark Configuration Register 6 */ + u32 wcfg7; /* Watermark Configuration Register 7 */ + u32 wcsr; /* Watermark Control and Status Register */ + u32 scfg0; /* Snooping Configuration Register 0 */ + u32 scfg1; /* Snooping Configuration Register 1 */ + u32 scfg2; /* Snooping Configuration Register 2 */ + u32 ssr0; /* Snooping Status Register 0 */ + u32 ssr1; /* Snooping Status Register 1 */ + u32 res0; + u32 mlwe0; /* Master Lock WEIM CS0 Register */ + u32 mlwe1; /* Master Lock WEIM CS1 Register */ + u32 mlwe2; /* Master Lock WEIM CS2 Register */ + u32 mlwe3; /* Master Lock WEIM CS3 Register */ + u32 mlwe4; /* Master Lock WEIM CS4 Register */ + u32 mlwe5; /* Master Lock WEIM CS5 Register */ +}; + +/* Pulse width modulation */ +struct pwm_regs { + u32 cr; /* Control Register */ + u32 sr; /* Status Register */ + u32 ir; /* Interrupt Register */ + u32 sar; /* Sample Register */ + u32 pr; /* Period Register */ + u32 cnr; /* Counter Register */ +}; + +/* Enhanced Periodic Interrupt Timer */ +struct epit_regs { + u32 cr; /* Control register */ + u32 sr; /* Status register */ + u32 lr; /* Load register */ + u32 cmpr; /* Compare register */ + u32 cnr; /* Counter register */ +}; + +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +}; #endif @@ -289,6 +409,8 @@ struct aips_regs { #define CCM_PERCLK_MASK 0x3f #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +#define CCM_CRDR_BT_UART_SRC_MASK 7 /* ESDRAM Controller register bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) @@ -345,12 +467,65 @@ struct aips_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA +/* MAX bits */ +#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) + +/* M3IF bits */ +#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) + +/* WEIM bits */ +/* 13 fields of the upper CS control register */ +#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ + (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ + (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + /* Names used in GPIO driver */ #define GPIO1_BASE_ADDR IMX_GPIO1_BASE #define GPIO2_BASE_ADDR IMX_GPIO2_BASE #define GPIO3_BASE_ADDR IMX_GPIO3_BASE #define GPIO4_BASE_ADDR IMX_GPIO4_BASE +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 5f9c90ad87..045ccc4512 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -10,6 +10,10 @@ #include <asm/imx-common/iomux-v3.h> enum { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 2dfe4efb4b..30d9de2764 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -322,6 +322,9 @@ #define V_SCLK V_OSCK +/* CKO buffer control */ +#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) + /* AUXCLKx reg fields */ #define AUXCLK_ENABLE_MASK (1 << 8) #define AUXCLK_SRCSELECT_SHIFT 1 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 19fdecec01..e35a81a8af 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -50,6 +50,7 @@ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) +#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) /* General Purpose Timers */ #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h new file mode 100644 index 0000000000..463654efd3 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __EHCI_RMOBILE_H__ +#define __EHCI_RMOBILE_H__ + +/* Register offset */ +#define OHCI_OFFSET 0x00 +#define OHCI_SIZE 0x1000 +#define EHCI_OFFSET 0x1000 +#define EHCI_SIZE 0x1000 + +#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) + +/* USBCTR */ +#define DIRPD (1 << 8) +#define PLL_RST (1 << 2) +#define PCICLK_MASK (1 << 1) +#define USBH_RST (1 << 0) + +/* CMND_STS */ +#define SERREN (1 << 8) +#define PERREN (1 << 6) +#define MASTEREN (1 << 2) +#define MEMEN (1 << 1) + +/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ +#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) + +/* AHBPCI_WIN1_CTR */ +#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define AHB_CFG_AHBPCI 0x40000000 +#define AHB_CFG_HOST 0x80000000 + +/* AHBPCI_WIN2_CTR */ +#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) + +/* PCI_INT_ENABLE */ +#define USBH_PMEEN (1 << 19) +#define USBH_INTBEN (1 << 17) +#define USBH_INTAEN (1 << 16) + +/* AHB_BUS_CTR */ +#define SMODE_READY_CTR (1 << 17) +#define SMODE_READ_BURST (1 << 16) +#define MMODE_HBUSREQ (1 << 7) +#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) +#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) +#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) +#define MMODE_WR_INCR (1 << 2) +#define MMODE_BYTE_BURST (1 << 1) +#define MMODE_HTRANS (1 << 0) + +/* PCI_ARBITER_CTR */ +#define PCIBUS_PARK_TIMER 0x00FF0000 +#define PCIBUS_PARK_TIMER_SET 0x00070000 +#define PCIBP_MODE (1 << 12) +#define PCIREQ7 (1 << 7) +#define PCIREQ6 (1 << 6) +#define PCIREQ5 (1 << 5) +#define PCIREQ4 (1 << 4) +#define PCIREQ3 (1 << 3) +#define PCIREQ2 (1 << 2) +#define PCIREQ1 (1 << 1) +#define PCIREQ0 (1 << 0) + +#define SMSTPCR7 0xE615014C +#define SMSTPCR703 (1 << 3) + +/* Init AHB master and slave functions of the host logic */ +#define AHB_BUS_CTR_INIT \ + (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ + MMODE_BYTE_BURST | MMODE_HTRANS) + +#define USBCTR_WIN_SIZE_1GB 0x800 + +/* PCI Configuration Registers */ +#define PCI_CONF_OHCI_OFFSET 0x10000 +#define PCI_CONF_EHCI_OFFSET 0x10100 +struct ahb_pciconf { + u32 vid_did; + u32 cmnd_sts; + u32 rev; + u32 cache_line; + u32 basead; +}; + +/* PCI Configuration Registers for AHB-PCI Bridge Registers */ +#define PCI_CONF_AHBPCI_OFFSET 0x10000 +struct ahbconf_pci_bridge { + u32 vid_did; /* 0x00 */ + u32 cmnd_sts; + u32 revid_cc; + u32 cls_lt_ht_bist; + u32 basead; /* 0x10 */ + u32 win1_basead; + u32 win2_basead; + u32 dummy0[5]; + u32 ssvdi_ssid; /* 0x2C */ + u32 dummy1[4]; + u32 intr_line_pin; +}; + +/* AHB-PCI Bridge PCI Communication Registers */ +#define AHBPCI_OFFSET 0x10800 +struct ahbcom_pci_bridge { + u32 pciahb_win1_ctr; /* 0x00 */ + u32 pciahb_win2_ctr; + u32 pciahb_dct_ctr; + u32 dummy0; + u32 ahbpci_win1_ctr; /* 0x10 */ + u32 ahbpci_win2_ctr; + u32 dummy1; + u32 ahbpci_dct_ctr; + u32 pci_int_enable; /* 0x20 */ + u32 pci_int_status; + u32 dummy2[2]; + u32 ahb_bus_ctr; /* 0x30 */ + u32 usbctr; + u32 dummy3[2]; + u32 pci_arbiter_ctr; /* 0x40 */ + u32 dummy4; + u32 pci_unit_rev; /* 0x48 */ +}; + +struct rmobile_ehci_reg { + u32 hciversion; /* hciversion/caplength */ + u32 hcsparams; /* hcsparams */ + u32 hccparams; /* hccparams */ + u32 hcsp_portroute; /* hcsp_portroute */ + u32 usbcmd; /* usbcmd */ + u32 usbsts; /* usbsts */ + u32 usbintr; /* usbintr */ + u32 frindex; /* frindex */ + u32 ctrldssegment; /* ctrldssegment */ + u32 periodiclistbase; /* periodiclistbase */ + u32 asynclistaddr; /* asynclistaddr */ + u32 dummy[9]; + u32 configflag; /* configflag */ + u32 portsc; /* portsc */ +}; + +#endif /* __EHCI_RMOBILE_H__ */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index da8df74a10..d5dbc22c18 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -19,170 +19,830 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct s5pc100_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c; - struct s5p_gpio_bank d; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank l3; - struct s5p_gpio_bank l4; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum s5pc100_gpio_pin { + S5PC100_GPIO_A00, + S5PC100_GPIO_A01, + S5PC100_GPIO_A02, + S5PC100_GPIO_A03, + S5PC100_GPIO_A04, + S5PC100_GPIO_A05, + S5PC100_GPIO_A06, + S5PC100_GPIO_A07, + S5PC100_GPIO_A10, + S5PC100_GPIO_A11, + S5PC100_GPIO_A12, + S5PC100_GPIO_A13, + S5PC100_GPIO_A14, + S5PC100_GPIO_A15, + S5PC100_GPIO_A16, + S5PC100_GPIO_A17, + S5PC100_GPIO_B0, + S5PC100_GPIO_B1, + S5PC100_GPIO_B2, + S5PC100_GPIO_B3, + S5PC100_GPIO_B4, + S5PC100_GPIO_B5, + S5PC100_GPIO_B6, + S5PC100_GPIO_B7, + S5PC100_GPIO_C0, + S5PC100_GPIO_C1, + S5PC100_GPIO_C2, + S5PC100_GPIO_C3, + S5PC100_GPIO_C4, + S5PC100_GPIO_C5, + S5PC100_GPIO_C6, + S5PC100_GPIO_C7, + S5PC100_GPIO_D0, + S5PC100_GPIO_D1, + S5PC100_GPIO_D2, + S5PC100_GPIO_D3, + S5PC100_GPIO_D4, + S5PC100_GPIO_D5, + S5PC100_GPIO_D6, + S5PC100_GPIO_D7, + S5PC100_GPIO_E00, + S5PC100_GPIO_E01, + S5PC100_GPIO_E02, + S5PC100_GPIO_E03, + S5PC100_GPIO_E04, + S5PC100_GPIO_E05, + S5PC100_GPIO_E06, + S5PC100_GPIO_E07, + S5PC100_GPIO_E10, + S5PC100_GPIO_E11, + S5PC100_GPIO_E12, + S5PC100_GPIO_E13, + S5PC100_GPIO_E14, + S5PC100_GPIO_E15, + S5PC100_GPIO_E16, + S5PC100_GPIO_E17, + S5PC100_GPIO_F00, + S5PC100_GPIO_F01, + S5PC100_GPIO_F02, + S5PC100_GPIO_F03, + S5PC100_GPIO_F04, + S5PC100_GPIO_F05, + S5PC100_GPIO_F06, + S5PC100_GPIO_F07, + S5PC100_GPIO_F10, + S5PC100_GPIO_F11, + S5PC100_GPIO_F12, + S5PC100_GPIO_F13, + S5PC100_GPIO_F14, + S5PC100_GPIO_F15, + S5PC100_GPIO_F16, + S5PC100_GPIO_F17, + S5PC100_GPIO_F20, + S5PC100_GPIO_F21, + S5PC100_GPIO_F22, + S5PC100_GPIO_F23, + S5PC100_GPIO_F24, + S5PC100_GPIO_F25, + S5PC100_GPIO_F26, + S5PC100_GPIO_F27, + S5PC100_GPIO_F30, + S5PC100_GPIO_F31, + S5PC100_GPIO_F32, + S5PC100_GPIO_F33, + S5PC100_GPIO_F34, + S5PC100_GPIO_F35, + S5PC100_GPIO_F36, + S5PC100_GPIO_F37, + S5PC100_GPIO_G00, + S5PC100_GPIO_G01, + S5PC100_GPIO_G02, + S5PC100_GPIO_G03, + S5PC100_GPIO_G04, + S5PC100_GPIO_G05, + S5PC100_GPIO_G06, + S5PC100_GPIO_G07, + S5PC100_GPIO_G10, + S5PC100_GPIO_G11, + S5PC100_GPIO_G12, + S5PC100_GPIO_G13, + S5PC100_GPIO_G14, + S5PC100_GPIO_G15, + S5PC100_GPIO_G16, + S5PC100_GPIO_G17, + S5PC100_GPIO_G20, + S5PC100_GPIO_G21, + S5PC100_GPIO_G22, + S5PC100_GPIO_G23, + S5PC100_GPIO_G24, + S5PC100_GPIO_G25, + S5PC100_GPIO_G26, + S5PC100_GPIO_G27, + S5PC100_GPIO_G30, + S5PC100_GPIO_G31, + S5PC100_GPIO_G32, + S5PC100_GPIO_G33, + S5PC100_GPIO_G34, + S5PC100_GPIO_G35, + S5PC100_GPIO_G36, + S5PC100_GPIO_G37, + S5PC100_GPIO_I0, + S5PC100_GPIO_I1, + S5PC100_GPIO_I2, + S5PC100_GPIO_I3, + S5PC100_GPIO_I4, + S5PC100_GPIO_I5, + S5PC100_GPIO_I6, + S5PC100_GPIO_I7, + S5PC100_GPIO_J00, + S5PC100_GPIO_J01, + S5PC100_GPIO_J02, + S5PC100_GPIO_J03, + S5PC100_GPIO_J04, + S5PC100_GPIO_J05, + S5PC100_GPIO_J06, + S5PC100_GPIO_J07, + S5PC100_GPIO_J10, + S5PC100_GPIO_J11, + S5PC100_GPIO_J12, + S5PC100_GPIO_J13, + S5PC100_GPIO_J14, + S5PC100_GPIO_J15, + S5PC100_GPIO_J16, + S5PC100_GPIO_J17, + S5PC100_GPIO_J20, + S5PC100_GPIO_J21, + S5PC100_GPIO_J22, + S5PC100_GPIO_J23, + S5PC100_GPIO_J24, + S5PC100_GPIO_J25, + S5PC100_GPIO_J26, + S5PC100_GPIO_J27, + S5PC100_GPIO_J30, + S5PC100_GPIO_J31, + S5PC100_GPIO_J32, + S5PC100_GPIO_J33, + S5PC100_GPIO_J34, + S5PC100_GPIO_J35, + S5PC100_GPIO_J36, + S5PC100_GPIO_J37, + S5PC100_GPIO_J40, + S5PC100_GPIO_J41, + S5PC100_GPIO_J42, + S5PC100_GPIO_J43, + S5PC100_GPIO_J44, + S5PC100_GPIO_J45, + S5PC100_GPIO_J46, + S5PC100_GPIO_J47, + S5PC100_GPIO_K00, + S5PC100_GPIO_K01, + S5PC100_GPIO_K02, + S5PC100_GPIO_K03, + S5PC100_GPIO_K04, + S5PC100_GPIO_K05, + S5PC100_GPIO_K06, + S5PC100_GPIO_K07, + S5PC100_GPIO_K10, + S5PC100_GPIO_K11, + S5PC100_GPIO_K12, + S5PC100_GPIO_K13, + S5PC100_GPIO_K14, + S5PC100_GPIO_K15, + S5PC100_GPIO_K16, + S5PC100_GPIO_K17, + S5PC100_GPIO_K20, + S5PC100_GPIO_K21, + S5PC100_GPIO_K22, + S5PC100_GPIO_K23, + S5PC100_GPIO_K24, + S5PC100_GPIO_K25, + S5PC100_GPIO_K26, + S5PC100_GPIO_K27, + S5PC100_GPIO_K30, + S5PC100_GPIO_K31, + S5PC100_GPIO_K32, + S5PC100_GPIO_K33, + S5PC100_GPIO_K34, + S5PC100_GPIO_K35, + S5PC100_GPIO_K36, + S5PC100_GPIO_K37, + S5PC100_GPIO_L00, + S5PC100_GPIO_L01, + S5PC100_GPIO_L02, + S5PC100_GPIO_L03, + S5PC100_GPIO_L04, + S5PC100_GPIO_L05, + S5PC100_GPIO_L06, + S5PC100_GPIO_L07, + S5PC100_GPIO_L10, + S5PC100_GPIO_L11, + S5PC100_GPIO_L12, + S5PC100_GPIO_L13, + S5PC100_GPIO_L14, + S5PC100_GPIO_L15, + S5PC100_GPIO_L16, + S5PC100_GPIO_L17, + S5PC100_GPIO_L20, + S5PC100_GPIO_L21, + S5PC100_GPIO_L22, + S5PC100_GPIO_L23, + S5PC100_GPIO_L24, + S5PC100_GPIO_L25, + S5PC100_GPIO_L26, + S5PC100_GPIO_L27, + S5PC100_GPIO_L30, + S5PC100_GPIO_L31, + S5PC100_GPIO_L32, + S5PC100_GPIO_L33, + S5PC100_GPIO_L34, + S5PC100_GPIO_L35, + S5PC100_GPIO_L36, + S5PC100_GPIO_L37, + S5PC100_GPIO_L40, + S5PC100_GPIO_L41, + S5PC100_GPIO_L42, + S5PC100_GPIO_L43, + S5PC100_GPIO_L44, + S5PC100_GPIO_L45, + S5PC100_GPIO_L46, + S5PC100_GPIO_L47, + S5PC100_GPIO_H00, + S5PC100_GPIO_H01, + S5PC100_GPIO_H02, + S5PC100_GPIO_H03, + S5PC100_GPIO_H04, + S5PC100_GPIO_H05, + S5PC100_GPIO_H06, + S5PC100_GPIO_H07, + S5PC100_GPIO_H10, + S5PC100_GPIO_H11, + S5PC100_GPIO_H12, + S5PC100_GPIO_H13, + S5PC100_GPIO_H14, + S5PC100_GPIO_H15, + S5PC100_GPIO_H16, + S5PC100_GPIO_H17, + S5PC100_GPIO_H20, + S5PC100_GPIO_H21, + S5PC100_GPIO_H22, + S5PC100_GPIO_H23, + S5PC100_GPIO_H24, + S5PC100_GPIO_H25, + S5PC100_GPIO_H26, + S5PC100_GPIO_H27, + S5PC100_GPIO_H30, + S5PC100_GPIO_H31, + S5PC100_GPIO_H32, + S5PC100_GPIO_H33, + S5PC100_GPIO_H34, + S5PC100_GPIO_H35, + S5PC100_GPIO_H36, + S5PC100_GPIO_H37, + + S5PC100_GPIO_MAX_PORT }; -struct s5pc110_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank mp0_1; - struct s5p_gpio_bank mp0_2; - struct s5p_gpio_bank mp0_3; - struct s5p_gpio_bank mp0_4; - struct s5p_gpio_bank mp0_5; - struct s5p_gpio_bank mp0_6; - struct s5p_gpio_bank mp0_7; - struct s5p_gpio_bank mp1_0; - struct s5p_gpio_bank mp1_1; - struct s5p_gpio_bank mp1_2; - struct s5p_gpio_bank mp1_3; - struct s5p_gpio_bank mp1_4; - struct s5p_gpio_bank mp1_5; - struct s5p_gpio_bank mp1_6; - struct s5p_gpio_bank mp1_7; - struct s5p_gpio_bank mp1_8; - struct s5p_gpio_bank mp2_0; - struct s5p_gpio_bank mp2_1; - struct s5p_gpio_bank mp2_2; - struct s5p_gpio_bank mp2_3; - struct s5p_gpio_bank mp2_4; - struct s5p_gpio_bank mp2_5; - struct s5p_gpio_bank mp2_6; - struct s5p_gpio_bank mp2_7; - struct s5p_gpio_bank mp2_8; - struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +enum s5pc110_gpio_pin { + S5PC110_GPIO_A00, + S5PC110_GPIO_A01, + S5PC110_GPIO_A02, + S5PC110_GPIO_A03, + S5PC110_GPIO_A04, + S5PC110_GPIO_A05, + S5PC110_GPIO_A06, + S5PC110_GPIO_A07, + S5PC110_GPIO_A10, + S5PC110_GPIO_A11, + S5PC110_GPIO_A12, + S5PC110_GPIO_A13, + S5PC110_GPIO_A14, + S5PC110_GPIO_A15, + S5PC110_GPIO_A16, + S5PC110_GPIO_A17, + S5PC110_GPIO_B0, + S5PC110_GPIO_B1, + S5PC110_GPIO_B2, + S5PC110_GPIO_B3, + S5PC110_GPIO_B4, + S5PC110_GPIO_B5, + S5PC110_GPIO_B6, + S5PC110_GPIO_B7, + S5PC110_GPIO_C00, + S5PC110_GPIO_C01, + S5PC110_GPIO_C02, + S5PC110_GPIO_C03, + S5PC110_GPIO_C04, + S5PC110_GPIO_C05, + S5PC110_GPIO_C06, + S5PC110_GPIO_C07, + S5PC110_GPIO_C10, + S5PC110_GPIO_C11, + S5PC110_GPIO_C12, + S5PC110_GPIO_C13, + S5PC110_GPIO_C14, + S5PC110_GPIO_C15, + S5PC110_GPIO_C16, + S5PC110_GPIO_C17, + S5PC110_GPIO_D00, + S5PC110_GPIO_D01, + S5PC110_GPIO_D02, + S5PC110_GPIO_D03, + S5PC110_GPIO_D04, + S5PC110_GPIO_D05, + S5PC110_GPIO_D06, + S5PC110_GPIO_D07, + S5PC110_GPIO_D10, + S5PC110_GPIO_D11, + S5PC110_GPIO_D12, + S5PC110_GPIO_D13, + S5PC110_GPIO_D14, + S5PC110_GPIO_D15, + S5PC110_GPIO_D16, + S5PC110_GPIO_D17, + S5PC110_GPIO_E00, + S5PC110_GPIO_E01, + S5PC110_GPIO_E02, + S5PC110_GPIO_E03, + S5PC110_GPIO_E04, + S5PC110_GPIO_E05, + S5PC110_GPIO_E06, + S5PC110_GPIO_E07, + S5PC110_GPIO_E10, + S5PC110_GPIO_E11, + S5PC110_GPIO_E12, + S5PC110_GPIO_E13, + S5PC110_GPIO_E14, + S5PC110_GPIO_E15, + S5PC110_GPIO_E16, + S5PC110_GPIO_E17, + S5PC110_GPIO_F00, + S5PC110_GPIO_F01, + S5PC110_GPIO_F02, + S5PC110_GPIO_F03, + S5PC110_GPIO_F04, + S5PC110_GPIO_F05, + S5PC110_GPIO_F06, + S5PC110_GPIO_F07, + S5PC110_GPIO_F10, + S5PC110_GPIO_F11, + S5PC110_GPIO_F12, + S5PC110_GPIO_F13, + S5PC110_GPIO_F14, + S5PC110_GPIO_F15, + S5PC110_GPIO_F16, + S5PC110_GPIO_F17, + S5PC110_GPIO_F20, + S5PC110_GPIO_F21, + S5PC110_GPIO_F22, + S5PC110_GPIO_F23, + S5PC110_GPIO_F24, + S5PC110_GPIO_F25, + S5PC110_GPIO_F26, + S5PC110_GPIO_F27, + S5PC110_GPIO_F30, + S5PC110_GPIO_F31, + S5PC110_GPIO_F32, + S5PC110_GPIO_F33, + S5PC110_GPIO_F34, + S5PC110_GPIO_F35, + S5PC110_GPIO_F36, + S5PC110_GPIO_F37, + S5PC110_GPIO_G00, + S5PC110_GPIO_G01, + S5PC110_GPIO_G02, + S5PC110_GPIO_G03, + S5PC110_GPIO_G04, + S5PC110_GPIO_G05, + S5PC110_GPIO_G06, + S5PC110_GPIO_G07, + S5PC110_GPIO_G10, + S5PC110_GPIO_G11, + S5PC110_GPIO_G12, + S5PC110_GPIO_G13, + S5PC110_GPIO_G14, + S5PC110_GPIO_G15, + S5PC110_GPIO_G16, + S5PC110_GPIO_G17, + S5PC110_GPIO_G20, + S5PC110_GPIO_G21, + S5PC110_GPIO_G22, + S5PC110_GPIO_G23, + S5PC110_GPIO_G24, + S5PC110_GPIO_G25, + S5PC110_GPIO_G26, + S5PC110_GPIO_G27, + S5PC110_GPIO_G30, + S5PC110_GPIO_G31, + S5PC110_GPIO_G32, + S5PC110_GPIO_G33, + S5PC110_GPIO_G34, + S5PC110_GPIO_G35, + S5PC110_GPIO_G36, + S5PC110_GPIO_G37, + S5PC110_GPIO_I0, + S5PC110_GPIO_I1, + S5PC110_GPIO_I2, + S5PC110_GPIO_I3, + S5PC110_GPIO_I4, + S5PC110_GPIO_I5, + S5PC110_GPIO_I6, + S5PC110_GPIO_I7, + S5PC110_GPIO_J00, + S5PC110_GPIO_J01, + S5PC110_GPIO_J02, + S5PC110_GPIO_J03, + S5PC110_GPIO_J04, + S5PC110_GPIO_J05, + S5PC110_GPIO_J06, + S5PC110_GPIO_J07, + S5PC110_GPIO_J10, + S5PC110_GPIO_J11, + S5PC110_GPIO_J12, + S5PC110_GPIO_J13, + S5PC110_GPIO_J14, + S5PC110_GPIO_J15, + S5PC110_GPIO_J16, + S5PC110_GPIO_J17, + S5PC110_GPIO_J20, + S5PC110_GPIO_J21, + S5PC110_GPIO_J22, + S5PC110_GPIO_J23, + S5PC110_GPIO_J24, + S5PC110_GPIO_J25, + S5PC110_GPIO_J26, + S5PC110_GPIO_J27, + S5PC110_GPIO_J30, + S5PC110_GPIO_J31, + S5PC110_GPIO_J32, + S5PC110_GPIO_J33, + S5PC110_GPIO_J34, + S5PC110_GPIO_J35, + S5PC110_GPIO_J36, + S5PC110_GPIO_J37, + S5PC110_GPIO_J40, + S5PC110_GPIO_J41, + S5PC110_GPIO_J42, + S5PC110_GPIO_J43, + S5PC110_GPIO_J44, + S5PC110_GPIO_J45, + S5PC110_GPIO_J46, + S5PC110_GPIO_J47, + S5PC110_GPIO_MP010, + S5PC110_GPIO_MP011, + S5PC110_GPIO_MP012, + S5PC110_GPIO_MP013, + S5PC110_GPIO_MP014, + S5PC110_GPIO_MP015, + S5PC110_GPIO_MP016, + S5PC110_GPIO_MP017, + S5PC110_GPIO_MP020, + S5PC110_GPIO_MP021, + S5PC110_GPIO_MP022, + S5PC110_GPIO_MP023, + S5PC110_GPIO_MP024, + S5PC110_GPIO_MP025, + S5PC110_GPIO_MP026, + S5PC110_GPIO_MP027, + S5PC110_GPIO_MP030, + S5PC110_GPIO_MP031, + S5PC110_GPIO_MP032, + S5PC110_GPIO_MP033, + S5PC110_GPIO_MP034, + S5PC110_GPIO_MP035, + S5PC110_GPIO_MP036, + S5PC110_GPIO_MP037, + S5PC110_GPIO_MP040, + S5PC110_GPIO_MP041, + S5PC110_GPIO_MP042, + S5PC110_GPIO_MP043, + S5PC110_GPIO_MP044, + S5PC110_GPIO_MP045, + S5PC110_GPIO_MP046, + S5PC110_GPIO_MP047, + S5PC110_GPIO_MP050, + S5PC110_GPIO_MP051, + S5PC110_GPIO_MP052, + S5PC110_GPIO_MP053, + S5PC110_GPIO_MP054, + S5PC110_GPIO_MP055, + S5PC110_GPIO_MP056, + S5PC110_GPIO_MP057, + S5PC110_GPIO_MP060, + S5PC110_GPIO_MP061, + S5PC110_GPIO_MP062, + S5PC110_GPIO_MP063, + S5PC110_GPIO_MP064, + S5PC110_GPIO_MP065, + S5PC110_GPIO_MP066, + S5PC110_GPIO_MP067, + S5PC110_GPIO_MP070, + S5PC110_GPIO_MP071, + S5PC110_GPIO_MP072, + S5PC110_GPIO_MP073, + S5PC110_GPIO_MP074, + S5PC110_GPIO_MP075, + S5PC110_GPIO_MP076, + S5PC110_GPIO_MP077, + S5PC110_GPIO_MP100, + S5PC110_GPIO_MP101, + S5PC110_GPIO_MP102, + S5PC110_GPIO_MP103, + S5PC110_GPIO_MP104, + S5PC110_GPIO_MP105, + S5PC110_GPIO_MP106, + S5PC110_GPIO_MP107, + S5PC110_GPIO_MP110, + S5PC110_GPIO_MP111, + S5PC110_GPIO_MP112, + S5PC110_GPIO_MP113, + S5PC110_GPIO_MP114, + S5PC110_GPIO_MP115, + S5PC110_GPIO_MP116, + S5PC110_GPIO_MP117, + S5PC110_GPIO_MP120, + S5PC110_GPIO_MP121, + S5PC110_GPIO_MP122, + S5PC110_GPIO_MP123, + S5PC110_GPIO_MP124, + S5PC110_GPIO_MP125, + S5PC110_GPIO_MP126, + S5PC110_GPIO_MP127, + S5PC110_GPIO_MP130, + S5PC110_GPIO_MP131, + S5PC110_GPIO_MP132, + S5PC110_GPIO_MP133, + S5PC110_GPIO_MP134, + S5PC110_GPIO_MP135, + S5PC110_GPIO_MP136, + S5PC110_GPIO_MP137, + S5PC110_GPIO_MP140, + S5PC110_GPIO_MP141, + S5PC110_GPIO_MP142, + S5PC110_GPIO_MP143, + S5PC110_GPIO_MP144, + S5PC110_GPIO_MP145, + S5PC110_GPIO_MP146, + S5PC110_GPIO_MP147, + S5PC110_GPIO_MP150, + S5PC110_GPIO_MP151, + S5PC110_GPIO_MP152, + S5PC110_GPIO_MP153, + S5PC110_GPIO_MP154, + S5PC110_GPIO_MP155, + S5PC110_GPIO_MP156, + S5PC110_GPIO_MP157, + S5PC110_GPIO_MP160, + S5PC110_GPIO_MP161, + S5PC110_GPIO_MP162, + S5PC110_GPIO_MP163, + S5PC110_GPIO_MP164, + S5PC110_GPIO_MP165, + S5PC110_GPIO_MP166, + S5PC110_GPIO_MP167, + S5PC110_GPIO_MP170, + S5PC110_GPIO_MP171, + S5PC110_GPIO_MP172, + S5PC110_GPIO_MP173, + S5PC110_GPIO_MP174, + S5PC110_GPIO_MP175, + S5PC110_GPIO_MP176, + S5PC110_GPIO_MP177, + S5PC110_GPIO_MP180, + S5PC110_GPIO_MP181, + S5PC110_GPIO_MP182, + S5PC110_GPIO_MP183, + S5PC110_GPIO_MP184, + S5PC110_GPIO_MP185, + S5PC110_GPIO_MP186, + S5PC110_GPIO_MP187, + S5PC110_GPIO_MP200, + S5PC110_GPIO_MP201, + S5PC110_GPIO_MP202, + S5PC110_GPIO_MP203, + S5PC110_GPIO_MP204, + S5PC110_GPIO_MP205, + S5PC110_GPIO_MP206, + S5PC110_GPIO_MP207, + S5PC110_GPIO_MP210, + S5PC110_GPIO_MP211, + S5PC110_GPIO_MP212, + S5PC110_GPIO_MP213, + S5PC110_GPIO_MP214, + S5PC110_GPIO_MP215, + S5PC110_GPIO_MP216, + S5PC110_GPIO_MP217, + S5PC110_GPIO_MP220, + S5PC110_GPIO_MP221, + S5PC110_GPIO_MP222, + S5PC110_GPIO_MP223, + S5PC110_GPIO_MP224, + S5PC110_GPIO_MP225, + S5PC110_GPIO_MP226, + S5PC110_GPIO_MP227, + S5PC110_GPIO_MP230, + S5PC110_GPIO_MP231, + S5PC110_GPIO_MP232, + S5PC110_GPIO_MP233, + S5PC110_GPIO_MP234, + S5PC110_GPIO_MP235, + S5PC110_GPIO_MP236, + S5PC110_GPIO_MP237, + S5PC110_GPIO_MP240, + S5PC110_GPIO_MP241, + S5PC110_GPIO_MP242, + S5PC110_GPIO_MP243, + S5PC110_GPIO_MP244, + S5PC110_GPIO_MP245, + S5PC110_GPIO_MP246, + S5PC110_GPIO_MP247, + S5PC110_GPIO_MP250, + S5PC110_GPIO_MP251, + S5PC110_GPIO_MP252, + S5PC110_GPIO_MP253, + S5PC110_GPIO_MP254, + S5PC110_GPIO_MP255, + S5PC110_GPIO_MP256, + S5PC110_GPIO_MP257, + S5PC110_GPIO_MP260, + S5PC110_GPIO_MP261, + S5PC110_GPIO_MP262, + S5PC110_GPIO_MP263, + S5PC110_GPIO_MP264, + S5PC110_GPIO_MP265, + S5PC110_GPIO_MP266, + S5PC110_GPIO_MP267, + S5PC110_GPIO_MP270, + S5PC110_GPIO_MP271, + S5PC110_GPIO_MP272, + S5PC110_GPIO_MP273, + S5PC110_GPIO_MP274, + S5PC110_GPIO_MP275, + S5PC110_GPIO_MP276, + S5PC110_GPIO_MP277, + S5PC110_GPIO_MP280, + S5PC110_GPIO_MP281, + S5PC110_GPIO_MP282, + S5PC110_GPIO_MP283, + S5PC110_GPIO_MP284, + S5PC110_GPIO_MP285, + S5PC110_GPIO_MP286, + S5PC110_GPIO_MP287, + S5PC110_GPIO_RES, + S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)), + S5PC110_GPIO_H01, + S5PC110_GPIO_H02, + S5PC110_GPIO_H03, + S5PC110_GPIO_H04, + S5PC110_GPIO_H05, + S5PC110_GPIO_H06, + S5PC110_GPIO_H07, + S5PC110_GPIO_H10, + S5PC110_GPIO_H11, + S5PC110_GPIO_H12, + S5PC110_GPIO_H13, + S5PC110_GPIO_H14, + S5PC110_GPIO_H15, + S5PC110_GPIO_H16, + S5PC110_GPIO_H17, + S5PC110_GPIO_H20, + S5PC110_GPIO_H21, + S5PC110_GPIO_H22, + S5PC110_GPIO_H23, + S5PC110_GPIO_H24, + S5PC110_GPIO_H25, + S5PC110_GPIO_H26, + S5PC110_GPIO_H27, + S5PC110_GPIO_H30, + S5PC110_GPIO_H31, + S5PC110_GPIO_H32, + S5PC110_GPIO_H33, + S5PC110_GPIO_H34, + S5PC110_GPIO_H35, + S5PC110_GPIO_H36, + S5PC110_GPIO_H37, + + S5PC110_GPIO_MAX_PORT }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 +#define S5PC100_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = { + { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT }, +}; -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) +#define S5PC110_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = { + { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT }, +}; -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) +static inline struct gpio_info *get_gpio_data(void) +{ + if (cpu_is_s5pc100()) + return s5pc100_gpio_data; + else if (cpu_is_s5pc110()) + return s5pc110_gpio_data; -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + return NULL; +} -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_s5pc100()) + return S5PC100_GPIO_NUM_PARTS; + else if (cpu_is_s5pc110()) + return S5PC110_GPIO_NUM_PARTS; -#define S5PC100_SET_BANK(bank) \ - (((unsigned)&(((struct s5pc100_gpio *) \ - S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + return 0; +} -#define S5PC110_SET_BANK(bank) \ - ((((unsigned)&(((struct s5pc110_gpio *) \ - S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p]<bank><set><bit>, where + * p is optional + * <bank> - a single character bank name, as defined by the SOC + * <set> - a single digit set number + * <bit> - bit number within the set (in 0..7 range). + * + * <set><bit> essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + u8 bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; -#define s5pc100_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC100_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) +#define GPIO_PER_BANK 8 +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table s5pc100_gpio_table[] = { + GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0), + GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0), + GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0), + GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0), + GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0), + GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0), + { 0 } +}; -#define s5pc110_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC110_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) +static const struct gpio_name_num_table s5pc110_gpio_table[] = { + GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0), + GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0), + GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0), + GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0), + { 0 } +}; -static inline unsigned int s5p_gpio_base(int nr) -{ - return samsung_get_base_gpio(); -} +/* functions */ +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x2 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index d97190dd7c..44cd455699 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -14,11 +14,31 @@ #define GPIO_FULLPORT(x) ((x) >> 3) #define GPIO_BIT(x) ((x) & 0x7) +enum tegra_gpio_init { + TEGRA_GPIO_INIT_IN, + TEGRA_GPIO_INIT_OUT0, + TEGRA_GPIO_INIT_OUT1, +}; + +struct tegra_gpio_config { + u32 gpio:16; + u32 init:2; +}; + /* * Tegra-specific GPIO API */ +/** + * Configure a list of GPIOs + * + * @param config List of GPIO configurations + * @param len Number of config items in list + */ +void gpio_config_table(const struct tegra_gpio_config *config, int len); + void gpio_info(void); #define gpio_status() gpio_info() + #endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 035159d665..da477697bf 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -80,6 +80,11 @@ struct pmux_pingrp_config { #endif }; +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +void pinmux_set_tristate_input_clamping(void); +#endif + /* Set the mux function for a pin group */ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 310bbd7df9..84e7b5553d 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -14,8 +14,6 @@ /* for mmc_config definition */ #include <mmc.h> -#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ - #ifndef __ASSEMBLY__ struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index c1cb3ef16b..b86562ac6d 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -231,6 +231,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CEC, PMUX_FUNC_CLDVFS, diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index c49801c21d..1884935a57 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -247,6 +247,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CCLA, PMUX_FUNC_CEC, diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index 11c0104ff3..f7bc97fe5f 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -166,6 +166,7 @@ enum pmux_pingrp { * purely a convenience. The translation is done through a table search. */ enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_AHB_CLK, PMUX_FUNC_APB_CLK, PMUX_FUNC_AUDIO_SYNC, diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 6d83061dc1..a42e00990f 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -306,6 +306,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CEC, PMUX_FUNC_CLK_12M_OUT, diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1330..cca920b28e 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#if defined CONFIG_MX6SL +#define PAD_CTL_LVE (1 << 1) +#define PAD_CTL_LVE_BIT (1 << 22) +#endif + #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20 diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h new file mode 100644 index 0000000000..2d948508d5 --- /dev/null +++ b/arch/arm/include/asm/imx-common/video.h @@ -0,0 +1,24 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#ifdef CONFIG_IMX_HDMI +extern int detect_hdmi(struct display_info_t const *dev); +#endif + +#endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index e035d6acc0..585f1f781b 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -11,7 +11,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \ ifdef CONFIG_ARM64 obj-y += crt0_64.o else -obj-y += crt0.o +obj-y += vectors.o crt0.o endif ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 6cc136aa3c..4f6b9f01cb 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -12,16 +12,23 @@ void __flush_cache(unsigned long start, unsigned long size) { #if defined(CONFIG_ARM1136) - void arm1136_cache_flush(void); - arm1136_cache_flush(); +#if !defined(CONFIG_SYS_ICACHE_OFF) + asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ #endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ +#endif + +#endif /* CONFIG_ARM1136 */ + #ifdef CONFIG_ARM926EJS /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif +#endif /* CONFIG_ARM926EJS */ return; } void flush_cache(unsigned long start, unsigned long size) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S new file mode 100644 index 0000000000..d68cc477dc --- /dev/null +++ b/arch/arm/lib/vectors.S @@ -0,0 +1,291 @@ +/* + * vectors - Generic ARM exception table code + * + * Copyright (c) 1998 Dan Malek <dmalek@jlc.net> + * Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (c) 2000 Wolfgang Denk <wd@denx.de> + * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> + * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + ************************************************************************* + * + * Symbol _start is referenced elsewhere, so make it global + * + ************************************************************************* + */ + +.globl _start + +/* + ************************************************************************* + * + * Vectors have their own section so linker script can map them easily + * + ************************************************************************* + */ + + .section ".vectors", "x" + +/* + ************************************************************************* + * + * Exception vectors as described in ARM reference manuals + * + * Uses indirect branch to allow reaching handlers anywhere in memory. + * + ************************************************************************* + */ + +_start: + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG + .word CONFIG_SYS_DV_NOR_BOOT_CFG +#endif + +_start: + ldr pc, _reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +/* + ************************************************************************* + * + * Indirect vectors table + * + * Symbols referenced here must be defined somewhere else + * + ************************************************************************* + */ + + .globl _undefined_instruction + .globl _software_interrupt + .globl _prefetch_abort + .globl _data_abort + .globl _not_used + .globl _irq + .globl _fiq + +_reset: .word reset +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +/* SPL interrupt handling: just hang */ + +#ifdef CONFIG_SPL_BUILD + + .align 5 +undefined_instruction: +software_interrupt: +prefetch_abort: +data_abort: +not_used: +irq: +fiq: + +1: + bl 1b /* hang and never return */ + +#else /* !CONFIG_SPL_BUILD */ + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de + +#endif /* CONFIG_USE_IRQ */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif /* CONFIG_USE_IRQ */ + +#endif /* CONFIG_SPL_BUILD */ |