diff options
Diffstat (limited to 'arch/arm')
52 files changed, 638 insertions, 919 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0e8dc0179b..53d0831935 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1021,7 +1021,6 @@ config TARGET_COLIBRI_PXA270 config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT - select CLK_UNIPHIER select DM select DM_GPIO select DM_I2C diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 7b15d4ef7e..3992401590 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +else +obj-y += spr_misc.o spr_lowlevel_init.o endif extra-$(CONFIG_SPL_BUILD) := start.o diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index be0d14fbf0..7b9dc65c27 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -84,7 +84,7 @@ int print_cpuinfo(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC) static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S new file mode 100644 index 0000000000..649488399a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2006 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* + * platform specific initializations are already done in Xloader + * Initializations already done include + * DDR, PLLs, IP's clock enable and reset release etc + */ +.globl lowlevel_init +lowlevel_init: + mov pc, lr + +/* void setfreq(unsigned int device, unsigned int frequency) */ +.global setfreq +setfreq: + stmfd sp!,{r14} + stmfd sp!,{r0-r12} + + mov r8,sp + ldr sp,SRAM_STACK_V + + /* Saving the function arguements for later use */ + mov r4,r0 + mov r5,r1 + + /* Putting DDR into self refresh */ + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,DDR_ACTIVE_V + bic r1, r1, r2 + str r1,[r0] + ldr r0,DDR_57_V + ldr r1,[r0] + ldr r2,CYCLES_MASK_V + bic r1, r1, r2 + ldr r2,REFRESH_CYCLES_V + orr r1, r1, r2, lsl #16 + str r1,[r0] + ldr r0,DDR_07_V + ldr r1,[r0] + ldr r2,SREFRESH_MASK_V + orr r1, r1, r2 + str r1,[r0] + + /* flush pipeline */ + b flush + .align 5 +flush: + /* Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +delay: + sub r0,r0,#1 + cmp r0,#0 + bne delay + + /* Putting system in slow mode */ + ldr r0,SCCTRL_V + mov r1,#2 + str r1,[r0] + + /* Changing PLL(1/2) frequency */ + mov r0,r4 + mov r1,r5 + + cmp r4,#0 + beq pll1_freq + + /* Change PLL2 (DDR frequency) */ + ldr r6,PLL2_FREQ_V + ldr r7,PLL2_CNTL_V + b pll2_freq + +pll1_freq: + /* Change PLL1 (CPU frequency) */ + ldr r6,PLL1_FREQ_V + ldr r7,PLL1_CNTL_V + +pll2_freq: + mov r0,r6 + ldr r1,[r0] + ldr r2,PLLFREQ_MASK_V + bic r1,r1,r2 + mov r2,r5,lsr#1 + orr r1,r1,r2,lsl#24 + str r1,[r0] + + mov r0,r7 + ldr r1,P1C0A_V + str r1,[r0] + ldr r1,P1C0E_V + str r1,[r0] + ldr r1,P1C06_V + str r1,[r0] + ldr r1,P1C0E_V + str r1,[r0] + +lock: + ldr r1,[r0] + and r1,r1,#1 + cmp r1,#0 + beq lock + + /* Putting system back to normal mode */ + ldr r0,SCCTRL_V + mov r1,#4 + str r1,[r0] + + /* Putting DDR back to normal */ + ldr r0,DDR_07_V + ldr r1,[R0] + ldr r2,SREFRESH_MASK_V + bic r1, r1, r2 + str r1,[r0] + ldr r2,DDR_ACTIVE_V + orr r1, r1, r2 + str r1,[r0] + + /* Delay to ensure self refresh mode */ + ldr r0,SREFRESH_DELAY_V +1: + sub r0,r0,#1 + cmp r0,#0 + bne 1b + + mov sp,r8 + /* Resuming back to code */ + ldmia sp!,{r0-r12} + ldmia sp!,{pc} + +SCCTRL_V: + .word 0xfca00000 +PLL1_FREQ_V: + .word 0xfca8000C +PLL1_CNTL_V: + .word 0xfca80008 +PLL2_FREQ_V: + .word 0xfca80018 +PLL2_CNTL_V: + .word 0xfca80014 +PLLFREQ_MASK_V: + .word 0xff000000 +P1C0A_V: + .word 0x1C0A +P1C0E_V: + .word 0x1C0E +P1C06_V: + .word 0x1C06 + +SREFRESH_DELAY_V: + .word 0x9999 +SRAM_STACK_V: + .word 0xD2800600 +DDR_07_V: + .word 0xfc60001c +DDR_ACTIVE_V: + .word 0x01000000 +DDR_57_V: + .word 0xfc6000e4 +CYCLES_MASK_V: + .word 0xffff0000 +REFRESH_CYCLES_V: + .word 0xf0f0 +SREFRESH_MASK_V: + .word 0x00010000 + +.global setfreq_sz +setfreq_sz: + .word setfreq_sz - setfreq diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c new file mode 100644 index 0000000000..a02304f49e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <net.h> +#include <linux/mtd/st_smi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_emi.h> +#include <asm/arch/spr_defs.h> + +#define CPU 0 +#define DDR 1 +#define SRAM_REL 0xD2801000 + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer); +#endif + +int dram_init(void) +{ + /* Store complete RAM size and return */ + gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int board_early_init_f() +{ +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_NET) + uchar mac_id[6]; + + if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) + eth_env_set_enetaddr("ethaddr", mac_id); +#endif + env_set("verify", "n"); + +#if defined(CONFIG_SPEAR_USBTTY) + env_set("stdin", "usbtty"); + env_set("stdout", "usbtty"); + env_set("stderr", "usbtty"); + +#ifndef CONFIG_SYS_NO_DCACHE + dcache_enable(); +#endif +#endif + return 0; +} + +#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + +int spear_board_init(ulong mach_type) +{ + gd->bd->bi_arch_number = mach_type; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; + +#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif + return 0; +} + +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer) +{ + u8 buf[2]; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* Check if mac in i2c memory is valid */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + /* Valid mac address is saved in i2c eeprom */ + i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN); + return 0; + } + + return -1; +} + +static int write_mac(uchar *mac) +{ + u8 buf[2]; + + buf[0] = (u8)MAGIC_BYTE0; + buf[1] = (u8)MAGIC_BYTE1; + i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + buf[0] = (u8)~MAGIC_BYTE0; + buf[1] = (u8)~MAGIC_BYTE1; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* check if valid MAC address is saved in I2C EEPROM or not? */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); + puts("I2C EEPROM written with mac address \n"); + return 0; + } + + puts("I2C EEPROM writing failed\n"); + return -1; +} +#endif + +int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + void (*sram_setfreq) (unsigned int, unsigned int); + unsigned int frequency; +#if defined(CONFIG_CMD_NET) + unsigned char mac[6]; +#endif + + if ((argc > 3) || (argc < 2)) + return cmd_usage(cmdtp); + + if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) { + + frequency = simple_strtoul(argv[2], NULL, 0); + + if (frequency > 333) { + printf("Frequency is limited to 333MHz\n"); + return 1; + } + + sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz); + + if (!strcmp(argv[1], "cpufreq")) { + sram_setfreq(CPU, frequency); + printf("CPU frequency changed to %u\n", frequency); + } else { + sram_setfreq(DDR, frequency); + printf("DDR frequency changed to %u\n", frequency); + } + + return 0; + +#if defined(CONFIG_CMD_NET) + } else if (!strcmp(argv[1], "ethaddr")) { + + u32 reg; + char *e, *s = argv[2]; + for (reg = 0; reg < 6; ++reg) { + mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + write_mac(mac); + + return 0; +#endif + } else if (!strcmp(argv[1], "print")) { +#if defined(CONFIG_CMD_NET) + if (!i2c_read_mac(mac)) { + printf("Ethaddr (from i2c mem) = %pM\n", mac); + } else { + printf("Ethaddr (from i2c mem) = Not set\n"); + } +#endif + return 0; + } + + return cmd_usage(cmdtp); +} + +U_BOOT_CMD(chip_config, 3, 1, do_chip_config, + "configure chip", + "chip_config cpufreq/ddrfreq frequency\n" +#if defined(CONFIG_CMD_NET) + "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" +#endif + "chip_config print"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f5f4840f19..c9252751db 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -345,11 +345,38 @@ static void fdt_fixup_msi(void *blob) } #endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +/* Remove JR node used by SEC firmware */ +void fdt_fixup_remove_jr(void *blob) +{ + int jr_node, addr_cells, len; + int crypto_node = fdt_path_offset(blob, "crypto"); + u64 jr_offset, used_jr; + fdt32_t *reg; + + used_jr = sec_firmware_used_jobring_offset(); + fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL); + + jr_node = fdt_node_offset_by_compatible(blob, crypto_node, + "fsl,sec-v4.0-job-ring"); + + while (jr_node != -FDT_ERR_NOTFOUND) { + reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len); + jr_offset = fdt_read_number(reg, addr_cells); + if (jr_offset == used_jr) { + fdt_del_node(blob, jr_node); + break; + } + jr_node = fdt_node_offset_by_compatible(blob, jr_node, + "fsl,sec-v4.0-job-ring"); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { -#ifdef CONFIG_FSL_LSCH2 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr = in_be32(&gur->svr); + unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) @@ -358,11 +385,15 @@ void ft_cpu_setup(void *blob, bd_t *bd) else { ccsr_sec_t __iomem *sec; +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + if (fdt_fixup_kaslr(blob)) + fdt_fixup_remove_jr(blob); +#endif + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif -#endif #ifdef CONFIG_MP ft_fixup_cpu(blob); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index fffce712d3..0e7483437a 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -232,6 +232,59 @@ unsigned int sec_firmware_support_psci_version(void) #endif /* + * Check with sec_firmware if it supports random number generation + * via HW RNG + * + * The return value will be true if it is supported + */ +bool sec_firmware_support_hwrng(void) +{ + uint8_t rand[8]; + if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { + if (!sec_firmware_get_random(rand, 8)) + return true; + } + + return false; +} + +/* + * sec_firmware_get_random - Get a random number from SEC Firmware + * @rand: random number buffer to be filled + * @bytes: Number of bytes of random number to be supported + * @eret: -1 in case of error, 0 for success + */ +int sec_firmware_get_random(uint8_t *rand, int bytes) +{ + unsigned long long num; + struct pt_regs regs; + int param1; + + if (!bytes || bytes > 8) { + printf("Max Random bytes genration supported is 8\n"); + return -1; + } +#define SIP_RNG_64 0xC200FF11 + regs.regs[0] = SIP_RNG_64; + + if (bytes <= 4) + param1 = 0; + else + param1 = 1; + regs.regs[1] = param1; + + smc_call(®s); + + if (regs.regs[0]) + return -1; + + num = regs.regs[1]; + memcpy(rand, &num, bytes); + + return 0; +} + +/* * sec_firmware_init - Initialize the SEC Firmware * @sec_firmware_img: the SEC Firmware image address * @eret_hold_l: the address to hold exception return address low @@ -278,3 +331,49 @@ int sec_firmware_init(const void *sec_firmware_img, return 0; } + +/* + * fdt_fix_kaslr - Add kalsr-seed node in Device tree + * @fdt: Device tree + * @eret: 0 in case of error, 1 for success + */ +int fdt_fixup_kaslr(void *fdt) +{ + int nodeoffset; + int err, ret = 0; + u8 rand[8]; + +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) + /* Check if random seed generation is supported */ + if (sec_firmware_support_hwrng() == false) + return 0; + + ret = sec_firmware_get_random(rand, 8); + if (ret < 0) { + printf("WARNING: No random number to set kaslr-seed\n"); + return 0; + } + + err = fdt_check_header(fdt); + if (err < 0) { + printf("fdt_chosen: %s\n", fdt_strerror(err)); + return 0; + } + + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) + return 0; + + err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand, + sizeof(rand)); + if (err < 0) { + printf("WARNING: can't set kaslr-seed %s.\n", + fdt_strerror(err)); + return 0; + } + ret = 1; +#endif + + return ret; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d07715fc4f..762429c463 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -119,8 +119,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ uniphier-pxs2-vodka.dtb dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ uniphier-pxs3-ref.dtb -dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \ - uniphier-sld3-ref.dtb dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ uniphier-sld8-ref.dtb diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index b26e21bd7f..14caee7f0d 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -315,7 +315,6 @@ &edma 25>; dma-names = "tx", "rx"; interrupts = <64>; - interrupt-parent = <&intc>; reg = <0x48060000 0x1000>; status = "disabled"; }; @@ -328,7 +327,6 @@ &edma 3>; dma-names = "tx", "rx"; interrupts = <28>; - interrupt-parent = <&intc>; reg = <0x481d8000 0x1000>; status = "disabled"; }; @@ -338,7 +336,6 @@ ti,hwmods = "mmc3"; ti,needs-special-reset; interrupts = <29>; - interrupt-parent = <&intc>; reg = <0x47810000 0x1000>; status = "disabled"; }; @@ -724,7 +721,6 @@ 0x4a101200 0x100>; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; /* * c0_rx_thresh_pend * c0_rx_pend @@ -787,7 +783,6 @@ lcdc: lcdc@4830e000 { compatible = "ti,am33xx-tilcdc"; reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; interrupts = <36>; ti,hwmods = "lcdc"; status = "disabled"; @@ -796,7 +791,6 @@ tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; - interrupt-parent = <&intc>; interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 8d89b83b53..d8a65145d6 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -632,6 +632,34 @@ status = "disabled"; }; + rstc@f8048000 { + compatible = "atmel,sama5d3-rstc"; + reg = <0xf8048000 0x10>; + clocks = <&clk32k>; + }; + + shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + + pit: timer@f8048030 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xf8048030 0x10>; + clocks = <&h32ck>; + }; + + watchdog@f8048040 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xf8048040 0x10>; + clocks = <&clk32k>; + status = "disabled"; + }; + sckc@f8048050 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xf8048050 0x4>; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 927340fa48..44257aff35 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -426,6 +426,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 60287c478f..cbb848207c 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -587,6 +587,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -604,6 +605,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index a29597ae88..498354c45f 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -598,6 +598,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -615,6 +616,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 2962cb5ae7..32844f781f 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -610,6 +610,7 @@ compatible = "snps,dwc3"; reg = <0x65a00000 0x10000>; interrupts = <0 134 4>; + dr_mode = "host"; tx-fifo-resize; }; }; @@ -627,6 +628,7 @@ compatible = "snps,dwc3"; reg = <0x65c00000 0x10000>; interrupts = <0 137 4>; + dr_mode = "host"; tx-fifo-resize; }; }; diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts deleted file mode 100644 index baf706976a..0000000000 --- a/arch/arm/dts/uniphier-sld3-ref.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -/include/ "uniphier-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD3 Reference Board"; - compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi deleted file mode 100644 index 2bb2e029ee..0000000000 --- a/arch/arm/dts/uniphier-sld3.dtsi +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/ { - compatible = "socionext,uniphier-sld3"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - u-boot,dm-pre-reloc; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&sys_clk 0>; - clock-frequency = <36864000>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&sys_clk 1>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-sld3-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - u-boot,dm-pre-reloc; - - mio_clk: clock { - compatible = "socionext,uniphier-sld3-mio-clock"; - #clock-cells = <1>; - u-boot,dm-pre-reloc; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-sld3-mio-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge"; - resets = <&mio_rst 1>, <&mio_rst 4>; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; - cap-mmc-hw-reset; - }; - - sd: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, - <&mio_rst 15>; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-sld3-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-sld3-pinctrl"; - u-boot,dm-pre-reloc; - }; - }; - - aidet@f1830000 { - compatible = "simple-mfd", "syscon"; - reg = <0xf1830000 0x200>; - }; - - sysctrl@f1840000 { - compatible = "socionext,uniphier-sld3-sysctrl", - "simple-mfd", "syscon"; - reg = <0xf1840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-sld3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-sld3-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@f8000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; - interrupts = <0 65 4>; - clocks = <&sys_clk 2>; - nand-ecc-strength = <8>; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index bc1d97d7a9..6d42a7111f 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -8,10 +8,14 @@ #define __SEC_FIRMWARE_H_ #define PSCI_INVALID_VER 0xffffffff +#define SEC_JR3_OFFSET 0x40000 int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); +bool sec_firmware_support_hwrng(void); +int sec_firmware_get_random(uint8_t *rand, int bytes); +int fdt_fixup_kaslr(void *fdt); #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); @@ -22,4 +26,9 @@ static inline unsigned int sec_firmware_support_psci_version(void) } #endif +static inline unsigned int sec_firmware_used_jobring_offset(void) +{ + return SEC_JR3_OFFSET; +} + #endif /* __SEC_FIRMWARE_H_ */ diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 624ccd7c2f..dc935fd9e5 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -22,7 +22,9 @@ obj-y += cache.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o +ifeq ($(CONFIG_ATMEL_PIT_TIMER),) obj-y += timer.o +endif ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 9538bc1fad..1ede4cb10a 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o +ifeq ($(CONFIG_ATMEL_PIT_TIMER),) obj-y += timer.o +endif diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index f70f5ec965..947ce5f1ce 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -18,7 +18,7 @@ config STM32F7 select SPL_OF_CONTROL select SPL_OF_LIBFDT select SPL_OF_TRANSLATE - select SPL_OS_BOOT + imply SPL_OS_BOOT select SPL_PINCTRL select SPL_RAM select SPL_SERIAL_SUPPORT diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3147db76cb..6a7e239e0d 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -15,10 +15,6 @@ choice prompt "UniPhier SoC select" default ARCH_UNIPHIER_PRO4 -config ARCH_UNIPHIER_SLD3 - bool "UniPhier sLD3 SoC" - select ARCH_UNIPHIER_32BIT - config ARCH_UNIPHIER_LD4_SLD8 bool "UniPhier LD4/sLD8 SoCs" select ARCH_UNIPHIER_32BIT diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c index 658969b049..3df82bfef0 100644 --- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c @@ -197,9 +197,6 @@ void uniphier_cache_set_active_ways(int cpu, u32 active_ways) void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00; switch (readl(UNIPHIER_SSCID)) { /* revision */ - case 0x11: /* sLD3 */ - base = (void __iomem *)UNIPHIER_SSCC + 0x870; - break; case 0x12: /* LD4 */ case 0x16: /* sld8 */ base = (void __iomem *)UNIPHIER_SSCC + 0x840; diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index 76631f2faa..b39899e623 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -26,27 +26,6 @@ ENTRY(debug_ll_init) and r1, r1, #SG_REVISION_TYPE_MASK mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -#define UNIPHIER_SLD3_UART_CLK 36864000 - cmp r1, #0x25 - bne sld3_end - - sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0 - - ldr r0, =BCSCR5 - ldr r1, =0x24440000 - str r1, [r0] - - ldr r0, =SC_CLKCTRL - ldr r1, [r0] - orr r1, r1, #SC_CLKCTRL_CEN_PERI - str r1, [r0] - - ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE) - - b init_uart -sld3_end: -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) #define UNIPHIER_LD4_UART_CLK 36864000 cmp r1, #0x26 diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index af5ed1c050..a399a169a9 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -25,13 +25,16 @@ ENTRY(lowlevel_init) orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_DEBUG_LL + bl debug_ll_init +#endif + bl setup_init_ram @ RAM area for stack and page table /* * Now we are using the page table embedded in the Boot ROM. - * It is not handy since it is not a straight mapped table for sLD3. - * Also, the access to the external bus is prohibited. What we need - * to do next is to create a page table and switch over to it. + * What we need to do next is to create a page table and switch + * over to it. */ bl create_page_table bl __v7_flush_dcache_all @@ -43,10 +46,6 @@ ENTRY(lowlevel_init) bl enable_mmu -#ifdef CONFIG_DEBUG_LL - bl debug_ll_init -#endif - mov lr, r8 @ restore link mov pc, lr @ back to my caller ENDPROC(lowlevel_init) @@ -99,11 +98,6 @@ ENDPROC(enable_mmu) ENTRY(setup_init_ram) ldr r1, = SSCO_BASE - mrc p15, 0, r0, c2, c0, 0 @ TTBR0 - ldr r0, [r0, #0x400] @ entry for virtual address 0x100***** - bfc r0, #0, #20 - cmp r0, #0x50000000 @ is sLD3 page table? - biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1******* /* Touch to zero for the boot way */ 0: ldr r0, = 0x00408006 @ touch to zero with address range diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index 65a468dec9..3ab101a9cf 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -29,7 +29,6 @@ u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS]; static int uniphier_get_nr_cpus(void) { switch (uniphier_get_soc_id()) { - case UNIPHIER_SLD3_ID: case UNIPHIER_PRO4_ID: case UNIPHIER_PRO5_ID: return 2; diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile index 02107b376a..5a9d8d7272 100644 --- a/arch/arm/mach-uniphier/bcu/Makefile +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -2,6 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += bcu-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += bcu-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += bcu-ld4.o diff --git a/arch/arm/mach-uniphier/bcu/bcu-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-sld3.c deleted file mode 100644 index 99b318fd8f..0000000000 --- a/arch/arm/mach-uniphier/bcu/bcu-sld3.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "bcu-regs.h" - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd) -{ - int shift; - - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - /* - * 0xe0000000-0xefffffff: Ex-bus - * 0xf0000000-0xfbffffff: ASM bus - * 0xfc000000-0xffffffff: OCM bus - */ - writel(0x24440000, BCSCR5); - - /* Specify DDR channel */ - shift = bd->dram_ch[0].size / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 884bc67654..ed58d07f7e 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -86,15 +86,6 @@ struct uniphier_initdata { }; static const struct uniphier_initdata uniphier_initdata[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .nand_2cs = true, - .sbc_init = uniphier_sbc_init_admulti, - .pll_init = uniphier_sld3_pll_init, - .clk_init = uniphier_ld4_clk_init, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 78de256a01..9bfc4c2541 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -static const struct uniphier_board_data uniphier_sld3_data = { - .dram_freq = 1600, - .dram_ch[0] = { - .size = 0x20000000, - .width = 32, - }, - .dram_ch[1] = { - .size = 0x20000000, - .width = 16, - }, - .dram_ch[2] = { - .size = 0x10000000, - .width = 16, - }, - .flags = UNIPHIER_BD_DRAM_SPARSE, -}; -#endif - #if defined(CONFIG_ARCH_UNIPHIER_LD4) static const struct uniphier_board_data uniphier_ld4_data = { .dram_freq = 1600, @@ -146,9 +127,6 @@ struct uniphier_board_id { }; static const struct uniphier_board_id uniphier_boards[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { "socionext,uniphier-sld3", &uniphier_sld3_data, }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { "socionext,uniphier-ld4", &uniphier_ld4_data, }, #endif diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile index b357292130..6c8580ce79 100644 --- a/arch/arm/mach-uniphier/boot-device/Makefile +++ b/arch/arm/mach-uniphier/boot-device/Makefile @@ -4,7 +4,6 @@ obj-y += boot-device.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c b/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c deleted file mode 100644 index 2b36494f73..0000000000 --- a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2014 Panasonic Corporation - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spl.h> -#include <linux/io.h> -#include <linux/kernel.h> - -#include "boot-device.h" - -const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = { - {BOOT_DEVICE_NOR, "NOR (XECS0)"}, - {BOOT_DEVICE_NONE, "External Master"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, -}; - -const unsigned uniphier_sld3_boot_device_count = - ARRAY_SIZE(uniphier_sld3_boot_device_table); diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 094f77b4d1..0f93926f28 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -26,15 +26,6 @@ struct uniphier_boot_device_info { }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .boot_device_sel_shift = 0, - .boot_device_table = uniphier_sld3_boot_device_table, - .boot_device_count = &uniphier_sld3_boot_device_count, - .have_internal_stm = 0, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h index c4ce3e50a3..f9631d6820 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.h +++ b/arch/arm/mach-uniphier/boot-device/boot-device.h @@ -13,14 +13,12 @@ struct uniphier_boot_device { const char *desc; }; -extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[]; extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[]; extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[]; -extern const unsigned int uniphier_sld3_boot_device_count; extern const unsigned int uniphier_ld4_boot_device_count; extern const unsigned int uniphier_pro5_boot_device_count; extern const unsigned int uniphier_pxs2_boot_device_count; diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 1680dddd6e..76633bcd49 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -4,17 +4,15 @@ ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o else -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o diff --git a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c index 3430303f87..407daf0664 100644 --- a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c +++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c @@ -12,7 +12,7 @@ #include "../init.h" #include "../sc-regs.h" -void uniphier_sld3_dram_clk_init(void) +void uniphier_ld4_dram_clk_init(void) { u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/clk-early-sld3.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c index 3235da20bc..07b916dc9a 100644 --- a/arch/arm/mach-uniphier/clk/clk-early-sld3.c +++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c @@ -12,7 +12,7 @@ #include "../init.h" #include "../sc-regs.h" -void uniphier_sld3_early_clk_init(void) +void uniphier_ld4_early_clk_init(void) { u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/dpll-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c deleted file mode 100644 index 0eb310ceb8..0000000000 --- a/arch/arm/mach-uniphier/clk/dpll-sld3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" - -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) -{ - /* add pll init code here */ - return 0; -} diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c deleted file mode 100644 index 37a7c12782..0000000000 --- a/arch/arm/mach-uniphier/clk/pll-sld3.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "pll.h" - -void uniphier_sld3_pll_init(void) -{ - uniphier_ld4_dpll_ssc_en(); -} diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c index 2ce73c5af8..90ef411087 100644 --- a/arch/arm/mach-uniphier/cpu-info.c +++ b/arch/arm/mach-uniphier/cpu-info.c @@ -23,10 +23,6 @@ int print_cpuinfo(void) puts("SoC: "); switch (id) { - case UNIPHIER_SLD3_ID: - puts("sLD3"); - required_model = 2; - break; case UNIPHIER_LD4_ID: puts("LD4"); required_rev = 2; diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 0bad718de6..3837ee7ec6 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -3,7 +3,6 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += debug-uart-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c deleted file mode 100644 index 508318a682..0000000000 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/kernel.h> -#include <linux/io.h> - -#include "../bcu/bcu-regs.h" -#include "../sc-regs.h" -#include "../sg-regs.h" -#include "debug-uart.h" - -#define UNIPHIER_SLD3_UART_CLK 36864000 - -unsigned int uniphier_sld3_debug_uart_init(void) -{ - u32 tmp; - - sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */ - - writel(0x24440000, BCSCR5); - - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - - return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE); -} diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 72a514dc0e..94d05a8b9c 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -33,11 +33,6 @@ void _debug_uart_init(void) unsigned int divisor; switch (uniphier_get_soc_id()) { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - case UNIPHIER_SLD3_ID: - divisor = uniphier_sld3_debug_uart_init(); - break; -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) case UNIPHIER_LD4_ID: divisor = uniphier_ld4_debug_uart_init(); diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.h b/arch/arm/mach-uniphier/debug-uart/debug-uart.h index 8de9124b02..d57e5df3db 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.h +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.h @@ -7,7 +7,6 @@ #ifndef _MACH_DEBUG_UART_H #define _MACH_DEBUG_UART_H -unsigned int uniphier_sld3_debug_uart_init(void); unsigned int uniphier_ld4_debug_uart_init(void); unsigned int uniphier_pro4_debug_uart_init(void); unsigned int uniphier_sld8_debug_uart_init(void); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 1da33f6d80..baf2a7b481 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -4,7 +4,6 @@ ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \ diff --git a/arch/arm/mach-uniphier/dram/umc-sld3.c b/arch/arm/mach-uniphier/dram/umc-sld3.c deleted file mode 100644 index 99249eb201..0000000000 --- a/arch/arm/mach-uniphier/dram/umc-sld3.c +++ /dev/null @@ -1,6 +0,0 @@ -#include "../init.h" - -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd) -{ - return 0; -} diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 6eb8d26504..32d359321a 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -28,15 +28,6 @@ struct uniphier_memif_data { static const struct uniphier_memif_data uniphier_memif_data[] = { { - .soc_id = UNIPHIER_SLD3_ID, - .sparse_ch1_base = 0xc0000000, - /* - * In fact, SLD3 has DRAM ch2, but the memory regions for ch1 - * and ch2 overlap, and host cannot get access to them at the - * same time. Hide the ch2 from U-Boot. - */ - }, - { .soc_id = UNIPHIER_LD4_ID, .sparse_ch1_base = 0xc0000000, }, diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index b322628eed..29f638d947 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -28,7 +28,6 @@ struct uniphier_board_data { const struct uniphier_board_data *uniphier_get_board_param(void); -int uniphier_sld3_init(const struct uniphier_board_data *bd); int uniphier_ld4_init(const struct uniphier_board_data *bd); int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); @@ -63,34 +62,29 @@ static inline void uniphier_ld11_sbc_init(void) } #endif -void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd); void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd); int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd); -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd); int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd); -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd); int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd); -void uniphier_sld3_early_clk_init(void); +void uniphier_ld4_early_clk_init(void); -void uniphier_sld3_dram_clk_init(void); +void uniphier_ld4_dram_clk_init(void); void uniphier_pro5_dram_clk_init(void); void uniphier_pxs2_dram_clk_init(void); -int uniphier_sld3_umc_init(const struct uniphier_board_data *bd); int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pro5_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); -void uniphier_sld3_pll_init(void); void uniphier_ld4_pll_init(void); void uniphier_pro4_pll_init(void); void uniphier_ld11_pll_init(void); diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index 4ced2cbace..3b34e4d372 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -15,7 +15,7 @@ #include "init.h" static int __uniphier_memconf_init(const struct uniphier_board_data *bd, - int have_ch2, int have_ch2_disable_bit) + int have_ch2) { u32 val = 0; unsigned long size_per_word; @@ -100,8 +100,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, goto out; if (!bd->dram_ch[2].size) { - if (have_ch2_disable_bit) - val |= SG_MEMCONF_CH2_DISABLE; + val |= SG_MEMCONF_CH2_DISABLE; goto out; } @@ -149,15 +148,10 @@ out: int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd) { - return __uniphier_memconf_init(bd, 0, 0); -} - -int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd) -{ - return __uniphier_memconf_init(bd, 1, 0); + return __uniphier_memconf_init(bd, 0); } int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd) { - return __uniphier_memconf_init(bd, 1, 1); + return __uniphier_memconf_init(bd, 1); } diff --git a/arch/arm/mach-uniphier/mmc-boot-mode.c b/arch/arm/mach-uniphier/mmc-boot-mode.c index d60c578ce7..f40534eebb 100644 --- a/arch/arm/mach-uniphier/mmc-boot-mode.c +++ b/arch/arm/mach-uniphier/mmc-boot-mode.c @@ -14,7 +14,7 @@ u32 spl_boot_mode(const u32 boot_device) struct mmc *mmc; /* - * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8: + * work around a bug in the Boot ROM of LD4, Pro4, and sLD8: * * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of * Extended CSD register; when switching to the Boot Partition 1, the diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index ad58e10e23..54bbe43ebb 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -11,11 +11,7 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) -#define SC_BASE_ADDR 0xf1840000 -#else #define SC_BASE_ADDR 0x61840000 -#endif #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) diff --git a/arch/arm/mach-uniphier/soc-info.h b/arch/arm/mach-uniphier/soc-info.h index 04732527a7..9ba6a7ed69 100644 --- a/arch/arm/mach-uniphier/soc-info.h +++ b/arch/arm/mach-uniphier/soc-info.h @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/stddef.h> -#define UNIPHIER_SLD3_ID 0x25 #define UNIPHIER_LD4_ID 0x26 #define UNIPHIER_PRO4_ID 0x28 #define UNIPHIER_SLD8_ID 0x29 diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c index 6da5631bca..1272b4e25c 100644 --- a/arch/arm/mach-uniphier/spl_board_init.c +++ b/arch/arm/mach-uniphier/spl_board_init.c @@ -24,35 +24,24 @@ struct uniphier_spl_initdata { }; static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { - .soc_id = UNIPHIER_SLD3_ID, - .bcu_init = uniphier_sld3_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, - .dpll_init = uniphier_sld3_dpll_init, - .memconf_init = uniphier_memconf_3ch_no_disbit_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, - .umc_init = uniphier_sld3_umc_init, - }, -#endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, .bcu_init = uniphier_ld4_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_ld4_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_ld4_umc_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) { .soc_id = UNIPHIER_PRO4_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pro4_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_pro4_umc_init, }, #endif @@ -60,17 +49,17 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { { .soc_id = UNIPHIER_SLD8_ID, .bcu_init = uniphier_ld4_bcu_init, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_sld8_dpll_init, .memconf_init = uniphier_memconf_2ch_init, - .dram_clk_init = uniphier_sld3_dram_clk_init, + .dram_clk_init = uniphier_ld4_dram_clk_init, .umc_init = uniphier_sld8_umc_init, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) { .soc_id = UNIPHIER_PRO5_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pro5_dpll_init, .memconf_init = uniphier_memconf_2ch_init, .dram_clk_init = uniphier_pro5_dram_clk_init, @@ -80,7 +69,7 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS2) { .soc_id = UNIPHIER_PXS2_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pxs2_dpll_init, .memconf_init = uniphier_memconf_3ch_init, .dram_clk_init = uniphier_pxs2_dram_clk_init, @@ -90,7 +79,7 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { .soc_id = UNIPHIER_LD6B_ID, - .early_clk_init = uniphier_sld3_early_clk_init, + .early_clk_init = uniphier_ld4_early_clk_init, .dpll_init = uniphier_pxs2_dpll_init, .memconf_init = uniphier_memconf_3ch_init, .dram_clk_init = uniphier_pxs2_dram_clk_init, |