diff options
Diffstat (limited to 'arch/arm')
37 files changed, 1019 insertions, 40 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0083bf9ef0..38ad59058f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -788,6 +788,7 @@ config TARGET_HIKEY config TARGET_LS1012AQDS bool "Support ls1012aqds" + select ARCH_LS1012A select ARM64 help Support for Freescale LS1012AQDS platform. @@ -797,6 +798,7 @@ config TARGET_LS1012AQDS config TARGET_LS1012ARDB bool "Support ls1012ardb" + select ARCH_LS1012A select ARM64 help Support for Freescale LS1012ARDB platform. @@ -806,6 +808,7 @@ config TARGET_LS1012ARDB config TARGET_LS1012AFRDM bool "Support ls1012afrdm" + select ARCH_LS1012A select ARM64 help Support for Freescale LS1012AFRDM platform. @@ -817,16 +820,21 @@ config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 select SUPPORT_SPL + select ARCH_LS1021A select ARCH_SUPPORT_PSCI + select LS1_DEEP_SLEEP config TARGET_LS1021ATWR bool "Support ls1021atwr" select CPU_V7 select SUPPORT_SPL + select ARCH_LS1021A select ARCH_SUPPORT_PSCI + select LS1_DEEP_SLEEP config TARGET_LS1043AQDS bool "Support ls1043aqds" + select ARCH_LS1043A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -835,12 +843,39 @@ config TARGET_LS1043AQDS config TARGET_LS1043ARDB bool "Support ls1043ardb" + select ARCH_LS1043A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help Support for Freescale LS1043ARDB platform. +config TARGET_LS1046AQDS + bool "Support ls1046aqds" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + select DM_SPI_FLASH if DM_SPI + help + Support for Freescale LS1046AQDS platform. + The LS1046A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1046A + Layerscape Architecture processor. + +config TARGET_LS1046ARDB + bool "Support ls1046ardb" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + select DM_SPI_FLASH if DM_SPI + help + Support for Freescale LS1046ARDB platform. + The LS1046A Reference Design Board (RDB) is a high-performance + development platform that supports the QorIQ LS1046A + Layerscape Architecture processor. + config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -926,6 +961,8 @@ source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/cpu/armv7/ls102xa/Kconfig" + source "arch/arm/cpu/armv7/mx7/Kconfig" source "arch/arm/cpu/armv7/mx6/Kconfig" @@ -934,6 +971,8 @@ source "arch/arm/cpu/armv7/mx5/Kconfig" source "arch/arm/cpu/armv7/omap-common/Kconfig" +source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" + source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-rmobile/Kconfig" @@ -991,7 +1030,9 @@ source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" +source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig new file mode 100644 index 0000000000..920eb4ad98 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -0,0 +1,6 @@ +config ARCH_LS1021A + bool "Freescale Layerscape LS1021A SoC" + select SYS_FSL_ERRATUM_A010315 + +config LS1_DEEP_SLEEP + bool "Freescale Layerscape 1 deep sleep" diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 02283009ab..f8300c7775 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o ifdef CONFIG_ARMV7_PSCI -obj-y += psci.o +obj-y += psci.o ls102xa_psci.o endif diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c index 6212640d14..b4de523ee4 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -9,6 +9,163 @@ #include "fsl_epu.h" +struct fsm_reg_vals epu_default_val[] = { + /* EPGCR (Event Processor Global Control Register) */ + {EPGCR, 0}, + /* EPECR (Event Processor Event Control Registers) */ + {EPECR0 + EPECR_STRIDE * 0, 0}, + {EPECR0 + EPECR_STRIDE * 1, 0}, + {EPECR0 + EPECR_STRIDE * 2, 0xF0004004}, + {EPECR0 + EPECR_STRIDE * 3, 0x80000084}, + {EPECR0 + EPECR_STRIDE * 4, 0x20000084}, + {EPECR0 + EPECR_STRIDE * 5, 0x08000004}, + {EPECR0 + EPECR_STRIDE * 6, 0x80000084}, + {EPECR0 + EPECR_STRIDE * 7, 0x80000084}, + {EPECR0 + EPECR_STRIDE * 8, 0x60000084}, + {EPECR0 + EPECR_STRIDE * 9, 0x08000084}, + {EPECR0 + EPECR_STRIDE * 10, 0x42000084}, + {EPECR0 + EPECR_STRIDE * 11, 0x90000084}, + {EPECR0 + EPECR_STRIDE * 12, 0x80000084}, + {EPECR0 + EPECR_STRIDE * 13, 0x08000084}, + {EPECR0 + EPECR_STRIDE * 14, 0x02000084}, + {EPECR0 + EPECR_STRIDE * 15, 0x00000004}, + /* + * EPEVTCR (Event Processor EVT Pin Control Registers) + * SCU8 triger EVT2, and SCU11 triger EVT9 + */ + {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001}, + {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0}, + {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001}, + /* EPCMPR (Event Processor Counter Compare Registers) */ + {EPCMPR0 + EPCMPR_STRIDE * 0, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 1, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 3, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020}, + {EPCMPR0 + EPCMPR_STRIDE * 6, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 7, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 13, 0}, + {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF}, + {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF}, + /* EPCCR (Event Processor Counter Control Registers) */ + {EPCCR0 + EPCCR_STRIDE * 0, 0}, + {EPCCR0 + EPCCR_STRIDE * 1, 0}, + {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 3, 0}, + {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 6, 0}, + {EPCCR0 + EPCCR_STRIDE * 7, 0}, + {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 13, 0}, + {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000}, + {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000}, + /* EPSMCR (Event Processor SCU Mux Control Registers) */ + {EPSMCR0 + EPSMCR_STRIDE * 0, 0}, + {EPSMCR0 + EPSMCR_STRIDE * 1, 0}, + {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000}, + {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000}, + {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000}, + {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00}, + {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000}, + {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000}, + {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000}, + {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000}, + {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030}, + {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000}, + {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000}, + {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100}, + {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031}, + {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000}, + /* EPACR (Event Processor Action Control Registers) */ + {EPACR0 + EPACR_STRIDE * 0, 0}, + {EPACR0 + EPACR_STRIDE * 1, 0}, + {EPACR0 + EPACR_STRIDE * 2, 0}, + {EPACR0 + EPACR_STRIDE * 3, 0x00000080}, + {EPACR0 + EPACR_STRIDE * 4, 0}, + {EPACR0 + EPACR_STRIDE * 5, 0x00000040}, + {EPACR0 + EPACR_STRIDE * 6, 0}, + {EPACR0 + EPACR_STRIDE * 7, 0}, + {EPACR0 + EPACR_STRIDE * 8, 0}, + {EPACR0 + EPACR_STRIDE * 9, 0x0000001C}, + {EPACR0 + EPACR_STRIDE * 10, 0x00000020}, + {EPACR0 + EPACR_STRIDE * 11, 0}, + {EPACR0 + EPACR_STRIDE * 12, 0x00000003}, + {EPACR0 + EPACR_STRIDE * 13, 0x06000000}, + {EPACR0 + EPACR_STRIDE * 14, 0x04000000}, + {EPACR0 + EPACR_STRIDE * 15, 0x02000000}, + /* EPIMCR (Event Processor Input Mux Control Registers) */ + {EPIMCR0 + EPIMCR_STRIDE * 0, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 1, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 2, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 3, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000}, + {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000}, + {EPIMCR0 + EPIMCR_STRIDE * 6, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 7, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 8, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 9, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 10, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 11, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000}, + {EPIMCR0 + EPIMCR_STRIDE * 13, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 14, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 15, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000}, + {EPIMCR0 + EPIMCR_STRIDE * 17, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 18, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 19, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000}, + {EPIMCR0 + EPIMCR_STRIDE * 21, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000}, + {EPIMCR0 + EPIMCR_STRIDE * 23, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 24, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 25, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 26, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 27, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000}, + {EPIMCR0 + EPIMCR_STRIDE * 29, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 30, 0}, + {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000}, + /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ + {EPXTRIGCR, 0x0000FFDF}, + /* end */ + {FSM_END_FLAG, 0}, +}; + +/** + * fsl_epu_setup - Setup EPU registers to default values + */ +void fsl_epu_setup(void *epu_base) +{ + struct fsm_reg_vals *data = epu_default_val; + + if (!epu_base || !data) + return; + + while (data->offset != FSM_END_FLAG) { + out_be32(epu_base + data->offset, data->value); + data++; + } +} + /** * fsl_epu_clean - Clear EPU registers */ diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h index d658aad2ea..d6f731054d 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -63,6 +63,14 @@ #define EPCTR31 0xA7C #define EPCTR_STRIDE FSL_STRIDE_4B +#define FSM_END_FLAG 0xFFFFFFFFUL + +struct fsm_reg_vals { + u32 offset; + u32 value; +}; + +void fsl_epu_setup(void *epu_base); void fsl_epu_clean(void *epu_base); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index 46fac51341..8e247ee60b 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -23,9 +23,15 @@ int is_serdes_configured(enum srds_prtcl device) u64 ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!(serdes1_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes1_prtcl_map; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!(serdes2_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes2_prtcl_map; #endif @@ -87,19 +93,24 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) serdes_prtcl_map |= (1ULL << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1ULL << NONE); + return serdes_prtcl_map; } void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 - serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + if (!(serdes1_prtcl_map & (1ULL << NONE))) + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_SERDES_ADDR, RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 - serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + if (!(serdes2_prtcl_map & (1ULL << NONE))) + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_SERDES_ADDR + FSL_SRDS_2 * 0x1000, RCWSR4_SRDS2_PRTCL_MASK, diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c new file mode 100644 index 0000000000..1cbe93cf41 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -0,0 +1,236 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Author: Hongbo Zhang <hongbo.zhang@nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * This file implements LS102X platform PSCI SYSTEM-SUSPEND function + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/arch/immap_ls102xa.h> +#include <fsl_immap.h> +#include "fsl_epu.h" + +#define __secure __attribute__((section("._secure.text"))) + +#define CCSR_GICD_CTLR 0x1000 +#define CCSR_GICC_CTLR 0x2000 +#define DCSR_RCPM_CG1CR0 0x31c +#define DCSR_RCPM_CSTTACR0 0xb00 +#define DCFG_CRSTSR_WDRFR 0x8 +#define DDR_RESV_LEN 128 + +#ifdef CONFIG_LS1_DEEP_SLEEP +/* + * DDR controller initialization training breaks the first 128 bytes of DDR, + * save them so that the bootloader can restore them while resuming. + */ +static void __secure ls1_save_ddr_head(void) +{ + const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + int i; + + out_le32(&scfg->sparecr[2], dest); + + for (i = 0; i < DDR_RESV_LEN; i++) + *dest++ = *src++; +} + +static void __secure ls1_fsm_setup(void) +{ + void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; + + out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); + out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001); + + fsl_epu_setup((void *)dcsr_epu_base); + + /* Pull MCKE signal low before enabling deep sleep signal in FPGA */ + out_be32(dcsr_epu_base + EPECR0, 0x5); + out_be32(dcsr_epu_base + EPSMCR15, 0x76300000); +} + +static void __secure ls1_deepsleep_irq_cfg(void) +{ + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; + u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0; + + /* Mask interrupts from GIC */ + out_be32(&rcpm->nfiqoutr, 0x0ffffffff); + out_be32(&rcpm->nirqoutr, 0x0ffffffff); + /* Mask deep sleep wake-up interrupts while entering deep sleep */ + out_be32(&rcpm->dsimskr, 0x0ffffffff); + + ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); + /* + * Workaround: There is bug of register ippdexpcr1, when read it always + * returns zero, so its value is saved to a scrachpad register to be + * read, that is why we don't read it from register ippdexpcr1 itself. + */ + ippdexpcr1 = in_le32(&scfg->sparecr[7]); + + if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) + pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | + SCFG_PMCINTECR_ETSECRXG1 | + SCFG_PMCINTECR_ETSECERRG0 | + SCFG_PMCINTECR_ETSECERRG1; + + if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO) + pmcintecr |= SCFG_PMCINTECR_GPIO; + + if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART) + pmcintecr |= SCFG_PMCINTECR_LPUART; + + if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER) + pmcintecr |= SCFG_PMCINTECR_FTM; + + /* Always set external IRQ pins as wakeup source */ + pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1; + + out_be32(&scfg->pmcintlecr, 0); + /* Clear PMC interrupt status */ + out_be32(&scfg->pmcintsr, 0xffffffff); + /* Enable wakeup interrupt during deep sleep */ + out_be32(&scfg->pmcintecr, pmcintecr); +} + +static void __secure ls1_delay(unsigned int loop) +{ + while (loop--) { + int i = 1000; + while (i--) + ; + } +} + +static void __secure ls1_start_fsm(void) +{ + void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* Set HRSTCR */ + setbits_be32(&scfg->hrstcr, 0x80000000); + + /* Place DDR controller in self refresh mode */ + setbits_be32(&ddr->sdram_cfg_2, 0x80000000); + + ls1_delay(2000); + + /* Set EVT4_B to lock the signal MCKE down */ + out_be32(dcsr_epu_base + EPECR0, 0x0); + + ls1_delay(2000); + + out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0); + out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0); + + /* Enable all EPU Counters */ + setbits_be32(dcsr_epu_base + EPGCR, 0x80000000); + + /* Enable SCU15 */ + setbits_be32(dcsr_epu_base + EPECR15, 0x90000004); + + /* Enter WFI mode, and EPU FSM will start */ + __asm__ __volatile__ ("wfi" : : : "memory"); + + /* NEVER ENTER HERE */ + while (1) + ; +} + +static void __secure ls1_deep_sleep(u32 entry_point) +{ + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; +#ifdef QIXIS_BASE + u32 tmp; + void *qixis_base = (void *)QIXIS_BASE; +#endif + + /* Enable cluster to enter the PCL10 state */ + out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); + + /* Save the first 128 bytes of DDR data */ + ls1_save_ddr_head(); + + /* Save the kernel resume entry */ + out_le32(&scfg->sparecr[3], entry_point); + + /* Request to put cluster 0 in PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0); + + /* Setup the registers of the EPU FSM for deep sleep */ + ls1_fsm_setup(); + +#ifdef QIXIS_BASE + /* Connect the EVENT button to IRQ in FPGA */ + tmp = in_8(qixis_base + QIXIS_CTL_SYS); + tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; + tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; + out_8(qixis_base + QIXIS_CTL_SYS, tmp); + + /* Enable deep sleep signals in FPGA */ + tmp = in_8(qixis_base + QIXIS_PWR_CTL2); + tmp |= QIXIS_PWR_CTL2_PCTL; + out_8(qixis_base + QIXIS_PWR_CTL2, tmp); + + /* Pull down PCIe RST# */ + tmp = in_8(qixis_base + QIXIS_RST_FORCE_3); + tmp |= QIXIS_RST_FORCE_3_PCIESLOT1; + out_8(qixis_base + QIXIS_RST_FORCE_3, tmp); +#endif + + /* Enable Warm Device Reset */ + setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); + setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); + + ls1_deepsleep_irq_cfg(); + + psci_v7_flush_dcache_all(); + + ls1_start_fsm(); +} + +#else +static void __secure ls1_sleep(void) +{ + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; + +#ifdef QIXIS_BASE + u32 tmp; + void *qixis_base = (void *)QIXIS_BASE; + + /* Connect the EVENT button to IRQ in FPGA */ + tmp = in_8(qixis_base + QIXIS_CTL_SYS); + tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; + tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; + out_8(qixis_base + QIXIS_CTL_SYS, tmp); +#endif + + /* Enable cluster to enter the PCL10 state */ + out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); + + setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ); + + __asm__ __volatile__ ("wfi" : : : "memory"); +} +#endif + +void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id) +{ +#ifdef CONFIG_LS1_DEEP_SLEEP + ls1_deep_sleep(entry_point); +#else + ls1_sleep(); +#endif +} diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index 8f386800f6..3d41d37a64 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -29,6 +29,7 @@ #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0 .pushsection ._secure.text, "ax" @@ -61,6 +62,8 @@ _ls102x_psci_supported_table: .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK .word ARM_PSCI_0_2_FN_SYSTEM_RESET .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK + .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND + .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK .word 0 .word ARM_PSCI_RET_NI @@ -243,4 +246,12 @@ psci_system_reset: 1: wfi b 1b +.globl psci_system_suspend +psci_system_suspend: + push {lr} + + bl ls1_system_suspend + + pop {pc} + .popsection diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b1b0c710ae..31f00cbd69 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -7,9 +7,11 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_stream_id.h> +#include <fsl_csu.h> struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), @@ -58,12 +60,29 @@ unsigned int get_soc_major_rev(void) return major; } +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE2; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + #ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index f80f6e20d1..6a362085a6 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -187,7 +187,7 @@ ENDPROC(psci_get_cpu_id) .weak psci_get_cpu_id /* Imported from Linux kernel */ -LENTRY(v7_flush_dcache_all) +ENTRY(psci_v7_flush_dcache_all) stmfd sp!, {r4-r5, r7, r9-r11, lr} dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr @@ -234,7 +234,7 @@ finished: isb ldmfd sp!, {r4-r5, r7, r9-r11, lr} bx lr -ENDPROC(v7_flush_dcache_all) +ENDPROC(psci_v7_flush_dcache_all) ENTRY(psci_disable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR @@ -264,7 +264,7 @@ ENTRY(psci_cpu_off_common) isb dsb - bl v7_flush_dcache_all + bl psci_v7_flush_dcache_all clrex @ Why??? diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig new file mode 100644 index 0000000000..f8057baa03 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -0,0 +1,17 @@ +config ARCH_LS1012A + bool "Freescale Layerscape LS1012A SoC" + select SYS_FSL_MMDC + select SYS_FSL_ERRATUM_A010315 + +config ARCH_LS1043A + bool "Freescale Layerscape LS1043A SoC" + select SYS_FSL_ERRATUM_A010315 + +config ARCH_LS1046A + bool "Freescale Layerscape LS1046A SoC" + +config SYS_FSL_MMDC + bool "Freescale Multi Mode DDR Controller" + +config SYS_FSL_ERRATUM_A010315 + bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 8c1317faea..51c1ceeb83 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -30,10 +30,10 @@ ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif -ifneq ($(CONFIG_LS1012A),) +ifneq ($(CONFIG_ARCH_LS1012A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o endif -ifneq ($(CONFIG_LS1046A),) +ifneq ($(CONFIG_ARCH_LS1046A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 20be323084..f865373df3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -18,7 +18,6 @@ #include <asm/arch/mp.h> #endif #include <fm_eth.h> -#include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -457,10 +456,6 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) #ifdef CONFIG_SYS_MEM_TOP_HIDE #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function #endif -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - ram_top -= debug_server_get_dram_block_size(); -#endif /* Carve the MC private DRAM block from the end of DRAM */ #ifdef CONFIG_FSL_MC_ENET diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index db2771ab40..e06b063740 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -22,9 +22,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif @@ -98,6 +104,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; + if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; @@ -115,6 +124,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else serdes_prtcl_map[lane_prtcl] = 1; } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; } void fsl_serdes_init(void) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8922197d43..55005f0420 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -60,7 +60,7 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus = sysclk; #endif -#ifdef CONFIG_LS1012A +#ifdef CONFIG_ARCH_LS1012A sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; @@ -91,7 +91,7 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_LS1012A +#ifdef CONFIG_ARCH_LS1012A sys_info->freq_systembus = sys_info->freq_ddrbus / 2; sys_info->freq_ddrbus *= 2; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index d5f29ee970..7faa86c3fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -28,9 +28,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif @@ -79,6 +85,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; + if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; @@ -136,6 +145,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, #endif } } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; } void fsl_serdes_init(void) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5af6b73bc9..5d0b7a45c3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -179,6 +179,21 @@ ENTRY(lowlevel_init) isb dsb sy #endif + +#ifdef CONFIG_ARCH_LS1046A + /* Initialize the L2 RAM latency */ + mrs x1, S3_1_c11_c0_2 + mov x0, #0x1C7 + /* Clear L2 Tag RAM latency and L2 Data RAM latency */ + bic x1, x1, x0 + /* Set L2 data ram latency bits [2:0] */ + orr x1, x1, #0x2 + /* set L2 tag ram latency bits [8:6] */ + orr x1, x1, #0x80 + msr S3_1_c11_c0_2, x1 + isb +#endif + mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index f54ac3f431..b68e87d657 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -17,6 +17,9 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif int ppa_init(void) { @@ -24,12 +27,30 @@ int ppa_init(void) u32 *boot_loc_ptr_l, *boot_loc_ptr_h; int ret; +#ifdef CONFIG_CHAIN_OF_TRUST + uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR; + uintptr_t ppa_img_addr = 0; +#endif + #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR; #else #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" #endif +#ifdef CONFIG_CHAIN_OF_TRUST + ppa_img_addr = (uintptr_t)ppa_fit_addr; + if (fsl_check_boot_mode_secure() != 0) { + ret = fsl_secboot_validate(ppa_esbc_hdr, + CONFIG_PPA_KEY_HASH, + &ppa_img_addr); + if (ret != 0) + printf("PPA validation failed\n"); + else + printf("PPA validation Successful\n"); + } +#endif + #ifdef CONFIG_FSL_LSCH3 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); boot_loc_ptr_l = &gur->bootlocptrl; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d102..463d1e30d2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -8,10 +8,14 @@ #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS +#include <fsl_csu.h> +#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -58,11 +62,13 @@ static void erratum_a008336(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; - out_le32(eddrtqcr1, 0x63b30002); + if (fsl_ddr_get_version(0) == 0x50200) + out_le32(eddrtqcr1, 0x63b30002); #endif #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; - out_le32(eddrtqcr1, 0x63b30002); + if (fsl_ddr_get_version(0) == 0x50200) + out_le32(eddrtqcr1, 0x63b30002); #endif #endif } @@ -222,6 +228,10 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; +#ifdef CONFIG_ARCH_LS1046A + /* Disable SATA ECC */ + out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); +#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); @@ -298,11 +308,28 @@ void erratum_a008850_post(void) #endif } +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE4; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 19e34fade2..1dabdbb305 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -8,7 +8,6 @@ #include <spl.h> #include <asm/io.h> #include <fsl_ifc.h> -#include <fsl_csu.h> #include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -62,13 +61,5 @@ void board_init_f(ulong dummy) i2c_init_all(); #endif dram_init(); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - board_init_r(NULL, 0); } #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df57288076..e89b6e8074 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -144,6 +144,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ + fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ fsl-ls1012a-frdm.dtb diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts b/arch/arm/dts/fsl-ls1046a-qds-duart.dts new file mode 100644 index 0000000000..10a95ea025 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi new file mode 100644 index 0000000000..c5122930fe --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -0,0 +1,77 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@nxp.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A QDS Board"; + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <1000000>; /* input clock */ + spi-cpol; + spi-cpha; + reg = <0>; + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts new file mode 100644 index 0000000000..49024541e3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A RDB Board"; + + aliases { + spi0 = &qspi; + }; + +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + qflash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi new file mode 100644 index 0000000000..87dd9976d1 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -0,0 +1,166 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * Mingkai Hu <mingkai.hu@nxp.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "skeleton64.dtsi" + +/ { + compatible = "fsl,ls1046a"; + interrupt-parent = <&gic>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1410000 0 0x10000>, /* GICD */ + <0x0 0x1420000 0 0x10000>, /* GICC */ + <0x0 0x1440000 0 0x20000>, /* GICH */ + <0x0 0x1460000 0 0x20000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1046a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 65 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart2: serial@21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart3: serial@21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + num-cs = <4>; + big-endian; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 527998111f..a5c6c4cd26 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -7,15 +7,18 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ +#include <linux/kconfig.h> #include <fsl_ddrc_version.h> +#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 + #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #else #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ #endif -#ifndef CONFIG_LS1012A +#ifndef CONFIG_ARCH_LS1012A #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #endif @@ -165,6 +168,7 @@ #define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SRDS_1 + /* SoC related */ #ifdef CONFIG_LS1043A #define CONFIG_MAX_CPUS 4 @@ -201,13 +205,13 @@ #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#elif defined(CONFIG_LS1012A) +#elif defined(CONFIG_ARCH_LS1012A) #define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#elif defined(CONFIG_LS1046A) +#elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 @@ -234,6 +238,12 @@ #define GICC_BASE 0x01420000 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#define CONFIG_SYS_FSL_ERRATUM_A008511 +#define CONFIG_SYS_FSL_ERRATUM_A009801 +#define CONFIG_SYS_FSL_ERRATUM_A009803 +#define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A010165 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1b3f44d85..9f94b4505e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -11,6 +11,10 @@ #ifdef CONFIG_LS2080A enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, @@ -57,6 +61,10 @@ enum srds { }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 95a42935ca..df5187195d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ -#ifdef CONFIG_LS1012A +#ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 #else #define PCIE_LUT_BASE 0x10000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 93e26c1d7f..7acba2730a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,15 +33,6 @@ #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) -/* SP (Cortex-A5) related */ -#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) -#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ - (CONFIG_SYS_FSL_SP_ADDR + 0x0008) -#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ - (CONFIG_SYS_FSL_SP_ADDR + 0x1000) - #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index db76066c80..f46f1d866a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -6,6 +6,7 @@ #ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ +#include <fsl_csu.h> enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8d4a7adb1d..4512732f79 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -100,6 +100,10 @@ void cpu_name(char *name); void erratum_a009635(void); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + bool soc_has_dp_ddr(void); bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 56d8f3247f..fab8774028 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -16,7 +16,9 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) @@ -129,6 +131,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 3a92f5a7b4..fafc44b1a2 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -10,6 +10,10 @@ #include <config.h> enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 0a80772b51..c34fd63e66 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -161,6 +161,17 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000 +#define SCFG_DPSLPCR_WDRR_EN 0x00000001 +#define SCFG_PMCINTECR_LPUART 0x40000000 +#define SCFG_PMCINTECR_FTM 0x20000000 +#define SCFG_PMCINTECR_GPIO 0x10000000 +#define SCFG_PMCINTECR_IRQ0 0x08000000 +#define SCFG_PMCINTECR_IRQ1 0x04000000 +#define SCFG_PMCINTECR_ETSECRXG0 0x00800000 +#define SCFG_PMCINTECR_ETSECRXG1 0x00400000 +#define SCFG_PMCINTECR_ETSECERRG0 0x00080000 +#define SCFG_PMCINTECR_ETSECERRG1 0x00040000 +#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 /* Supplemental Configuration Unit */ struct ccsr_scfg { @@ -226,7 +237,7 @@ struct ccsr_scfg { u32 debug_streamid; u32 resv10[5]; u32 snpcnfgcr; - u32 resv11[1]; + u32 hrstcr; u32 intpcr; u32 resv12[20]; u32 scfgrevcr; @@ -243,6 +254,9 @@ struct ccsr_scfg { u32 sdhciovserlcr; u32 resv14[61]; u32 sparecr[8]; + u32 resv15[248]; + u32 core0sftrstsr; + u32 clusterpmcr; }; /* Clocking */ @@ -433,6 +447,42 @@ struct ccsr_ahci { u32 cmds; /* port 0/1 CMD status error */ }; +#define RCPM_POWMGTCSR 0x130 +#define RCPM_POWMGTCSR_SERDES_PW 0x80000000 +#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 +#define RCPM_POWMGTCSR_LPM20_ST 0x00000200 +#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 +#define RCPM_IPPDEXPCR0 0x140 +#define RCPM_IPPDEXPCR0_ETSEC 0x80000000 +#define RCPM_IPPDEXPCR0_GPIO 0x00000040 +#define RCPM_IPPDEXPCR1 0x144 +#define RCPM_IPPDEXPCR1_LPUART 0x40000000 +#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 +#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 +#define RCPM_NFIQOUTR 0x15c +#define RCPM_NIRQOUTR 0x16c +#define RCPM_DSIMSKR 0x18c +#define RCPM_CLPCL10SETR 0x1c4 +#define RCPM_CLPCL10SETR_C0 0x00000001 + +struct ccsr_rcpm { + u8 rev1[0x4c]; + u32 twaitsr; + u8 rev2[0xe0]; + u32 powmgtcsr; + u8 rev3[0xc]; + u32 ippdexpcr0; + u32 ippdexpcr1; + u8 rev4[0x14]; + u32 nfiqoutr; + u8 rev5[0xc]; + u32 nirqoutr; + u8 rev6[0x1c]; + u32 dsimskr; + u8 rev7[0x34]; + u32 clpcl10setr; +}; + uint get_svr(void); #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index a354684bcc..9c9135448e 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -11,4 +11,8 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); int ls102xa_smmu_stream_id_init(void); +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + #endif /* __FSL_LS102XA_SOC_H */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 051e8aeaf3..4525287f66 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -121,6 +121,24 @@ /* BOOTSCRIPT_ADDR is not required */ #endif +#ifdef CONFIG_FSL_LS_PPA +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_LS1043A +#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000 +#endif +#else +#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" +#endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */ + +/* Define the key hash here if SRK used for signing PPA image is + * different from SRK hash put in SFP used for U-Boot. + * Example + * #define CONFIG_PPA_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ +#define CONFIG_PPA_KEY_HASH NULL +#endif /* ifdef CONFIG_FSL_LS_PPA */ + #include <config_fsl_chain_trust.h> #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 5b8ce4d31b..9f1f779868 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -89,6 +89,8 @@ void psci_cpu_off_common(void); int psci_update_dt(void *fdt); void psci_board_init(void); int fdt_psci(void *fdt); + +void psci_v7_flush_dcache_all(void); #endif /* ! __ASSEMBLY__ */ #endif /* __ARM_PSCI_H__ */ |