diff options
Diffstat (limited to 'arch/arm')
81 files changed, 6154 insertions, 1333 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0bc4322c51..76365ef313 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -907,7 +907,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -919,7 +919,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index afe38e10b1..983e235f44 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-g12a-sei510.dtb \ meson-g12b-odroid-n2.dtb \ meson-g12b-a311d-khadas-vim3.dtb \ + meson-sm1-khadas-vim3l.dtb \ meson-sm1-sei610.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ @@ -329,6 +330,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex_socdk.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ @@ -702,7 +704,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mn-ddr4-evk.dtb \ - imx8mq-evk.dtb + imx8mq-evk.dtb \ + imx8mp-evk.dtb dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi new file mode 100644 index 0000000000..4675ada0a0 --- /dev/null +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c4 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&i2c6 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts new file mode 100644 index 0000000000..6df3beb92d --- /dev/null +++ b/arch/arm/dts/imx8mp-evk.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus EVK board"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-pinfunc.h b/arch/arm/dts/imx8mp-pinfunc.h new file mode 100644 index 0000000000..da78f89b6c --- /dev/null +++ b/arch/arm/dts/imx8mp-pinfunc.h @@ -0,0 +1,931 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DTS_IMX8MP_PINFUNC_H +#define __DTS_IMX8MP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K 0x014 0x274 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO00__SJC_FAIL 0x014 0x274 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M 0x018 0x278 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO01__SJC_ACTIVE 0x018 0x278 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK 0x020 0x280 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO03__SJC_DONE 0x020 0x280 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV 0x024 0x284 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO04__USDHC1_TEST_TRIG 0x024 0x284 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY 0x028 0x288 0x554 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT 0x028 0x288 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO05__USDHC2_TEST_TRIG 0x028 0x288 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO06__ECSPI1_TEST_TRIG 0x02C 0x28C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO07__ECSPI2_TEST_TRIG 0x030 0x290 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT 0x034 0x294 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO08__FLEXSPI_TEST_TRIG 0x034 0x294 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP 0x038 0x298 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO09__RAWNAND_TEST_TRIG 0x038 0x298 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__HSIOMIX_usb1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO10__OCOTP_FUSE_LATCHED 0x03C 0x29C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__HSIOMIX_usb2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 +#define MX8MP_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0 0x040 0x2A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO11__CAAM_RNG_OSC_OBS 0x040 0x2A0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1 0x044 0x2A4 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO12__CSU_CSU_ALARM_AUT00 0x044 0x2A4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__HSIOMIX_usb1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2 0x048 0x2A8 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO13__CSU_CSU_ALARM_AUT01 0x048 0x2A8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO14__CSU_CSU_ALARM_AUT02 0x04C 0x2AC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__HSIOMIX_usb2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x050 0x2B0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_GPIO1_IO15__CSU_CSU_INT_DEB 0x050 0x2B0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDC__SIM_M_HADDR15 0x054 0x2B4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 +#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 +#define MX8MP_IOMUXC_ENET_MDIO__SIM_M_HADDR16 0x058 0x2B8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD3__SIM_M_HADDR17 0x05C 0x2BC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TD2__SIM_M_HADDR18 0x060 0x2C0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TD1__SIM_M_HADDR19 0x064 0x2C4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 +#define MX8MP_IOMUXC_ENET_TD0__SIM_M_HADDR20 0x068 0x2C8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT 0x06C 0x2CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TX_CTL__SIM_M_HADDR21 0x06C 0x2CC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 +#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_CLK 0x084 0x2E4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD2__SIM_M_HADDR27 0x084 0x2E4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 +#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF_IN 0x088 0x2E8 0x544 0x3 0x0 +#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 +#define MX8MP_IOMUXC_ENET_RD3__SIM_M_HADDR28 0x088 0x2E8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_CLK__SIM_M_HADDR29 0x08C 0x2EC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_CMD__SIM_M_HADDR30 0x090 0x2F0 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA0__SIM_M_HADDR31 0x094 0x2F4 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA1__SIM_M_HBURST00 0x098 0x2F8 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA2__SIM_M_HBURST01 0x09C 0x2FC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA3__SIM_M_HBURST02 0x0A0 0x300 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA4__SIM_M_HRESP 0x0A4 0x304 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA5__TPSMP_HDATA05 0x0A8 0x308 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA6__TPSMP_HDATA06 0x0AC 0x30C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 +#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_DATA7__TPSMP_HDATA07 0x0B0 0x310 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_RESET_B__ECSPI3_TEST_TRIG 0x0B4 0x314 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 +#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD1_STROBE__USDHC3_TEST_TRIG 0x0B8 0x318 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0BC 0x31C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0C0 0x320 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CLK__OBSERVE_MUX_OUT00 0x0C0 0x320 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 +#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_CLK 0x0C4 0x324 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0C4 0x324 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_CMD__OBSERVE_MUX_OUT01 0x0C4 0x324 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 +#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 +#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0CC 0x32C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA1__OBSERVE_MUX_OUT03 0x0CC 0x32C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF_OUT 0x0D0 0x330 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0D0 0x330 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_DATA2__OBSERVE_MUX_OUT04 0x0D0 0x330 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1 +#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x1 +#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SD2_WP__SIM_M_HMASTLOCK 0x0DC 0x33C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_ALE__RAWNAND_ALE 0x0E0 0x340 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 +#define MX8MP_IOMUXC_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_ALE__SIM_M_HPROT00 0x0E0 0x340 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 +#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE0_B__SIM_M_HPROT01 0x0E4 0x344 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE1_B__SIM_M_HPROT02 0x0E8 0x348 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE2_B__SIM_M_HPROT03 0x0EC 0x34C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CE3_B__SIM_M_HADDR00 0x0F0 0x350 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_CLE__RAWNAND_CLE 0x0F4 0x354 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 +#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_CLE__SIM_M_HADDR01 0x0F4 0x354 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__RAWNAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA00__SIM_M_HADDR02 0x0F8 0x358 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__RAWNAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 +#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA01__SIM_M_HADDR03 0x0FC 0x35C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__RAWNAND_DATA02 0x100 0x360 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 +#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA02__SIM_M_HADDR04 0x100 0x360 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__RAWNAND_DATA03 0x104 0x364 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA03__SIM_M_HADDR05 0x104 0x364 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__RAWNAND_DATA04 0x108 0x368 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA04__SIM_M_HADDR06 0x108 0x368 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__RAWNAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA05__SIM_M_HADDR07 0x10C 0x36C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__RAWNAND_DATA06 0x110 0x370 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA06__SIM_M_HADDR08 0x110 0x370 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__RAWNAND_DATA07 0x114 0x374 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DATA07__SIM_M_HADDR09 0x114 0x374 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_DQS__RAWNAND_DQS 0x118 0x378 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 +#define MX8MP_IOMUXC_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 +#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 +#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_DQS__SIM_M_HADDR10 0x118 0x378 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__RAWNAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 +#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_RE_B__SIM_M_HADDR11 0x11C 0x37C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__RAWNAND_READY_B 0x120 0x380 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 +#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_READY_B__SIM_M_HADDR12 0x120 0x380 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__RAWNAND_WE_B 0x124 0x384 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 +#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WE_B__SIM_M_HADDR13 0x124 0x384 0x000 0x7 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__RAWNAND_WP_B 0x128 0x388 0x000 0x0 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 +#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 +#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 +#define MX8MP_IOMUXC_NAND_WP_B__SIM_M_HADDR14 0x128 0x388 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_CLK 0x130 0x390 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x2 +#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x2 +#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x2 +#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x2 +#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 +#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x148 0x3A8 0x508 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK 0x14C 0x3AC 0x4F4 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_CLK 0x14C 0x3AC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x3 +#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x3 +#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x3 +#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x3 +#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 +#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 +#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 +#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC 0x170 0x3D0 0x510 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 +#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK 0x174 0x3D4 0x50C 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 0x178 0x3D8 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 0x17C 0x3DC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 0x180 0x3E0 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 0x184 0x3E4 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 +#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_CLK 0x194 0x3F4 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI5_MCLK 0x198 0x3F8 0x4F0 0x1 0x1 +#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 +#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 +#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x4 +#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x4 +#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 +#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x4 +#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 +#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x5 +#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 0x1B0 0x410 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI2_TXD0__TPSMP_CLK 0x1B0 0x410 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 +#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 +#define MX8MP_IOMUXC_SAI2_MCLK__TPSMP_HDATA_DIR 0x1B4 0x414 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x4 +#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 +#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_CLK 0x1BC 0x41C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI3_RXC__TPSMP_HTRANS01 0x1BC 0x41C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 +#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x6 +#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 +#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x5 +#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 +#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x6 +#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 +#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 0x1CC 0x42C 0x000 0x6 0x0 +#define MX8MP_IOMUXC_SAI3_TXD__TPSMP_HDATA03 0x1CC 0x42C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 +#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_OUT 0x1D0 0x430 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF_IN 0x1D0 0x430 0x544 0x6 0x3 +#define MX8MP_IOMUXC_SAI3_MCLK__TPSMP_HDATA04 0x1D0 0x430 0x000 0x7 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0x1D4 0x434 0x000 0x0 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 +#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0x1D8 0x438 0x544 0x0 0x4 +#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 +#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 +#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 +#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_SCLK__TPSMP_HDATA08 0x1E0 0x440 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 +#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MOSI__TPSMP_HDATA09 0x1E4 0x444 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_MISO__TPSMP_HDATA10 0x1E8 0x448 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI1_SS0__TPSMP_HDATA11 0x1EC 0x44C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 +#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_SCLK__TPSMP_HDATA12 0x1F0 0x450 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 +#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 +#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MOSI__TPSMP_HDATA13 0x1F4 0x454 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__TPSMP_HDATA14 0x1F8 0x458 0x000 0x7 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 +#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 +#define MX8MP_IOMUXC_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 0x1F8 0x458 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 +#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 +#define MX8MP_IOMUXC_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_ECSPI2_SS0__TPSMP_HDATA15 0x1FC 0x45C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SCL__TPSMP_HDATA16 0x200 0x460 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 +#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 +#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C1_SDA__TPSMP_HDATA17 0x204 0x464 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SCL__TPSMP_HDATA18 0x208 0x468 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 +#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 +#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 +#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C2_SDA__TPSMP_HDATA19 0x20C 0x46C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SCL__TPSMP_HDATA20 0x210 0x470 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 +#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 +#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C3_SDA__TPSMP_HDATA21 0x214 0x474 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SCL__TPSMP_HDATA22 0x218 0x478 0x000 0x7 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 +#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 +#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_I2C4_SDA__TPSMP_HDATA23 0x21C 0x47C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 +#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_RXD__TPSMP_HDATA24 0x220 0x480 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 +#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART1_TXD__TPSMP_HDATA25 0x224 0x484 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 +#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_RXD__TPSMP_HDATA26 0x228 0x488 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 +#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART2_TXD__TPSMP_HDATA27 0x22C 0x48C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 +#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 +#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 +#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 +#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_RXD__TPSMP_HDATA28 0x230 0x490 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 +#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 +#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 +#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 +#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART3_TXD__TPSMP_HDATA29 0x234 0x494 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 +#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 +#define MX8MP_IOMUXC_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 +#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 +#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 +#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_RXD__TPSMP_HDATA30 0x238 0x498 0x000 0x7 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 +#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 +#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 +#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 +#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 +#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 +#define MX8MP_IOMUXC_UART4_TXD__TPSMP_HDATA31 0x23C 0x49C 0x000 0x7 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x240 0x4A0 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SCL__AUDIOMIX_test_out00 0x240 0x4A0 0x000 0x6 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x244 0x4A4 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_DDC_SDA__AUDIOMIX_test_out01 0x244 0x4A4 0x000 0x6 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x248 0x4A8 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 +#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x24C 0x4AC 0x000 0x0 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 +#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 +#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 + +#endif /* __DTS_IMX8MP_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi new file mode 100644 index 0000000000..0fb29cc812 --- /dev/null +++ b/arch/arm/dts/imx8mp.dtsi @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "imx8mp-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-latency = <61036>; + clocks = <&clk IMX8MP_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-latency = <61036>; + clocks = <&clk IMX8MP_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; + clocks = <&clk IMX8MP_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; + clocks = <&clk IMX8MP_CLK_ARM>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips1: bus@30000000 { + compatible = "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 5 30>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 35 21>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 82 32>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 114 30>; + }; + + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", + "syscon"; + reg = <0x30360000 0x10000>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "snvs-rtc"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + status = "disabled"; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + }; + + src: src@30390000 { + compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + }; + + aips2: bus@30400000 { + compatible = "simple-bus"; + reg = <0x30400000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, + <&clk IMX8MP_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, + <&clk IMX8MP_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, + <&clk IMX8MP_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, + <&clk IMX8MP_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART4_ROOT>, + <&clk IMX8MP_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c5: i2c@30ad0000 { + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30ad0000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; + status = "disabled"; + }; + + i2c6: i2c@30ae0000 { + compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30ae0000 0x10000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; + status = "disabled"; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS>, + <&clk IMX8MP_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, + <&clk IMX8MP_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, + <&clk IMX8MP_CLK_SIM_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_PHY_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_TIMER>, + <&clk IMX8MP_CLK_ENET_REF>, + <&clk IMX8MP_CLK_ENET_TIMER>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x38800000 0x10000>, + <0x38880000 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + }; +}; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts new file mode 100644 index 0000000000..1001b376ca --- /dev/null +++ b/arch/arm/dts/meson-sm1-khadas-vim3l.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include "meson-khadas-vim3.dtsi" + +/ { + compatible = "khadas,vim3l", "amlogic,sm1"; + model = "Khadas VIM3L"; + + vddcpu: regulator-vddcpu { + /* + * Silergy SY8030DEC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&vsys_3v3>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +/* + * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential + * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between + * an USB3.0 Type A connector and a M.2 Key M slot. The PHY driving + * these differential lines is shared between the USB3.0 controller + * and the PCIe Controller, thus only a single controller can use it. + * If the MCU is configured to mux the PCIe/USB3.0 differential lines + * to the M.2 Key M slot, uncomment the following block to disable + * USB3.0 from the USB Complex and enable the PCIe controller. + * The End User is not expected to uncomment the following except for + * testing purposes, but instead rely on the firmware/bootloader to + * update these nodes accordingly if PCIe mode is selected by the MCU. + */ + +/* +&pcie { + status = "okay"; +}; + +&usb { + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; +}; + */ diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index 322c858c4b..d55460755f 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -10,6 +10,10 @@ }; }; +&clkmgr { + u-boot,dm-pre-reloc; +}; + &rst { u-boot,dm-pre-reloc; }; @@ -17,3 +21,7 @@ &sdr { u-boot,dm-pre-reloc; }; + +&sysmgr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 51a6a51b53..eda558f2fe 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -114,7 +114,7 @@ status = "disabled"; }; - clkmgr@ffd04000 { + clkmgr: clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi new file mode 100644 index 0000000000..f0528a9ad9 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + + ccu: cache-controller@f7000000 { + compatible = "arteris,ncore-ccu"; + reg = <0xf7000000 0x100900>; + u-boot,dm-pre-reloc; + }; + }; +}; + +&clkmgr { + u-boot,dm-pre-reloc; +}; + +&gmac1 { + altr,sysmgr-syscon = <&sysmgr 0x48 0>; +}; + +&gmac2 { + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; +}; + +&i2c0 { + reset-names = "i2c"; +}; + +&i2c1 { + reset-names = "i2c"; +}; + +&i2c2 { + reset-names = "i2c"; +}; + +&i2c3 { + reset-names = "i2c"; +}; + +&mmc { + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; +}; + +&sdr { + compatible = "intel,sdr-ctl-agilex"; + reg = <0xf8000400 0x80>, + <0xf8010000 0x190>, + <0xf8011000 0x500>; + resets = <&rst DDRSCH_RESET>; + u-boot,dm-pre-reloc; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi new file mode 100644 index 0000000000..179b4d5591 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex-clock.h> + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + clocks = <&clkmgr AGILEX_EMAC0_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = <0 91 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; + clocks = <&clkmgr AGILEX_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = <0 92 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 16>; + clocks = <&clkmgr AGILEX_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@ffc02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@ffc02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 96 4>; + fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + clocks = <&clkmgr AGILEX_L4_MP_CLK>, + <&clkmgr AGILEX_SDMMC_CLK>; + clock-names = "biu", "ciu"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + pdma: pdma@ffda0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda0000 0x1000>; + interrupts = <0 81 4>, + <0 82 4>, + <0 83 4>, + <0 84 4>, + <0 85 4>, + <0 86 4>, + <0 87 4>, + <0 88 4>, + <0 89 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; + reset-names = "dma", "dma-ocp"; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + clock-names = "apb_pclk"; + }; + + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,stratix10-rst-mgr"; + reg = <0xffd11000 0x100>; + }; + + smmu: iommu@fa000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0xfa000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0xffd12000 0x500>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@ffc03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0xffc03000 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@ffc03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0xffc03100 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0xffd00000 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0xffd00100 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-frequency = <100000000>; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX_USB_CLK>; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0x40000>; + interrupts = <0 94 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + iommus = <&smmu 7>; + clocks = <&clkmgr AGILEX_USB_CLK>; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@ffd00400 { + compatible = "snps,dw-wdt"; + reg = <0xffd00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@ffd00500 { + compatible = "snps,dw-wdt"; + reg = <0xffd00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + sdr: sdr@f8011100 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xf8011100 0xc0>; + }; + + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 15 4>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-s10"; + altr,sdr-syscon = <&sdr>; + interrupts = <16 4>; + }; + + ocram-ecc@ff8cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8cc000 0x100>; + altr,ecc-parent = <&ocram>; + interrupts = <1 4>; + }; + + usb0-ecc@ff8c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0xff8c4000 0x100>; + altr,ecc-parent = <&usb0>; + interrupts = <2 4>; + }; + + emac0-rx-ecc@ff8c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0000 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 4>; + }; + + emac0-tx-ecc@ff8c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0400 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 4>; + }; + + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; + + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi new file mode 100644 index 0000000000..1908be4b8b --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include "socfpga_agilex-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + }; + + memory { + /* 8GB */ + reg = <0 0x00000000 0 0x80000000>, + <2 0x80000000 1 0x80000000>; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts new file mode 100644 index 0000000000..bcdeecc0e0 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk.dts @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x034B0000>; + }; + + qspi_rootfs: partition@34B0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x034B0000 0x0EB50000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index c11a5c0cc1..cc529bcd11 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -96,7 +96,7 @@ fpga-mgr = <&fpga_mgr>; }; - clkmgr@ffd04000 { + clkmgr: clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 6e5578d7bd..ef10708ee8 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -180,3 +180,11 @@ &l4_sp_clk { u-boot,dm-pre-reloc; }; + +&clkmgr { + u-boot,dm-pre-reloc; +}; + +&sysmgr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index bd68a78a37..a8e61cf728 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -82,7 +82,7 @@ ranges = <0 0 0 0xffffffff>; u-boot,dm-pre-reloc; - clkmgr@ffd1000 { + clkmgr: clkmgr@ffd10000 { compatible = "altr,clk-mgr"; reg = <0xffd10000 0x1000>; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index e1cfb522bf..38855aecd7 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -11,6 +11,10 @@ }; }; +&clkmgr { + u-boot,dm-pre-reloc; +}; + &qspi { status = "okay"; u-boot,dm-pre-reloc; @@ -23,3 +27,7 @@ spi-rx-bus-width = <4>; u-boot,dm-pre-reloc; }; + +&sysmgr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index 1fee5ffbfb..bfdfb764b2 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -106,6 +106,16 @@ function = "i2c4"; }; + pinctrl_i2c5: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + pinctrl_i2c6: i2c6 { + groups = "i2c6"; + function = "i2c6"; + }; + pinctrl_nand: nand { groups = "nand"; function = "nand"; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index b0f4dd089f..5ade63665a 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -33,6 +33,7 @@ #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ #define MXC_CPU_IMX8MN 0x8b /* dummy ID */ +#define MXC_CPU_IMX8MP 0x182/* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c910b614ac..87cc4d3b2b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -9,7 +9,8 @@ #ifdef CONFIG_IMX8MQ #include <asm/arch/clock_imx8mq.h> -#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \ + defined(CONFIG_IMX8MP) #include <asm/arch/clock_imx8mm.h> #else #error "Error no clock.h" diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h index 76c73edc90..debed6bac7 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -52,7 +52,109 @@ enum pll_clocks { ANATOP_DRAM_PLL, }; -#ifdef CONFIG_IMX8MN +#ifdef CONFIG_IMX8MP +enum clk_root_index { + ARM_A53_CLK_ROOT = 0, + ARM_M7_CLK_ROOT = 1, + ML_CLK_ROOT = 2, + GPU3D_CORE_CLK_ROOT = 3, + GPU3D_SHADER_CLK_ROOT = 4, + GPU2D_CLK_ROOT = 5, + AUDIO_AXI_CLK_ROOT = 6, + HSIO_AXI_CLK_ROOT = 7, + MEDIA_ISP_CLK_ROOT = 8, + MAIN_AXI_CLK_ROOT = 16, + ENET_AXI_CLK_ROOT = 17, + NAND_USDHC_BUS_CLK_ROOT = 18, + VPU_BUS_CLK_ROOT = 19, + MEDIA_AXI_CLK_ROOT = 20, + MEDIA_APB_CLK_ROOT = 21, + HDMI_APB_CLK_ROOT = 22, + HDMI_AXI_CLK_ROOT = 23, + GPU_AXI_CLK_ROOT = 24, + GPU_AHB_CLK_ROOT = 25, + NOC_CLK_ROOT = 26, + NOC_IO_CLK_ROOT = 27, + ML_AXI_CLK_ROOT = 28, + ML_AHB_CLK_ROOT = 29, + AHB_CLK_ROOT = 32, + IPG_CLK_ROOT = 33, + AUDIO_AHB_CLK_ROOT = 34, + MIPI_DSI_ESC_RX_CLK_ROOT = 36, + MEDIA_DISP2_CLK_ROOT = 38, + DRAM_SEL_CFG = 48, + CORE_SEL_CFG = 49, + DRAM_ALT_CLK_ROOT = 64, + DRAM_APB_CLK_ROOT = 65, + VPU_G1_CLK_ROOT = 66, + VPU_G2_CLK_ROOT = 67, + CAN1_CLK_ROOT = 68, + CAN2_CLK_ROOT = 69, + PCIE_PHY_CLK_ROOT = 71, + PCIE_AUX_CLK_ROOT = 72, + I2C5_CLK_ROOT = 73, + I2C6_CLK_ROOT = 74, + SAI1_CLK_ROOT = 75, + SAI2_CLK_ROOT = 76, + SAI3_CLK_ROOT = 77, + SAI4_CLK_ROOT = 78, + SAI5_CLK_ROOT = 79, + SAI6_CLK_ROOT = 80, + ENET_QOS_CLK_ROOT = 81, + ENET_QOS_TIMER_CLK_ROOT = 82, + ENET_REF_CLK_ROOT = 83, + ENET_TIMER_CLK_ROOT = 84, + ENET_PHY_REF_CLK_ROOT = 85, + NAND_CLK_ROOT = 86, + QSPI_CLK_ROOT = 87, + USDHC1_CLK_ROOT = 88, + USDHC2_CLK_ROOT = 89, + I2C1_CLK_ROOT = 90, + I2C2_CLK_ROOT = 91, + I2C3_CLK_ROOT = 92, + I2C4_CLK_ROOT = 93, + UART1_CLK_ROOT = 94, + UART2_CLK_ROOT = 95, + UART3_CLK_ROOT = 96, + UART4_CLK_ROOT = 97, + USB_CORE_REF_CLK_ROOT = 98, + USB_PHY_REF_CLK_ROOT = 99, + GIC_CLK_ROOT = 100, + ECSPI1_CLK_ROOT = 101, + ECSPI2_CLK_ROOT = 102, + PWM1_CLK_ROOT = 103, + PWM2_CLK_ROOT = 104, + PWM3_CLK_ROOT = 105, + PWM4_CLK_ROOT = 106, + GPT1_CLK_ROOT = 107, + GPT2_CLK_ROOT = 108, + GPT3_CLK_ROOT = 109, + GPT4_CLK_ROOT = 110, + GPT5_CLK_ROOT = 111, + GPT6_CLK_ROOT = 112, + TRACE_CLK_ROOT = 113, + WDOG_CLK_ROOT = 114, + WRCLK_CLK_ROOT = 115, + IPP_DO_CLKO1 = 116, + IPP_DO_CLKO2 = 117, + HDMI_FDCC_TST_CLK_ROOT = 118, + HDMI_27M_CLK_ROOT = 119, + HDMI_REF_266M_CLK_ROOT = 120, + USDHC3_CLK_ROOT = 121, + MEDIA_CAM1_PIX_CLK_ROOT = 122, + MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123, + MEDIA_DISP1_PIX_CLK_ROOT = 124, + MEDIA_CAM2_PIX_CLK_ROOT = 125, + MEDIA_LDB_CLK_ROOT = 126, + MEMREPAIR_CLK_ROOT = 127, + MEDIA_MIPI_TEST_BYTE_CLK = 130, + ECSPI3_CLK_ROOT = 131, + PDM_CLK_ROOT = 132, + VPU_VC8000E_CLK_ROOT = 133, + SAI7_CLK_ROOT = 134, + CLK_ROOT_MAX, +}; +#elif defined(CONFIG_IMX8MN) enum clk_root_index { ARM_A53_CLK_ROOT = 0, ARM_M7_CLK_ROOT = 1, @@ -284,6 +386,7 @@ enum clk_ccgr_index { CCGR_GPT2 = 17, CCGR_GPT3 = 18, CCGR_GPT4 = 19, + CCGR_AAM_8MP = 20, CCGR_GPT5 = 20, CCGR_GPT6 = 21, CCGR_HS = 22, @@ -315,7 +418,9 @@ enum clk_ccgr_index { CCGR_RAWNAND = 48, CCGR_RDC = 49, CCGR_ROM = 50, + CCGR_I2C5_8MP = 51, CCGR_SAI1 = 51, + CCGR_I2C6_8MP = 52, CCGR_SAI2 = 52, CCGR_SAI3 = 53, CCGR_SAI4 = 54, @@ -327,13 +432,16 @@ enum clk_ccgr_index { CCGR_SEC_DEBUG = 60, CCGR_SEMA1 = 61, CCGR_SEMA2 = 62, + CCGR_IRQ_STEER_8MP = 63, CCGR_SIM_DISPLAY = 63, CCGR_SIM_ENET = 64, CCGR_SIM_M = 65, CCGR_SIM_MAIN = 66, CCGR_SIM_S = 67, CCGR_SIM_WAKEUP = 68, + CCGR_GPU2D_8MP = 69, CCGR_SIM_HSIO = 69, + CCGR_GPU3D_8MP = 70, CCGR_SIM_VPU = 70, CCGR_SNVS = 71, CCGR_TRACE = 72, @@ -342,6 +450,7 @@ enum clk_ccgr_index { CCGR_UART3 = 75, CCGR_UART4 = 76, CCGR_USB_MSCALE_PL301 = 77, + CCGR_USB_PHY_8MP = 79, CCGR_GPU3D = 79, CCGR_USDHC1 = 81, CCGR_USDHC2 = 82, @@ -361,6 +470,7 @@ enum clk_ccgr_index { CCGR_PLL = 97, CCGR_TEMP_SENSOR = 98, CCGR_VPUMIX_BUS = 99, + CCGR_SAI7 = 101, CCGR_GPU2D = 102, CCGR_MAX }; diff --git a/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h new file mode 100644 index 0000000000..e7f3221823 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h @@ -0,0 +1,1080 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MP_PINS_H__ +#define __ASM_ARCH_IMX8MP_PINS_H__ + +#include <asm/mach-imx/iomux-v3.h> + +enum { + MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), + MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__SJC_FAIL = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), + MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__SJC_DE_B = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00 = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SJC_DONE = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01 = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__M7_NMI = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), + MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0), + MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0), + MX8MP_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0), + MX8MP_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDC__ENET_QOS_MDC = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0), + MX8MP_PAD_ENET_MDC__SIM_M_HADDR15 = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0), + MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0), + MX8MP_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0), + MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16 = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0), + MX8MP_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0), + MX8MP_PAD_ENET_TD3__SIM_M_HADDR17 = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0), + MX8MP_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0), + MX8MP_PAD_ENET_TD2__SIM_M_HADDR18 = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0), + MX8MP_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0), + MX8MP_PAD_ENET_TD1__SIM_M_HADDR19 = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0), + MX8MP_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0), + MX8MP_PAD_ENET_TD0__SIM_M_HADDR20 = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0), + MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21 = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0), + MX8MP_PAD_ENET_TXC__SIM_M_HADDR22 = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0), + MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0), + MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23 = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0), + MX8MP_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0), + MX8MP_PAD_ENET_RXC__SIM_M_HADDR24 = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0), + MX8MP_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0), + MX8MP_PAD_ENET_RD0__SIM_M_HADDR25 = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0), + MX8MP_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__SIM_M_HADDR26 = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0), + MX8MP_PAD_ENET_RD2__SIM_M_HADDR27 = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), + MX8MP_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0), + MX8MP_PAD_ENET_RD3__SIM_M_HADDR28 = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__I2C5_SCL = IOMUX_PAD(0x02EC, 0x008C, 3 | IOMUX_CONFIG_SION, 0x05C4, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0), + MX8MP_PAD_SD1_CLK__GPIO2_IO00 = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__SIM_M_HADDR29 = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0), + MX8MP_PAD_SD1_CMD__I2C5_SDA = IOMUX_PAD(0x02F0, 0x0090, 3 | IOMUX_CONFIG_SION, 0x05C8, 0, 0), + MX8MP_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0), + MX8MP_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__GPIO2_IO01 = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__SIM_M_HADDR30 = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__I2C6_SCL = IOMUX_PAD(0x02F4, 0x0094, 3 | IOMUX_CONFIG_SION, 0x05CC, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__GPIO2_IO02 = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31 = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__I2C6_SDA = IOMUX_PAD(0x02F8, 0x0098, 3 | IOMUX_CONFIG_SION, 0x05D0, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0), + MX8MP_PAD_SD1_DATA1__GPIO2_IO03 = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00 = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0), + MX8MP_PAD_SD1_DATA2__I2C4_SCL = IOMUX_PAD(0x02FC, 0x009C, 3 | IOMUX_CONFIG_SION, 0x05BC, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0), + MX8MP_PAD_SD1_DATA2__GPIO2_IO04 = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01 = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0), + MX8MP_PAD_SD1_DATA3__I2C4_SDA = IOMUX_PAD(0x0300, 0x00A0, 3 | IOMUX_CONFIG_SION, 0x05C0, 0, 0), + MX8MP_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0), + MX8MP_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__GPIO2_IO05 = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02 = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0304, 0x00A4, 3 | IOMUX_CONFIG_SION, 0x05A4, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__GPIO2_IO06 = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__SIM_M_HRESP = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0308, 0x00A8, 3 | IOMUX_CONFIG_SION, 0x05A8, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0), + MX8MP_PAD_SD1_DATA5__GPIO2_IO07 = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05 = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0), + MX8MP_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x030C, 0x00AC, 3 | IOMUX_CONFIG_SION, 0x05AC, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0), + MX8MP_PAD_SD1_DATA6__GPIO2_IO08 = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06 = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0), + MX8MP_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x0310, 0x00B0, 3 | IOMUX_CONFIG_SION, 0x05B0, 0, 0), + MX8MP_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0), + MX8MP_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__GPIO2_IO09 = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07 = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0), + MX8MP_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0314, 0x00B4, 3 | IOMUX_CONFIG_SION, 0x05B4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0), + MX8MP_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00 = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0), + MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01 = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0), + MX8MP_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0), + MX8MP_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0), + MX8MP_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02 = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), + MX8MP_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0), + MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0), + MX8MP_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03 = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0), + MX8MP_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04 = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0), + MX8MP_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0), + MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), + MX8MP_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0), + MX8MP_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__GPIO3_IO00 = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__SIM_M_HPROT00 = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0), + MX8MP_PAD_NAND_CE0_B__GPIO3_IO01 = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01 = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0), + MX8MP_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), + MX8MP_PAD_NAND_CE1_B__GPIO3_IO02 = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00 = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02 = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0), + MX8MP_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0), + MX8MP_PAD_NAND_CE2_B__GPIO3_IO03 = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01 = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03 = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0), + MX8MP_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0), + MX8MP_PAD_NAND_CE3_B__GPIO3_IO04 = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02 = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00 = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0), + MX8MP_PAD_NAND_CLE__UART4_DCE_RX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0), + MX8MP_PAD_NAND_CLE__UART4_DTE_TX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__GPIO3_IO05 = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03 = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__SIM_M_HADDR01 = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0), + MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0), + MX8MP_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__GPIO3_IO06 = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02 = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0), + MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0), + MX8MP_PAD_NAND_DATA01__GPIO3_IO07 = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03 = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02 = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0), + MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__UART4_DTE_RTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x05FC, 0, 0), + MX8MP_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0), + MX8MP_PAD_NAND_DATA02__GPIO3_IO08 = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04 = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03 = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0), + MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0), + MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), + MX8MP_PAD_NAND_DATA03__GPIO3_IO09 = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05 = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00 = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04 = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), + MX8MP_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06 = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01 = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05 = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07 = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02 = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06 = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08 = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03 = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07 = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09 = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0), + MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0), + MX8MP_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__SIM_M_HADDR10 = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0), + MX8MP_PAD_NAND_RE_B__UART4_DCE_TX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__UART4_DTE_RX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0), + MX8MP_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11 = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0), + MX8MP_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12 = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0), + MX8MP_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0), + MX8MP_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13 = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0), + MX8MP_PAD_NAND_WP_B__I2C4_SCL = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), + MX8MP_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14 = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0), + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__PWM4_OUT = IOMUX_PAD(0x038C, 0x012C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__I2C6_SCL = IOMUX_PAD(0x038C, 0x012C, 3 | IOMUX_CONFIG_SION, 0x05CC, 1, 0), + MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x038C, 0x012C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x0390, 0x0130, 0, 0x04F4, 0, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__PWM3_OUT = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__I2C6_SDA = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__PWM2_OUT = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__I2C5_SCL = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0), + MX8MP_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0), + MX8MP_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__CAN1_TX = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x039C, 0x013C, 0, 0x0500, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0), + MX8MP_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__CAN1_RX = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0), + + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03A0, 0x0140, 0, 0x0504, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0), + MX8MP_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__CAN2_TX = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03A4, 0x0144, 0, 0x04F0, 0, 0), + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03A4, 0x0144, 1, 0x04D4, 0, 0), + MX8MP_PAD_SAI5_MCLK__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0144, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__I2C5_SDA = IOMUX_PAD(0x03A4, 0x0144, 3 | IOMUX_CONFIG_SION, 0x05C8, 1, 0), + MX8MP_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03A4, 0x0144, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__CAN2_RX = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0), + + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0), + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0), + MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXFS__GPIO4_IO00 = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__GPIO4_IO01 = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0), + MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0), + MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0), + MX8MP_PAD_SAI1_RXD2__ENET1_MDC = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__GPIO4_IO04 = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0), + MX8MP_PAD_SAI1_RXD3__ENET1_MDIO = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0), + MX8MP_PAD_SAI1_RXD3__GPIO4_IO05 = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 = IOMUX_PAD(0x03C0, 0x0160, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 1, 0x0524, 1, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 2, 0x0518, 1, 0), + MX8MP_PAD_SAI1_RXD4__ENET1_RGMII_RD0 = IOMUX_PAD(0x03C0, 0x0160, 4, 0x0580, 1, 0), + MX8MP_PAD_SAI1_RXD4__GPIO4_IO06 = IOMUX_PAD(0x03C0, 0x0160, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 = IOMUX_PAD(0x03C4, 0x0164, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 2, 0x051C, 1, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x0164, 3, 0x04D0, 1, 0), + MX8MP_PAD_SAI1_RXD5__ENET1_RGMII_RD1 = IOMUX_PAD(0x03C4, 0x0164, 4, 0x0584, 1, 0), + MX8MP_PAD_SAI1_RXD5__GPIO4_IO07 = IOMUX_PAD(0x03C4, 0x0164, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 = IOMUX_PAD(0x03C8, 0x0168, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 1, 0x0528, 1, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 2, 0x0520, 1, 0), + MX8MP_PAD_SAI1_RXD6__ENET1_RGMII_RD2 = IOMUX_PAD(0x03C8, 0x0168, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__GPIO4_IO08 = IOMUX_PAD(0x03C8, 0x0168, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 = IOMUX_PAD(0x03CC, 0x016C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03CC, 0x016C, 1, 0x0514, 1, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03CC, 0x016C, 2, 0x04D8, 3, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03CC, 0x016C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__ENET1_RGMII_RD3 = IOMUX_PAD(0x03CC, 0x016C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__GPIO4_IO09 = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0), + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0), + MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0), + MX8MP_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0), + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0), + MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03E8, 0x0188, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 1, 0x0518, 2, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 2, 0x0524, 2, 0), + MX8MP_PAD_SAI1_TXD4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x03E8, 0x0188, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x03E8, 0x0188, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03EC, 0x018C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 1, 0x051C, 2, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__ENET1_RGMII_TXC = IOMUX_PAD(0x03EC, 0x018C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x03EC, 0x018C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 = IOMUX_PAD(0x03F0, 0x0190, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 1, 0x0520, 2, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 2, 0x0528, 2, 0), + MX8MP_PAD_SAI1_TXD6__ENET1_RX_ER = IOMUX_PAD(0x03F0, 0x0190, 4, 0x058C, 1, 0), + MX8MP_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x03F0, 0x0190, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0), + MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0), + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 1, 0x0510, 2, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 3, 0x04DC, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0), + MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0), + MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00 = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0), + MX8MP_PAD_SAI2_RXC__CAN1_TX = IOMUX_PAD(0x0400, 0x01A0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0), + MX8MP_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0), + MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01 = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT = IOMUX_PAD(0x0404, 0x01A4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0404, 0x01A4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0), + MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02 = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT = IOMUX_PAD(0x0408, 0x01A8, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0), + MX8MP_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0), + MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__CAN1_RX = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0), + MX8MP_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0), + MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN = IOMUX_PAD(0x0410, 0x01B0, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CAN2_TX = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__TPSMP_CLK = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN = IOMUX_PAD(0x0414, 0x01B4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__CAN2_RX = IOMUX_PAD(0x0414, 0x01B4, 3, 0x0550, 1, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0), + MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), + MX8MP_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0), + MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00 = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 2, 0x04F4, 2, 0), + MX8MP_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x041C, 0x01BC, 3, 0x059C, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0), + MX8MP_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01 = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 2, 0x04F8, 2, 0), + MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0), + MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0), + MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00 = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 2, 0x04FC, 2, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0), + MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01 = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 2, 0x0500, 2, 0), + MX8MP_PAD_SAI3_TXC__GPT1_CAPTURE1 = IOMUX_PAD(0x0428, 0x01C8, 3, 0x0594, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0), + MX8MP_PAD_SAI3_TXC__GPIO5_IO00 = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0), + MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02 = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0), + MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2 = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), + MX8MP_PAD_SAI3_TXD__GPIO5_IO01 = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03 = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0), + MX8MP_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__GPIO5_IO02 = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), + MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04 = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__I2C5_SCL = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0), + MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1 = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__CAN1_TX = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__GPIO5_IO03 = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), + MX8MP_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__I2C5_SDA = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0), + MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2 = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__CAN1_RX = IOMUX_PAD(0x0438, 0x01D8, 4, 0x054C, 2, 0), + MX8MP_PAD_SPDIF_RX__GPIO5_IO04 = IOMUX_PAD(0x0438, 0x01D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3 = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), + MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x05F8, 4, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06 = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08 = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x05F8, 5, 0), + MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07 = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09 = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DTE_RTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x05F4, 2, 0), + MX8MP_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0), + MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0), + MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08 = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10 = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DTE_CTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0), + MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0), + MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11 = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0), + MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12 = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0600, 7, 0), + MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0), + MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13 = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14 = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0), + MX8MP_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), + MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0), + MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15 = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0), + MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0), + MX8MP_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16 = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0), + MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0), + MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0), + MX8MP_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17 = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0468, 0x0208, 2, 0x0608, 3, 0), + MX8MP_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18 = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0), + MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0), + MX8MP_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0), + MX8MP_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19 = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0), + MX8MP_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0), + MX8MP_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20 = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0), + MX8MP_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0), + MX8MP_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21 = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0), + MX8MP_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), + MX8MP_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0), + MX8MP_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22 = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0), + MX8MP_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0), + MX8MP_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23 = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0), + + MX8MP_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__TPSMP_HDATA24 = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0), + MX8MP_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__TPSMP_HDATA25 = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0), + + MX8MP_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x0488, 0x0228, 0, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__TPSMP_HDATA26 = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x048C, 0x022C, 0, 0x05F0, 7, 0), + MX8MP_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__TPSMP_HDATA27 = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0), + + MX8MP_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x0490, 0x0230, 0, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DCE_CTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DTE_RTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x05E4, 4, 0), + MX8MP_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0230, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0), + MX8MP_PAD_UART3_RXD__CAN2_TX = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__TPSMP_HDATA28 = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x0494, 0x0234, 0, 0x05F8, 7, 0), + MX8MP_PAD_UART3_TXD__UART1_DCE_RTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x05E4, 5, 0), + MX8MP_PAD_UART3_TXD__UART1_DTE_CTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x0494, 0x0234, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0), + MX8MP_PAD_UART3_TXD__CAN2_RX = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0), + MX8MP_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__TPSMP_HDATA29 = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0), + + MX8MP_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DCE_CTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DTE_RTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0), + MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), + MX8MP_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__I2C6_SCL = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0), + MX8MP_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__TPSMP_HDATA30 = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0600, 9, 0), + MX8MP_PAD_UART4_TXD__UART2_DCE_RTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x05EC, 5, 0), + MX8MP_PAD_UART4_TXD__UART2_DTE_CTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0), + MX8MP_PAD_UART4_TXD__I2C6_SDA = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), + MX8MP_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__TPSMP_HDATA31 = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0), + MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26 = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00 = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27 = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01 = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__I2C6_SCL = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0), + MX8MP_PAD_HDMI_CEC__CAN2_TX = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__GPIO3_IO28 = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__I2C6_SDA = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0), + MX8MP_PAD_HDMI_HPD__CAN2_RX = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0), + MX8MP_PAD_HDMI_HPD__GPIO3_IO29 = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX8MP_PINS_H__ */ diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 3d5586ed4f..06dbd8d943 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -104,7 +104,7 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE (0x1 << 5) #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) -#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) #define PAD_CTL_PE (0x1 << 8) #else #define PAD_CTL_LVTTL (0x1 << 8) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index fff4800808..35b39b1f86 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -54,6 +54,7 @@ #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN)) +#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4ce2799b72..aa140c4798 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -112,7 +112,7 @@ config DDRMC_VF610_CALIBRATION config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" - depends on IMX8MN + depends on IMX8MN || IMX8MP config IMX_DCD_ADDR hex "DCD Blocks location on the image" @@ -123,4 +123,3 @@ config IMX_DCD_ADDR the ROM code to configure the device at early boot stage, is located. This information is shared with the user via mkimage -l just so the image can be signed. - diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 51c7c05f04..bfa85c64c6 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -92,6 +92,8 @@ static char *get_reset_cause(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_IMX8MP: + return "8MP"; /* Quad-core version of the imx8mp */ case MXC_CPU_IMX8MN: return "8MNano";/* Quad-core version of the imx8mn */ case MXC_CPU_IMX8MM: @@ -157,7 +159,7 @@ int print_cpuinfo(void) int cpu_tmp, minc, maxc, ret; printf("CPU: Freescale i.MX%s rev%d.%d", - get_imx_type((cpurev & 0xFF000) >> 12), + get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); max_freq = get_cpu_speed_grade_hz(); @@ -169,7 +171,7 @@ int print_cpuinfo(void) } #else printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index eb4a73b3e2..72affb1bdc 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -16,6 +16,10 @@ config IMX8MN bool select IMX8M +config IMX8MP + bool + select IMX8M + config SYS_SOC default "imx8m" @@ -40,10 +44,17 @@ config TARGET_IMX8MN_EVK select SUPPORT_SPL select IMX8M_DDR4 +config TARGET_IMX8MP_EVK + bool "imx8mp LPDDR4 EVK board" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" +source "board/freescale/imx8mp_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile index db4ba30c24..d9dee894aa 100644 --- a/arch/arm/mach-imx/imx8m/Makefile +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -5,4 +5,4 @@ obj-y += lowlevel_init.o obj-y += clock_slice.o soc.o obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o -obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN) += clock_imx8mm.o +obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index ee44ba75fe..ca4b4c05ab 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -10,9 +10,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> -#include <clk.h> -#include <clk-uclass.h> -#include <dt-bindings/clock/imx8mm-clock.h> #include <div64.h> #include <errno.h> @@ -22,34 +19,23 @@ static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; void enable_ocotp_clk(unsigned char enable) { - struct clk *clkp; - int ret; - - ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp); - if (ret) { - printf("%s: err: %d\n", __func__, ret); - return; - } - - enable ? clk_enable(clkp) : clk_disable(clkp); + clock_enable(CCGR_OCOTP, !!enable); } int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { - struct clk *clkp; - int ret; + /* 0 - 3 is valid i2c num */ + if (i2c_num > 3) + return -EINVAL; - ret = clk_get_by_id(IMX8MM_CLK_I2C1_ROOT + i2c_num, &clkp); - if (ret) { - printf("%s: err: %d\n", __func__, ret); - return ret; - } + clock_enable(CCGR_I2C1 + i2c_num, !!enable); - return enable ? clk_enable(clkp) : clk_disable(clkp); + return 0; } #ifdef CONFIG_SPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { + PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), @@ -282,24 +268,312 @@ u32 imx_get_uartclk(void) return 24000000U; } +u32 decode_intpll(enum clk_root_src intpll) +{ + u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask; + u32 main_div, pre_div, post_div, div; + u64 freq; + + switch (intpll) { + case ARM_PLL_CLK: + pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl); + break; + case GPU_PLL_CLK: + pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl); + break; + case VPU_PLL_CLK: + pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl); + break; + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl); + break; + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl); + break; + case SYSTEM_PLL3_CLK: + pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl); + pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl); + break; + default: + return -EINVAL; + } + + /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + return 0; + + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + return 0; + + /* + * When BYPASS is equal to 1, PLL enters the bypass mode + * regardless of the values of RESETB + */ + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + return 24000000u; + + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + puts("pll not locked\n"); + return 0; + } + + switch (intpll) { + case ARM_PLL_CLK: + case GPU_PLL_CLK: + case VPU_PLL_CLK: + case SYSTEM_PLL3_CLK: + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL2_1000M_CLK: + pll_clke_mask = INTPLL_CLKE_MASK; + div = 1; + break; + + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL2_500M_CLK: + pll_clke_mask = INTPLL_DIV2_CLKE_MASK; + div = 2; + break; + + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL2_333M_CLK: + pll_clke_mask = INTPLL_DIV3_CLKE_MASK; + div = 3; + break; + + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL2_250M_CLK: + pll_clke_mask = INTPLL_DIV4_CLKE_MASK; + div = 4; + break; + + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL2_200M_CLK: + pll_clke_mask = INTPLL_DIV5_CLKE_MASK; + div = 5; + break; + + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL2_166M_CLK: + pll_clke_mask = INTPLL_DIV6_CLKE_MASK; + div = 6; + break; + + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL2_125M_CLK: + pll_clke_mask = INTPLL_DIV8_CLKE_MASK; + div = 8; + break; + + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL2_100M_CLK: + pll_clke_mask = INTPLL_DIV10_CLKE_MASK; + div = 10; + break; + + case SYSTEM_PLL1_40M_CLK: + case SYSTEM_PLL2_50M_CLK: + pll_clke_mask = INTPLL_DIV20_CLKE_MASK; + div = 20; + break; + default: + return -EINVAL; + } + + if ((pll_gnrl_ctl & pll_clke_mask) == 0) + return 0; + + main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >> + INTPLL_MAIN_DIV_SHIFT; + pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >> + INTPLL_PRE_DIV_SHIFT; + post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >> + INTPLL_POST_DIV_SHIFT; + + /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */ + freq = 24000000ULL * main_div; + return lldiv(freq, pre_div * (1 << post_div) * div); +} + +u32 decode_fracpll(enum clk_root_src frac_pll) +{ + u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; + u32 main_div, pre_div, post_div, k; + + switch (frac_pll) { + case DRAM_PLL1_CLK: + pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl); + pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0); + pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1); + break; + case AUDIO_PLL1_CLK: + pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl); + pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0); + pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1); + break; + case AUDIO_PLL2_CLK: + pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl); + pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0); + pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1); + break; + case VIDEO_PLL_CLK: + pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl); + pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0); + pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1); + break; + default: + printf("Not supported\n"); + return 0; + } + + /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ + if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + return 0; + + if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + return 0; + /* + * When BYPASS is equal to 1, PLL enters the bypass mode + * regardless of the values of RESETB + */ + if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + return 24000000u; + + if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + puts("pll not locked\n"); + return 0; + } + + if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK)) + return 0; + + main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >> + INTPLL_MAIN_DIV_SHIFT; + pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >> + INTPLL_PRE_DIV_SHIFT; + post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >> + INTPLL_POST_DIV_SHIFT; + + k = pll_fdiv_ctl1 & GENMASK(15, 0); + + return lldiv((main_div * 65536 + k) * 24000000ULL, + 65536 * pre_div * (1 << post_div)); +} + +u32 get_root_src_clk(enum clk_root_src root_src) +{ + switch (root_src) { + case OSC_24M_CLK: + return 24000000u; + case OSC_HDMI_CLK: + return 26000000u; + case OSC_32K_CLK: + return 32000u; + case ARM_PLL_CLK: + case GPU_PLL_CLK: + case VPU_PLL_CLK: + case SYSTEM_PLL1_800M_CLK: + case SYSTEM_PLL1_400M_CLK: + case SYSTEM_PLL1_266M_CLK: + case SYSTEM_PLL1_200M_CLK: + case SYSTEM_PLL1_160M_CLK: + case SYSTEM_PLL1_133M_CLK: + case SYSTEM_PLL1_100M_CLK: + case SYSTEM_PLL1_80M_CLK: + case SYSTEM_PLL1_40M_CLK: + case SYSTEM_PLL2_1000M_CLK: + case SYSTEM_PLL2_500M_CLK: + case SYSTEM_PLL2_333M_CLK: + case SYSTEM_PLL2_250M_CLK: + case SYSTEM_PLL2_200M_CLK: + case SYSTEM_PLL2_166M_CLK: + case SYSTEM_PLL2_125M_CLK: + case SYSTEM_PLL2_100M_CLK: + case SYSTEM_PLL2_50M_CLK: + case SYSTEM_PLL3_CLK: + return decode_intpll(root_src); + case DRAM_PLL1_CLK: + case AUDIO_PLL1_CLK: + case AUDIO_PLL2_CLK: + case VIDEO_PLL_CLK: + return decode_fracpll(root_src); + default: + return 0; + } + + return 0; +} + +u32 get_root_clk(enum clk_root_index clock_id) +{ + enum clk_root_src root_src; + u32 post_podf, pre_podf, root_src_clk; + + if (clock_root_enabled(clock_id) <= 0) + return 0; + + if (clock_get_prediv(clock_id, &pre_podf) < 0) + return 0; + + if (clock_get_postdiv(clock_id, &post_podf) < 0) + return 0; + + if (clock_get_src(clock_id, &root_src) < 0) + return 0; + + root_src_clk = get_root_src_clk(root_src); + + return root_src_clk / (post_podf + 1) / (pre_podf + 1); +} + u32 mxc_get_clock(enum mxc_clock clk) { - struct clk *clkp; - int ret; + u32 val; switch (clk) { - case MXC_IPG_CLK: - ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp); - if (ret) - return 0; - return clk_get_rate(clkp); case MXC_ARM_CLK: - ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp); - if (ret) - return 0; - return clk_get_rate(clkp); + return get_root_clk(ARM_A53_CLK_ROOT); + case MXC_IPG_CLK: + clock_get_target_val(IPG_CLK_ROOT, &val); + val = val & 0x3; + return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1); + case MXC_CSPI_CLK: + return get_root_clk(ECSPI1_CLK_ROOT); + case MXC_ESDHC_CLK: + return get_root_clk(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return get_root_clk(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return get_root_clk(USDHC3_CLK_ROOT); + case MXC_I2C_CLK: + return get_root_clk(I2C1_CLK_ROOT); + case MXC_UART_CLK: + return get_root_clk(UART1_CLK_ROOT); + case MXC_QSPI_CLK: + return get_root_clk(QSPI_CLK_ROOT); default: - printf("%s: %d not supported\n", __func__, clk); + printf("Unsupported mxc_clock %d\n", clk); + break; } return 0; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 2db5bde211..878f2be166 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -326,16 +326,20 @@ unsigned int mxc_get_clock(enum mxc_clock clk) { u32 val; - if (clk == MXC_ARM_CLK) + switch(clk) { + case MXC_ARM_CLK: return get_root_clk(ARM_A53_CLK_ROOT); - - if (clk == MXC_IPG_CLK) { + case MXC_IPG_CLK: clock_get_target_val(IPG_CLK_ROOT, &val); val = val & 0x3; return get_root_clk(AHB_CLK_ROOT) / (val + 1); + case MXC_ESDHC_CLK: + return get_root_clk(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return get_root_clk(USDHC2_CLK_ROOT); + default: + return get_root_clk(clk); } - - return get_root_clk(clk); } u32 imx_get_uartclk(void) diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 09c5615004..31925ccaba 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -538,6 +538,278 @@ static struct clk_root_map root_array[] = { {DRAM_PLL1_CLK} }, }; +#elif defined(CONFIG_IMX8MP) +static struct clk_root_map root_array[] = { + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} + }, + {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2, + EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} + }, + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK} + }, + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_133M_CLK} + }, + {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_133M_CLK} + }, + {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_133M_CLK} + }, + {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1, + EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK} + }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1, + EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK} + }, + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3} + }, + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} + }, + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51, + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, +}; #endif static int select(enum clk_root_index clock_id) diff --git a/arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..586a5ff306 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +ROM_VERSION v2 +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x920000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5ce5a180e8..7fcbd53f30 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -57,7 +57,7 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); - if (is_imx8mm() || is_imx8mn()) + if (is_imx8mm() || is_imx8mn() || is_imx8mp()) setbits_le32(&gpr->gpr[10], BIT(1)); /* * set Region 0 attribute to allow secure and non-secure @@ -197,8 +197,11 @@ u32 get_cpu_rev(void) reg &= 0xff; - /* i.MX8MM */ - if (major_low == 0x42) { + /* iMX8MP */ + if (major_low == 0x43) { + return (MXC_CPU_IMX8MP << 12) | reg; + } else if (major_low == 0x42) { + /* iMX8MN */ return (MXC_CPU_IMX8MN << 12) | reg; } else if (major_low == 0x41) { type = get_cpu_variant_type(MXC_CPU_IMX8MM); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index dde1635a9d..5a6493a625 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -135,7 +135,8 @@ u32 spl_boot_device(void) enum boot_device boot_device_spl = get_boot_device(); - if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN)) + if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) || + IS_ENABLED(CONFIG_IMX8MP)) return spl_board_boot_device(boot_device_spl); switch (boot_device_spl) { diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index e29e4c0acc..513a33dae2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -8,6 +8,7 @@ config MESON64_COMMON select DM_SERIAL select SYSCON select REGMAP + select PWRSEQ select BOARD_LATE_INIT imply CMD_DM diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 3770e07258..969698c83f 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -29,6 +29,15 @@ config SYS_TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_AGILEX + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select ARMV8_SPIN_TABLE + select CLK + select NCORE_CACHE + select SPL_CLK if SPL + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -75,6 +84,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_AGILEX_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex)" + select TARGET_SOCFPGA_AGILEX + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -135,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -151,6 +165,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -168,6 +183,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index fc1181cb27..418f543b20 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -39,6 +39,18 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += clock_manager_agilex.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += timer_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o +endif + ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o @@ -51,8 +63,13 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += firewall.o obj-y += spl_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += firewall.o +obj-y += spl_agilex.o +endif endif ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9f3c643df8..dbb10ecb68 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -10,18 +10,17 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; - void cm_wait_for_lock(u32 mask) { u32 inter_val; u32 retry = 0; do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) - inter_val = readl(&clock_manager_base->inter) & mask; + inter_val = readl(socfpga_get_clkmgr_addr() + + CLKMGR_INTER) & mask; #else - inter_val = readl(&clock_manager_base->stat) & mask; + inter_val = readl(socfpga_get_clkmgr_addr() + + CLKMGR_STAT) & mask; #endif /* Wait for stable lock */ if (inter_val == mask) @@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ int cm_wait_for_fsm(void) { - return wait_for_bit_le32(&clock_manager_base->stat, - CLKMGR_STAT_BUSY, false, 20000, false); + return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000, + false); } int set_cpu_clk_info(void) diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c new file mode 100644 index 0000000000..791066d25b --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <dt-bindings/clock/agilex-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(socfpga_agilex_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK); +} + +u32 cm_get_qspi_controller_clk_hz(void) +{ + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(AGILEX_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(AGILEX_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 334a79fd9c..392f2eb915 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, return 0; } -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; - /* calculate the intended main VCO frequency based on handoff */ static unsigned int cm_calc_handoff_main_vco_clk_hz (struct mainpll_cfg *main_cfg) @@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), - &clock_manager_base->main_pll.vco1); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); mdelay(1); cm_wait_for_lock(LOCKED_MASK); } writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | - main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); + main_cfg->vco1_numer, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); mdelay(1); cm_wait_for_lock(LOCKED_MASK); } @@ -579,14 +577,18 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, /* execute the ramping here */ for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | - cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), - &clock_manager_base->per_pll.vco1); + writel((per_cfg->vco1_denom << + CLKMGR_PERPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(1, main_cfg, per_cfg, + clk_hz), + socfpga_get_clkmgr_addr() + + CLKMGR_A10_PERPLL_VCO1); mdelay(1); cm_wait_for_lock(LOCKED_MASK); } writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | - per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); + per_cfg->vco1_numer, + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); mdelay(1); cm_wait_for_lock(LOCKED_MASK); } @@ -638,16 +640,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) /* gate off all mainpll clock excpet HW managed clock */ writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, - &clock_manager_base->main_pll.enr); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR); /* now we can gate off the rest of the peripheral clocks */ - writel(0, &clock_manager_base->per_pll.en); + writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN); /* Put all plls in external bypass */ writel(CLKMGR_MAINPLL_BYPASS_RESET, - &clock_manager_base->main_pll.bypasss); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS); writel(CLKMGR_PERPLL_BYPASS_RESET, - &clock_manager_base->per_pll.bypasss); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS); /* * Put all plls VCO registers back to reset value. @@ -657,15 +659,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) writel(CLKMGR_MAINPLL_VCO0_RESET | CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), - &clock_manager_base->main_pll.vco0); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0); writel(CLKMGR_PERPLL_VCO0_RESET | CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), - &clock_manager_base->per_pll.vco0); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0); - writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); - writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); + writel(CLKMGR_MAINPLL_VCO1_RESET, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); + writel(CLKMGR_PERPLL_VCO1_RESET, + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); /* clear the interrupt register status register */ writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | @@ -676,7 +680,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, - &clock_manager_base->intr); + socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR); /* Program VCO Numerator and Denominator for main PLL */ ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); @@ -687,14 +691,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) else if (ramp_required == 2) pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + writel((main_cfg->vco1_denom << + CLKMGR_MAINPLL_VCO1_DENOM_LSB) | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, pll_ramp_main_hz), - &clock_manager_base->main_pll.vco1); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); } else - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | - main_cfg->vco1_numer, - &clock_manager_base->main_pll.vco1); + writel((main_cfg->vco1_denom << + CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); /* Program VCO Numerator and Denominator for periph PLL */ ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); @@ -707,23 +713,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) pll_ramp_periph_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + writel((per_cfg->vco1_denom << + CLKMGR_PERPLL_VCO1_DENOM_LSB) | cm_calc_safe_pll_numer(1, main_cfg, per_cfg, pll_ramp_periph_hz), - &clock_manager_base->per_pll.vco1); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); } else - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + writel((per_cfg->vco1_denom << + CLKMGR_PERPLL_VCO1_DENOM_LSB) | per_cfg->vco1_numer, - &clock_manager_base->per_pll.vco1); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); /* Wait for at least 5 us */ udelay(5); /* Now deassert BGPWRDN and PWRDN */ - clrbits_le32(&clock_manager_base->main_pll.vco0, + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); - clrbits_le32(&clock_manager_base->per_pll.vco0, + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); @@ -731,84 +739,92 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) udelay(7); /* enable the VCO and disable the external regulator to PLL */ - writel((readl(&clock_manager_base->main_pll.vco0) & + writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) & ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | CLKMGR_MAINPLL_VCO0_EN_SET_MSK, - &clock_manager_base->main_pll.vco0); - writel((readl(&clock_manager_base->per_pll.vco0) & + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0); + writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) & ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | CLKMGR_PERPLL_VCO0_EN_SET_MSK, - &clock_manager_base->per_pll.vco0); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0); /* setup all the main PLL counter and clock source */ writel(main_cfg->nocclk, - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); + socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK); writel(main_cfg->mpuclk, - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); + socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK); /* main_emaca_clk divider */ - writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); + writel(main_cfg->cntr2clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK); /* main_emacb_clk divider */ - writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); + writel(main_cfg->cntr3clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK); /* main_emac_ptp_clk divider */ - writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); + writel(main_cfg->cntr4clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK); /* main_gpio_db_clk divider */ - writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); + writel(main_cfg->cntr5clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK); /* main_sdmmc_clk divider */ - writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); + writel(main_cfg->cntr6clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK); /* main_s2f_user0_clk divider */ writel(main_cfg->cntr7clk_cnt | (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), - &clock_manager_base->main_pll.cntr7clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK); /* main_s2f_user1_clk divider */ - writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); + writel(main_cfg->cntr8clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK); /* main_hmc_pll_clk divider */ writel(main_cfg->cntr9clk_cnt | (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), - &clock_manager_base->main_pll.cntr9clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK); /* main_periph_ref_clk divider */ writel(main_cfg->cntr15clk_cnt, - &clock_manager_base->main_pll.cntr15clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK); /* setup all the peripheral PLL counter and clock source */ /* peri_emaca_clk divider */ writel(per_cfg->cntr2clk_cnt | (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr2clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK); /* peri_emacb_clk divider */ writel(per_cfg->cntr3clk_cnt | (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr3clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK); /* peri_emac_ptp_clk divider */ writel(per_cfg->cntr4clk_cnt | (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr4clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK); /* peri_gpio_db_clk divider */ writel(per_cfg->cntr5clk_cnt | (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr5clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK); /* peri_sdmmc_clk divider */ writel(per_cfg->cntr6clk_cnt | (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr6clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK); /* peri_s2f_user0_clk divider */ - writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); + writel(per_cfg->cntr7clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK); /* peri_s2f_user1_clk divider */ writel(per_cfg->cntr8clk_cnt | (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), - &clock_manager_base->per_pll.cntr8clk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK); /* peri_hmc_pll_clk divider */ - writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); + writel(per_cfg->cntr9clk_cnt, + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK); /* setup all the external PLL counter */ /* mpu wrapper / external divider */ writel(main_cfg->mpuclk_cnt | (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), - &clock_manager_base->main_pll.mpuclk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK); /* NOC wrapper / external divider */ writel(main_cfg->nocclk_cnt | (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), - &clock_manager_base->main_pll.nocclk); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK); /* NOC subclock divider such as l4 */ writel(main_cfg->nocdiv_l4mainclk | (main_cfg->nocdiv_l4mpclk << @@ -821,10 +837,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | (main_cfg->nocdiv_cspdbclk << CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), - &clock_manager_base->main_pll.nocdiv); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV); /* gpio_db external divider */ writel(per_cfg->gpiodiv_gpiodbclk, - &clock_manager_base->per_pll.gpiodiv); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV); /* setup the EMAC clock mux select */ writel((per_cfg->emacctl_emac0sel << @@ -833,7 +849,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | (per_cfg->emacctl_emac2sel << CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), - &clock_manager_base->per_pll.emacctl); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL); /* at this stage, check for PLL lock status */ cm_wait_for_lock(LOCKED_MASK); @@ -843,33 +859,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) * assert/deassert outresetall */ /* assert mainpll outresetall */ - setbits_le32(&clock_manager_base->main_pll.vco0, + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); /* assert perpll outresetall */ - setbits_le32(&clock_manager_base->per_pll.vco0, + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); /* de-assert mainpll outresetall */ - clrbits_le32(&clock_manager_base->main_pll.vco0, + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); /* de-assert perpll outresetall */ - clrbits_le32(&clock_manager_base->per_pll.vco0, + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); /* Take all PLLs out of bypass when boot mode is cleared. */ /* release mainpll from bypass */ writel(CLKMGR_MAINPLL_BYPASS_RESET, - &clock_manager_base->main_pll.bypassr); + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR); /* wait till Clock Manager is not busy */ cm_wait_for_fsm(); /* release perpll from bypass */ writel(CLKMGR_PERPLL_BYPASS_RESET, - &clock_manager_base->per_pll.bypassr); + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR); /* wait till Clock Manager is not busy */ cm_wait_for_fsm(); /* clear boot mode */ - clrbits_le32(&clock_manager_base->ctrl, + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL, CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); /* wait till Clock Manager is not busy */ cm_wait_for_fsm(); @@ -882,9 +898,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) /* Now ungate non-hw-managed clocks */ writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | - CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, - &clock_manager_base->main_pll.ens); - writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS); + writel(CLKMGR_PERPLL_EN_RESET, + socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS); /* Clear the loss lock and slip bits as they might set during clock reconfiguration */ @@ -894,14 +911,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, - &clock_manager_base->intr); + socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR); return 0; } static void cm_use_intosc(void) { - setbits_le32(&clock_manager_base->ctrl, + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL, CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); } diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 54a821a27f..8fa2760798 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -10,23 +10,20 @@ #include <asm/arch/clock_manager.h> #include <wait_bit.h> -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; - /* * function to write the bypass register which requires a poll of the * busy bit */ static void cm_write_bypass(u32 val) { - writel(val, &clock_manager_base->bypass); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ static void cm_write_ctrl(u32 val) { - writel(val, &clock_manager_base->ctrl); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL); cm_wait_for_fsm(); } @@ -80,8 +77,8 @@ int cm_basic_init(const struct cm_config * const cfg) * gatting off the rest of the periperal clocks. */ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & - readl(&clock_manager_base->per_pll.en), - &clock_manager_base->per_pll.en); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN), + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | @@ -90,12 +87,12 @@ int cm_basic_init(const struct cm_config * const cfg) CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, - &clock_manager_base->main_pll.en); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN); - writel(0, &clock_manager_base->sdr_pll.en); + writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN); /* now we can gate off the rest of the peripheral clocks */ - writel(0, &clock_manager_base->per_pll.en); + writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); /* Put all plls in bypass */ cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | @@ -104,13 +101,13 @@ int cm_basic_init(const struct cm_config * const cfg) /* Put all plls VCO registers back to reset value. */ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * The clocks to the flash devices and the L4_MAIN clocks can @@ -120,23 +117,26 @@ int cm_basic_init(const struct cm_config * const cfg) * after exiting safe mode but before ungating the clocks. */ writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, - &clock_manager_base->per_pll.src); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, - &clock_manager_base->main_pll.l4src); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); /* read back for the required 5 us delay. */ - readl(&clock_manager_base->main_pll.vco); - readl(&clock_manager_base->per_pll.vco); - readl(&clock_manager_base->sdr_pll.vco); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); - writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); - writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); + writel(cfg->peri_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); + writel(cfg->sdram_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * Time starts here. Must wait 7 us from @@ -145,44 +145,55 @@ int cm_basic_init(const struct cm_config * const cfg) end = timer_get_us() + 7; /* main mpu */ - writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); + writel(cfg->mpuclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK); /* altera group mpuclk */ - writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); + writel(cfg->altera_grp_mpuclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK); /* main main clock */ - writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); + writel(cfg->mainclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK); /* main for dbg */ - writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); + writel(cfg->dbgatclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK); /* main for cfgs2fuser0clk */ writel(cfg->cfg2fuser0clk, - &clock_manager_base->main_pll.cfgs2fuser0clk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK); /* Peri emac0 50 MHz default to RMII */ - writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); + writel(cfg->emac0clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK); /* Peri emac1 50 MHz default to RMII */ - writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); + writel(cfg->emac1clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK); /* Peri QSPI */ - writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); + writel(cfg->mainqspiclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK); - writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); + writel(cfg->perqspiclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK); /* Peri pernandsdmmcclk */ writel(cfg->mainnandsdmmcclk, - &clock_manager_base->main_pll.mainnandsdmmcclk); + socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK); writel(cfg->pernandsdmmcclk, - &clock_manager_base->per_pll.pernandsdmmcclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK); /* Peri perbaseclk */ - writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); + writel(cfg->perbaseclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK); /* Peri s2fuser1clk */ - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); + writel(cfg->s2fuser1clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK); /* 7 us must have elapsed before we can enable the VCO */ while (timer_get_us() < end) @@ -191,101 +202,112 @@ int cm_basic_init(const struct cm_config * const cfg) /* Enable vco */ /* main pll vco */ writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); /* periferal pll */ writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* sdram pll vco */ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* L3 MP and L3 SP */ - writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); + writel(cfg->maindiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV); - writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); + writel(cfg->dbgdiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV); - writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); + writel(cfg->tracediv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV); /* L4 MP, L4 SP, can0, and can1 */ - writel(cfg->perdiv, &clock_manager_base->per_pll.div); + writel(cfg->perdiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV); - writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); + writel(cfg->gpiodiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV); cm_wait_for_lock(LOCKED_MASK); /* write the sdram clock counters before toggling outreset all */ writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqsclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddr2xdqsclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK); writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK); writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, - &clock_manager_base->sdr_pll.s2fuser2clk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK); /* * after locking, but before taking out of bypass * assert/deassert outresetall */ - u32 mainvco = readl(&clock_manager_base->main_pll.vco); + u32 mainvco = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_VCO); /* assert main outresetall */ writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); - u32 periphvco = readl(&clock_manager_base->per_pll.vco); + u32 periphvco = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_VCO); /* assert pheriph outresetall */ writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* deassert main outresetall */ writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); /* deassert pheriph outresetall */ writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* deassert sdram outresetall */ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * now that we've toggled outreset all, all the clocks * are aligned nicely; so we can change any phase. */ ret = cm_write_with_phase(cfg->ddrdqsclk, - &clock_manager_base->sdr_pll.ddrdqsclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDRDQSCLK), CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); if (ret) return ret; /* SDRAM DDR2XDQSCLK */ ret = cm_write_with_phase(cfg->ddr2xdqsclk, - &clock_manager_base->sdr_pll.ddr2xdqsclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK), CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->ddrdqclk, - &clock_manager_base->sdr_pll.ddrdqclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDRDQCLK), CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->s2fuser2clk, - &clock_manager_base->sdr_pll.s2fuser2clk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK), CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); if (ret) return ret; @@ -294,24 +316,28 @@ int cm_basic_init(const struct cm_config * const cfg) cm_write_bypass(0); /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); + cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) | + CLKMGR_CTRL_SAFEMODE); /* * now that safe mode is clear with clocks gated * it safe to change the source mux for the flashes the the L4_MAIN */ - writel(cfg->persrc, &clock_manager_base->per_pll.src); - writel(cfg->l4src, &clock_manager_base->main_pll.l4src); + writel(cfg->persrc, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); + writel(cfg->l4src, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); /* Now ungate non-hw-managed clocks */ - writel(~0, &clock_manager_base->main_pll.en); - writel(~0, &clock_manager_base->per_pll.en); - writel(~0, &clock_manager_base->sdr_pll.en); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN); /* Clear the loss of lock bits (write 1 to clear) */ - writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | - CLKMGR_INTER_MAINPLLLOST_MASK, - &clock_manager_base->inter); + writel(CLKMGR_INTER_SDRPLLLOST_MASK | + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER); return 0; } @@ -321,7 +347,7 @@ static unsigned int cm_get_main_vco_clk_hz(void) u32 reg, clock; /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); clock = cm_get_osc_clk_hz(1); clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; @@ -336,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void) u32 reg, clock = 0; /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) @@ -347,7 +373,7 @@ static unsigned int cm_get_per_vco_clk_hz(void) clock = cm_get_f2s_per_ref_clk_hz(); /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> @@ -363,9 +389,9 @@ unsigned long cm_get_mpu_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the MPU clock */ - reg = readl(&clock_manager_base->altera.mpuclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK); clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mpuclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK); clock /= (reg + 1); return clock; } @@ -375,7 +401,7 @@ unsigned long cm_get_sdram_clk_hz(void) u32 reg, clock = 0; /* identify SDRAM PLL clock source */ - reg = readl(&clock_manager_base->sdr_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) @@ -386,14 +412,14 @@ unsigned long cm_get_sdram_clk_hz(void) clock = cm_get_f2s_sdr_ref_clk_hz(); /* get the SDRAM VCO clock */ - reg = readl(&clock_manager_base->sdr_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; /* get the SDRAM (DDR_DQS) clock */ - reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; clock /= (reg + 1); @@ -406,7 +432,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) u32 reg, clock = 0; /* identify the source of L4 SP clock */ - reg = readl(&clock_manager_base->main_pll.l4src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; @@ -414,20 +440,23 @@ unsigned int cm_get_l4_sp_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the clock prior L4 SP divider (main clk) */ - reg = readl(&clock_manager_base->altera.mainclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_ALTR_MAINCLK); clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mainclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINCLK); clock /= (reg + 1); } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERBASECLK); clock /= (reg + 1); } /* get the L4 SP clock which supplied to UART */ - reg = readl(&clock_manager_base->main_pll.maindiv); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV); reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; clock = clock / (1 << reg); @@ -440,7 +469,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void) u32 reg, clock = 0; /* identify the source of MMC clock */ - reg = readl(&clock_manager_base->per_pll.src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; @@ -450,13 +479,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the SDMMC clock */ - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK); clock /= (reg + 1); } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { clock = cm_get_per_vco_clk_hz(); /* get the SDMMC clock */ - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK); clock /= (reg + 1); } @@ -470,7 +501,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void) u32 reg, clock = 0; /* identify the source of QSPI clock */ - reg = readl(&clock_manager_base->per_pll.src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; @@ -480,13 +511,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the qspi clock */ - reg = readl(&clock_manager_base->main_pll.mainqspiclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINQSPICLK); clock /= (reg + 1); } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { clock = cm_get_per_vco_clk_hz(); /* get the qspi clock */ - reg = readl(&clock_manager_base->per_pll.perqspiclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERQSPICLK); clock /= (reg + 1); } @@ -500,7 +533,7 @@ unsigned int cm_get_spi_controller_clk_hz(void) clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK); clock /= (reg + 1); return clock; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 3ba2a00c02..05e42127b5 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -12,31 +12,26 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* * function to write the bypass register which requires a poll of the * busy bit */ static void cm_write_bypass_mainpll(u32 val) { - writel(val, &clock_manager_base->main_pll.bypass); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS); cm_wait_for_fsm(); } static void cm_write_bypass_perpll(u32 val) { - writel(val, &clock_manager_base->per_pll.bypass); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ static void cm_write_ctrl(u32 val) { - writel(val, &clock_manager_base->ctrl); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL); cm_wait_for_fsm(); } @@ -68,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg) writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & ~CLKMGR_PLLGLOB_RST_MASK), - &clock_manager_base->main_pll.pllglob); - writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); - writel(vcocalib, &clock_manager_base->main_pll.vcocalib); - writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); - writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); - writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB); + writel(cfg->main_pll_fdbck, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK); + writel(vcocalib, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB); + writel(cfg->main_pll_pllc0, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0); + writel(cfg->main_pll_pllc1, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1); + writel(cfg->main_pll_nocdiv, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV); /* setup peripheral PLL dividers */ /* calculate the vcocalib value */ @@ -90,18 +90,24 @@ void cm_basic_init(const struct cm_config * const cfg) writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & ~CLKMGR_PLLGLOB_RST_MASK), - &clock_manager_base->per_pll.pllglob); - writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); - writel(vcocalib, &clock_manager_base->per_pll.vcocalib); - writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); - writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); - writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); - writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB); + writel(cfg->per_pll_fdbck, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK); + writel(vcocalib, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB); + writel(cfg->per_pll_pllc0, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0); + writel(cfg->per_pll_pllc1, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1); + writel(cfg->per_pll_emacctl, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL); + writel(cfg->per_pll_gpiodiv, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV); /* Take both PLL out of reset and power up */ - setbits_le32(&clock_manager_base->main_pll.pllglob, + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB, CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); - setbits_le32(&clock_manager_base->per_pll.pllglob, + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB, CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); #define LOCKED_MASK \ @@ -115,66 +121,85 @@ void cm_basic_init(const struct cm_config * const cfg) * only take effect upon value change, we shall set a maximum value as * default value. */ - writel(0xff, &clock_manager_base->main_pll.mpuclk); - writel(0xff, &clock_manager_base->main_pll.nocclk); - writel(0xff, &clock_manager_base->main_pll.cntr2clk); - writel(0xff, &clock_manager_base->main_pll.cntr3clk); - writel(0xff, &clock_manager_base->main_pll.cntr4clk); - writel(0xff, &clock_manager_base->main_pll.cntr5clk); - writel(0xff, &clock_manager_base->main_pll.cntr6clk); - writel(0xff, &clock_manager_base->main_pll.cntr7clk); - writel(0xff, &clock_manager_base->main_pll.cntr8clk); - writel(0xff, &clock_manager_base->main_pll.cntr9clk); - writel(0xff, &clock_manager_base->per_pll.cntr2clk); - writel(0xff, &clock_manager_base->per_pll.cntr3clk); - writel(0xff, &clock_manager_base->per_pll.cntr4clk); - writel(0xff, &clock_manager_base->per_pll.cntr5clk); - writel(0xff, &clock_manager_base->per_pll.cntr6clk); - writel(0xff, &clock_manager_base->per_pll.cntr7clk); - writel(0xff, &clock_manager_base->per_pll.cntr8clk); - writel(0xff, &clock_manager_base->per_pll.cntr9clk); - - writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); - writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk); - writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk); - writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk); - writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk); - writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk); - writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk); - writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk); - writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); - writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk); - writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); - writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk); - writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); - writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); - writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk); - writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk); - writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk); - writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK); + writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK); + + writel(cfg->main_pll_mpuclk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK); + writel(cfg->main_pll_nocclk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK); + writel(cfg->main_pll_cntr2clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK); + writel(cfg->main_pll_cntr3clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK); + writel(cfg->main_pll_cntr4clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK); + writel(cfg->main_pll_cntr5clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK); + writel(cfg->main_pll_cntr6clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK); + writel(cfg->main_pll_cntr7clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK); + writel(cfg->main_pll_cntr8clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK); + writel(cfg->main_pll_cntr9clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK); + writel(cfg->per_pll_cntr2clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK); + writel(cfg->per_pll_cntr3clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK); + writel(cfg->per_pll_cntr4clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK); + writel(cfg->per_pll_cntr5clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK); + writel(cfg->per_pll_cntr6clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK); + writel(cfg->per_pll_cntr7clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK); + writel(cfg->per_pll_cntr8clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK); + writel(cfg->per_pll_cntr9clk, + socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK); /* Take all PLLs out of bypass */ cm_write_bypass_mainpll(0); cm_write_bypass_perpll(0); /* clear safe mode / out of boot mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) - & ~(CLKMGR_CTRL_SAFEMODE)); + cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) & + ~(CLKMGR_CTRL_SAFEMODE)); /* Now ungate non-hw-managed clocks */ - writel(~0, &clock_manager_base->main_pll.en); - writel(~0, &clock_manager_base->per_pll.en); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN); /* Clear the loss of lock bits (write 1 to clear) */ - writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, - &clock_manager_base->intrclr); + writel(CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR); } static unsigned long cm_get_main_vco_clk_hz(void) { unsigned long fref, refdiv, mdiv, reg, vco; - reg = readl(&clock_manager_base->main_pll.pllglob); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB); fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & CLKMGR_PLLGLOB_VCO_PSRC_MASK; @@ -193,7 +218,7 @@ static unsigned long cm_get_main_vco_clk_hz(void) refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & CLKMGR_PLLGLOB_REFCLKDIV_MASK; - reg = readl(&clock_manager_base->main_pll.fdbck); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK); mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; vco = fref / refdiv; @@ -205,7 +230,7 @@ static unsigned long cm_get_per_vco_clk_hz(void) { unsigned long fref, refdiv, mdiv, reg, vco; - reg = readl(&clock_manager_base->per_pll.pllglob); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB); fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & CLKMGR_PLLGLOB_VCO_PSRC_MASK; @@ -224,7 +249,7 @@ static unsigned long cm_get_per_vco_clk_hz(void) refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & CLKMGR_PLLGLOB_REFCLKDIV_MASK; - reg = readl(&clock_manager_base->per_pll.fdbck); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK); mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; vco = fref / refdiv; @@ -234,20 +259,23 @@ static unsigned long cm_get_per_vco_clk_hz(void) unsigned long cm_get_mpu_clk_hz(void) { - unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); + unsigned long clock = readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_MPUCLK); clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; switch (clock) { case CLKMGR_CLKSRC_MAIN: clock = cm_get_main_vco_clk_hz(); - clock /= (readl(&clock_manager_base->main_pll.pllc0) & + clock /= (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_PLLC0) & CLKMGR_PLLC0_DIV_MASK); break; case CLKMGR_CLKSRC_PER: clock = cm_get_per_vco_clk_hz(); - clock /= (readl(&clock_manager_base->per_pll.pllc0) & + clock /= (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_PERPLL_PLLC0) & CLKMGR_CLKCNT_MSK); break; @@ -264,28 +292,30 @@ unsigned long cm_get_mpu_clk_hz(void) break; } - clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & - CLKMGR_CLKCNT_MSK); + clock /= 1 + (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK); return clock; } unsigned int cm_get_l3_main_clk_hz(void) { - u32 clock = readl(&clock_manager_base->main_pll.nocclk); + u32 clock = readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_NOCCLK); clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; switch (clock) { case CLKMGR_CLKSRC_MAIN: clock = cm_get_main_vco_clk_hz(); - clock /= (readl(&clock_manager_base->main_pll.pllc1) & + clock /= (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_PLLC1) & CLKMGR_PLLC0_DIV_MASK); break; case CLKMGR_CLKSRC_PER: clock = cm_get_per_vco_clk_hz(); - clock /= (readl(&clock_manager_base->per_pll.pllc1) & - CLKMGR_CLKCNT_MSK); + clock /= (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK); break; case CLKMGR_CLKSRC_OSC1: @@ -301,28 +331,31 @@ unsigned int cm_get_l3_main_clk_hz(void) break; } - clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) & - CLKMGR_CLKCNT_MSK); + clock /= 1 + (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK); return clock; } unsigned int cm_get_mmc_controller_clk_hz(void) { - u32 clock = readl(&clock_manager_base->per_pll.cntr6clk); + u32 clock = readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_PERPLL_CNTR6CLK); clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; switch (clock) { case CLKMGR_CLKSRC_MAIN: clock = cm_get_l3_main_clk_hz(); - clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & - CLKMGR_CLKCNT_MSK); + clock /= 1 + (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_CNTR6CLK) & + CLKMGR_CLKCNT_MSK); break; case CLKMGR_CLKSRC_PER: clock = cm_get_l3_main_clk_hz(); - clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & - CLKMGR_CLKCNT_MSK); + clock /= 1 + (readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_PERPLL_CNTR6CLK) & + CLKMGR_CLKCNT_MSK); break; case CLKMGR_CLKSRC_OSC1: @@ -344,22 +377,25 @@ unsigned int cm_get_l4_sp_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> - CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); + clock /= (1 << ((readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); return clock; } unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(&sysmgr_regs->boot_scratch_cold0); + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); } unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> - CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK)); + clock /= (1 << ((readl(socfpga_get_clkmgr_addr() + + CLKMGR_S10_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK)); return clock; } diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c new file mode 100644 index 0000000000..69229dc651 --- /dev/null +++ b/arch/arm/mach-socfpga/firewall.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * + */ + +#include <asm/io.h> +#include <common.h> +#include <asm/arch/firewall.h> +#include <asm/arch/system_manager.h> + +static void firewall_l4_per_disable(void) +{ + const struct socfpga_firwall_l4_per *firwall_l4_per_base = + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; + u32 i; + const u32 *addr[] = { + &firwall_l4_per_base->nand, + &firwall_l4_per_base->nand_data, + &firwall_l4_per_base->usb0, + &firwall_l4_per_base->usb1, + &firwall_l4_per_base->spim0, + &firwall_l4_per_base->spim1, + &firwall_l4_per_base->emac0, + &firwall_l4_per_base->emac1, + &firwall_l4_per_base->emac2, + &firwall_l4_per_base->sdmmc, + &firwall_l4_per_base->gpio0, + &firwall_l4_per_base->gpio1, + &firwall_l4_per_base->i2c0, + &firwall_l4_per_base->i2c1, + &firwall_l4_per_base->i2c2, + &firwall_l4_per_base->i2c3, + &firwall_l4_per_base->i2c4, + &firwall_l4_per_base->timer0, + &firwall_l4_per_base->timer1, + &firwall_l4_per_base->uart0, + &firwall_l4_per_base->uart1 + }; + + /* + * The following lines of code will enable non-secure access + * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This + * is needed as most OS run in non-secure mode. Thus we need to + * enable non-secure access to these peripherals in order for the + * OS to use these peripherals. + */ + for (i = 0; i < ARRAY_SIZE(addr); i++) + writel(FIREWALL_L4_DISABLE_ALL, addr[i]); +} + +static void firewall_l4_sys_disable(void) +{ + const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = + (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; + u32 i; + const u32 *addr[] = { + &firwall_l4_sys_base->dma_ecc, + &firwall_l4_sys_base->emac0rx_ecc, + &firwall_l4_sys_base->emac0tx_ecc, + &firwall_l4_sys_base->emac1rx_ecc, + &firwall_l4_sys_base->emac1tx_ecc, + &firwall_l4_sys_base->emac2rx_ecc, + &firwall_l4_sys_base->emac2tx_ecc, + &firwall_l4_sys_base->nand_ecc, + &firwall_l4_sys_base->nand_read_ecc, + &firwall_l4_sys_base->nand_write_ecc, + &firwall_l4_sys_base->ocram_ecc, + &firwall_l4_sys_base->sdmmc_ecc, + &firwall_l4_sys_base->usb0_ecc, + &firwall_l4_sys_base->usb1_ecc, + &firwall_l4_sys_base->clock_manager, + &firwall_l4_sys_base->io_manager, + &firwall_l4_sys_base->reset_manager, + &firwall_l4_sys_base->system_manager, + &firwall_l4_sys_base->watchdog0, + &firwall_l4_sys_base->watchdog1, + &firwall_l4_sys_base->watchdog2, + &firwall_l4_sys_base->watchdog3 + }; + + for (i = 0; i < ARRAY_SIZE(addr); i++) + writel(FIREWALL_L4_DISABLE_ALL, addr[i]); +} + +static void firewall_bridge_disable(void) +{ + /* disable lwsocf2fpga and soc2fpga bridge security */ + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); +} + +void firewall_setup(void) +{ + firewall_l4_per_disable(); + firewall_l4_sys_disable(); + firewall_bridge_disable(); + + /* disable SMMU security */ + writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); + + /* enable non-secure interface to DMA330 DMA and peripherals */ + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA); + writel(SYSMGR_DMAPERIPH_ALL_NS, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH); +} diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 1f549d7e70..d3eca65e97 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -10,7 +10,11 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 +#else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 +#endif #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index dd80e3a767..c6830582a5 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -6,6 +6,8 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ +phys_addr_t socfpga_get_clkmgr_addr(void); + #ifndef __ASSEMBLER__ void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); @@ -18,6 +20,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/clock_manager_agilex.h> #endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h new file mode 100644 index 0000000000..386e82a4e3 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX_ +#define _CLOCK_MANAGER_AGILEX_ + +unsigned long cm_get_mpu_clk_hz(void); + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex.h" + +#endif /* _CLOCK_MANAGER_AGILEX_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index de8c22540f..23f280df1b 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -8,86 +8,57 @@ #ifndef __ASSEMBLER__ -struct socfpga_clock_manager_main_pll { - u32 vco0; - u32 vco1; - u32 en; - u32 ens; - u32 enr; - u32 bypass; - u32 bypasss; - u32 bypassr; - u32 mpuclk; - u32 nocclk; - u32 cntr2clk; - u32 cntr3clk; - u32 cntr4clk; - u32 cntr5clk; - u32 cntr6clk; - u32 cntr7clk; - u32 cntr8clk; - u32 cntr9clk; - u32 pad_0x48_0x5b[5]; - u32 cntr15clk; - u32 outrst; - u32 outrststat; - u32 nocdiv; - u32 pad_0x6c_0x80[5]; -}; - -struct socfpga_clock_manager_per_pll { - u32 vco0; - u32 vco1; - u32 en; - u32 ens; - u32 enr; - u32 bypass; - u32 bypasss; - u32 bypassr; - u32 pad_0x20_0x27[2]; - u32 cntr2clk; - u32 cntr3clk; - u32 cntr4clk; - u32 cntr5clk; - u32 cntr6clk; - u32 cntr7clk; - u32 cntr8clk; - u32 cntr9clk; - u32 pad_0x48_0x5f[6]; - u32 outrst; - u32 outrststat; - u32 emacctl; - u32 gpiodiv; - u32 pad_0x70_0x80[4]; -}; - -struct socfpga_clock_manager_altera { - u32 mpuclk; - u32 nocclk; - u32 mainmisc0; - u32 mainmisc1; - u32 perimisc0; - u32 perimisc1; -}; - -struct socfpga_clock_manager { - /* clkmgr */ - u32 ctrl; - u32 intr; - u32 intrs; - u32 intrr; - u32 intren; - u32 intrens; - u32 intrenr; - u32 stat; - u32 testioctrl; - u32 _pad_0x24_0x40[7]; - /* mainpllgrp */ - struct socfpga_clock_manager_main_pll main_pll; - /* perpllgrp */ - struct socfpga_clock_manager_per_pll per_pll; - struct socfpga_clock_manager_altera altera; -}; +/* Clock manager group */ +#define CLKMGR_A10_CTRL 0x00 +#define CLKMGR_A10_INTR 0x04 +#define CLKMGR_A10_STAT 0x1c +/* MainPLL group */ +#define CLKMGR_A10_MAINPLL_VCO0 0x40 +#define CLKMGR_A10_MAINPLL_VCO1 0x44 +#define CLKMGR_A10_MAINPLL_EN 0x48 +#define CLKMGR_A10_MAINPLL_ENS 0x4c +#define CLKMGR_A10_MAINPLL_ENR 0x50 +#define CLKMGR_A10_MAINPLL_BYPASS 0x54 +#define CLKMGR_A10_MAINPLL_BYPASSS 0x58 +#define CLKMGR_A10_MAINPLL_BYPASSR 0x5c +#define CLKMGR_A10_MAINPLL_MPUCLK 0x60 +#define CLKMGR_A10_MAINPLL_NOCCLK 0x64 +#define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68 +#define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c +#define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70 +#define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74 +#define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78 +#define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c +#define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80 +#define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84 +#define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c +#define CLKMGR_A10_MAINPLL_NOCDIV 0xa8 +/* Peripheral PLL group */ +#define CLKMGR_A10_PERPLL_VCO0 0xc0 +#define CLKMGR_A10_PERPLL_VCO1 0xc4 +#define CLKMGR_A10_PERPLL_EN 0xc8 +#define CLKMGR_A10_PERPLL_ENS 0xcc +#define CLKMGR_A10_PERPLL_ENR 0xd0 +#define CLKMGR_A10_PERPLL_BYPASS 0xd4 +#define CLKMGR_A10_PERPLL_BYPASSS 0xd8 +#define CLKMGR_A10_PERPLL_BYPASSR 0xdc +#define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8 +#define CLKMGR_A10_PERPLL_CNTR3CLK 0xec +#define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0 +#define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4 +#define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8 +#define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc +#define CLKMGR_A10_PERPLL_CNTR8CLK 0x100 +#define CLKMGR_A10_PERPLL_CNTR9CLK 0x104 +#define CLKMGR_A10_PERPLL_EMACCTL 0x128 +#define CLKMGR_A10_PERPLL_GPIOFIV 0x12c +/* Altera group */ +#define CLKMGR_A10_ALTR_MPUCLK 0x140 +#define CLKMGR_A10_ALTR_NOCCLK 0x144 + +#define CLKMGR_STAT CLKMGR_A10_STAT +#define CLKMGR_INTER CLKMGR_A10_INTER +#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN #ifdef CONFIG_SPL_BUILD int cm_basic_init(const void *blob); @@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* __ASSEMBLER__ */ -#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 -#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h index 5bedf28cf1..08655094ca 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h @@ -45,71 +45,53 @@ struct cm_config { u32 altera_grp_mpuclk; }; -struct socfpga_clock_manager_main_pll { - u32 vco; - u32 misc; - u32 mpuclk; - u32 mainclk; - u32 dbgatclk; - u32 mainqspiclk; - u32 mainnandsdmmcclk; - u32 cfgs2fuser0clk; - u32 en; - u32 maindiv; - u32 dbgdiv; - u32 tracediv; - u32 l4src; - u32 stat; - u32 _pad_0x38_0x40[2]; -}; - -struct socfpga_clock_manager_per_pll { - u32 vco; - u32 misc; - u32 emac0clk; - u32 emac1clk; - u32 perqspiclk; - u32 pernandsdmmcclk; - u32 perbaseclk; - u32 s2fuser1clk; - u32 en; - u32 div; - u32 gpiodiv; - u32 src; - u32 stat; - u32 _pad_0x34_0x40[3]; -}; - -struct socfpga_clock_manager_sdr_pll { - u32 vco; - u32 ctrl; - u32 ddrdqsclk; - u32 ddr2xdqsclk; - u32 ddrdqclk; - u32 s2fuser2clk; - u32 en; - u32 stat; -}; - -struct socfpga_clock_manager_altera { - u32 mpuclk; - u32 mainclk; -}; - -struct socfpga_clock_manager { - u32 ctrl; - u32 bypass; - u32 inter; - u32 intren; - u32 dbctrl; - u32 stat; - u32 _pad_0x18_0x3f[10]; - struct socfpga_clock_manager_main_pll main_pll; - struct socfpga_clock_manager_per_pll per_pll; - struct socfpga_clock_manager_sdr_pll sdr_pll; - struct socfpga_clock_manager_altera altera; - u32 _pad_0xe8_0x200[70]; -}; +/* Clock manager group */ +#define CLKMGR_GEN5_CTRL 0x00 +#define CLKMGR_GEN5_BYPASS 0x04 +#define CLKMGR_GEN5_INTER 0x08 +#define CLKMGR_GEN5_STAT 0x14 +/* MainPLL group */ +#define CLKMGR_GEN5_MAINPLL_VCO 0x40 +#define CLKMGR_GEN5_MAINPLL_MISC 0x44 +#define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48 +#define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c +#define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50 +#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54 +#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58 +#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c +#define CLKMGR_GEN5_MAINPLL_EN 0x60 +#define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64 +#define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68 +#define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c +#define CLKMGR_GEN5_MAINPLL_L4SRC 0x70 +/* Peripheral PLL group */ +#define CLKMGR_GEN5_PERPLL_VCO 0x80 +#define CLKMGR_GEN5_PERPLL_MISC 0x84 +#define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88 +#define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c +#define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90 +#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94 +#define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98 +#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c +#define CLKMGR_GEN5_PERPLL_EN 0xa0 +#define CLKMGR_GEN5_PERPLL_DIV 0xa4 +#define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8 +#define CLKMGR_GEN5_PERPLL_SRC 0xac +/* SDRAM PLL group */ +#define CLKMGR_GEN5_SDRPLL_VCO 0xc0 +#define CLKMGR_GEN5_SDRPLL_CTRL 0xc4 +#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8 +#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc +#define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0 +#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4 +#define CLKMGR_GEN5_SDRPLL_EN 0xd8 +/* Altera group */ +#define CLKMGR_GEN5_ALTR_MPUCLK 0xe0 +#define CLKMGR_GEN5_ALTR_MAINCLK 0xe4 + +#define CLKMGR_STAT CLKMGR_GEN5_STAT +#define CLKMGR_INTER CLKMGR_GEN5_INTER +#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN /* Clock speed accessors */ unsigned long cm_get_mpu_clk_hz(void); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index 24b20de011..e710aa2f94 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> * */ #ifndef _CLOCK_MANAGER_S10_ #define _CLOCK_MANAGER_S10_ +#include <asm/arch/clock_manager_soc64.h> + /* Clock speed accessors */ unsigned long cm_get_mpu_clk_hz(void); unsigned long cm_get_sdram_clk_hz(void); @@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(void); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); -const unsigned int cm_get_intosc_clk_hz(void); -const unsigned int cm_get_fpga_clk_hz(void); - -#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000 - -/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void); struct cm_config { /* main group */ @@ -69,75 +59,54 @@ struct cm_config { void cm_basic_init(const struct cm_config * const cfg); -struct socfpga_clock_manager_main_pll { - u32 en; - u32 ens; - u32 enr; - u32 bypass; - u32 bypasss; - u32 bypassr; - u32 mpuclk; - u32 nocclk; - u32 cntr2clk; - u32 cntr3clk; - u32 cntr4clk; - u32 cntr5clk; - u32 cntr6clk; - u32 cntr7clk; - u32 cntr8clk; - u32 cntr9clk; - u32 nocdiv; - u32 pllglob; - u32 fdbck; - u32 mem; - u32 memstat; - u32 pllc0; - u32 pllc1; - u32 vcocalib; - u32 _pad_0x90_0xA0[5]; -}; +/* Control status */ +#define CLKMGR_S10_CTRL 0x00 +#define CLKMGR_S10_STAT 0x04 +#define CLKMGR_S10_INTRCLR 0x14 +/* Mainpll group */ +#define CLKMGR_S10_MAINPLL_EN 0x30 +#define CLKMGR_S10_MAINPLL_BYPASS 0x3c +#define CLKMGR_S10_MAINPLL_MPUCLK 0x48 +#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c +#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50 +#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54 +#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58 +#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c +#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60 +#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64 +#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68 +#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c +#define CLKMGR_S10_MAINPLL_NOCDIV 0x70 +#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74 +#define CLKMGR_S10_MAINPLL_FDBCK 0x78 +#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80 +#define CLKMGR_S10_MAINPLL_PLLC0 0x84 +#define CLKMGR_S10_MAINPLL_PLLC1 0x88 +#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c +/* Periphpll group */ +#define CLKMGR_S10_PERPLL_EN 0xa4 +#define CLKMGR_S10_PERPLL_BYPASS 0xac +#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc +#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0 +#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4 +#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8 +#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc +#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0 +#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4 +#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8 +#define CLKMGR_S10_PERPLL_EMACCTL 0xdc +#define CLKMGR_S10_PERPLL_GPIODIV 0xe0 +#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4 +#define CLKMGR_S10_PERPLL_FDBCK 0xe8 +#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0 +#define CLKMGR_S10_PERPLL_PLLC0 0xf4 +#define CLKMGR_S10_PERPLL_PLLC1 0xf8 +#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc + +#define CLKMGR_STAT CLKMGR_S10_STAT +#define CLKMGR_INTER CLKMGR_S10_INTER +#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN -struct socfpga_clock_manager_per_pll { - u32 en; - u32 ens; - u32 enr; - u32 bypass; - u32 bypasss; - u32 bypassr; - u32 cntr2clk; - u32 cntr3clk; - u32 cntr4clk; - u32 cntr5clk; - u32 cntr6clk; - u32 cntr7clk; - u32 cntr8clk; - u32 cntr9clk; - u32 emacctl; - u32 gpiodiv; - u32 pllglob; - u32 fdbck; - u32 mem; - u32 memstat; - u32 pllc0; - u32 pllc1; - u32 vcocalib; - u32 _pad_0x100_0x124[10]; -}; - -struct socfpga_clock_manager { - u32 ctrl; - u32 stat; - u32 testioctrl; - u32 intrgen; - u32 intrmsk; - u32 intrclr; - u32 intrsts; - u32 intrstk; - u32 intrraw; - u32 _pad_0x24_0x2c[3]; - struct socfpga_clock_manager_main_pll main_pll; - struct socfpga_clock_manager_per_pll per_pll; -}; #define CLKMGR_CTRL_SAFEMODE BIT(0) #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h new file mode 100644 index 0000000000..71fbaa7667 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * + */ + +#ifndef _CLOCK_MANAGER_SOC64_ +#define _CLOCK_MANAGER_SOC64_ + +const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +#define CLKMGR_INTOSC_HZ 400000000 + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +#endif /* _CLOCK_MANAGER_SOC64_ */ diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall.h index b96f779f14..430341bea1 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> * */ -#ifndef _FIREWALL_S10_ -#define _FIREWALL_S10_ +#ifndef _FIREWALL_H_ +#define _FIREWALL_H_ struct socfpga_firwall_l4_per { u32 nand; /* 0x00 */ @@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys { #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0 + #define CCU_ADMASK_P_MASK BIT(0) #define CCU_ADMASK_NS_MASK BIT(1) @@ -117,4 +124,6 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) -#endif /* _FIREWALL_S10_ */ +void firewall_setup(void); + +#endif /* _FIREWALL_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h index ba0f1fd1b2..3e9b606ce2 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -26,8 +26,13 @@ #define S10_HANDOFF_OFFSET_LENGTH 0x4 #define S10_HANDOFF_OFFSET_DATA 0x10 -#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) -#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#else +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600) +#endif #define S10_HANDOFF_SIZE 4096 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index f11f907e1c..f6de1ccb4a 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void); void do_bridge_reset(int enable, unsigned int mask); void socfpga_pl310_clear(void); +void socfpga_get_managers_addr(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 6ad037e325..7844ad14cb 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -6,6 +6,8 @@ #ifndef _RESET_MANAGER_H_ #define _RESET_MANAGER_H_ +phys_addr_t socfpga_get_rstmgr_addr(void); + void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); @@ -41,8 +43,9 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_gen5.h> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include <asm/arch/reset_manager_arria10.h> -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -#include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_soc64.h> #endif #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 6623ebee65..22e4eb33de 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_deassert_osc1wd0(void); int socfpga_bridges_reset(void); -struct socfpga_reset_manager { - u32 stat; - u32 ramstat; - u32 miscstat; - u32 ctrl; - u32 hdsken; - u32 hdskreq; - u32 hdskack; - u32 counts; - u32 mpumodrst; - u32 per0modrst; - u32 per1modrst; - u32 brgmodrst; - u32 sysmodrst; - u32 coldmodrst; - u32 nrstmodrst; - u32 dbgmodrst; - u32 mpuwarmmask; - u32 per0warmmask; - u32 per1warmmask; - u32 brgwarmmask; - u32 syswarmmask; - u32 nrstwarmmask; - u32 l3warmmask; - u32 tststa; - u32 tstscratch; - u32 hdsktimeout; - u32 hmcintr; - u32 hmcintren; - u32 hmcintrens; - u32 hmcintrenr; - u32 hmcgpout; - u32 hmcgpin; -}; +#define RSTMGR_A10_STATUS 0x00 +#define RSTMGR_A10_CTRL 0x0c +#define RSTMGR_A10_MPUMODRST 0x20 +#define RSTMGR_A10_PER0MODRST 0x24 +#define RSTMGR_A10_PER1MODRST 0x28 +#define RSTMGR_A10_BRGMODRST 0x2c +#define RSTMGR_A10_SYSMODRST 0x30 + +#define RSTMGR_CTRL RSTMGR_A10_CTRL /* * SocFPGA Arria10 reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index f4dcb14623..d108eac1e2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -11,19 +11,15 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); void socfpga_bridges_reset(int enable); -struct socfpga_reset_manager { - u32 status; - u32 ctrl; - u32 counts; - u32 padding1; - u32 mpu_mod_reset; - u32 per_mod_reset; - u32 per2_mod_reset; - u32 brg_mod_reset; - u32 misc_mod_reset; - u32 padding2[12]; - u32 tstscratch; -}; +#define RSTMGR_GEN5_STATUS 0x00 +#define RSTMGR_GEN5_CTRL 0x04 +#define RSTMGR_GEN5_MPUMODRST 0x10 +#define RSTMGR_GEN5_PERMODRST 0x14 +#define RSTMGR_GEN5_PER2MODRST 0x18 +#define RSTMGR_GEN5_BRGMODRST 0x1c +#define RSTMGR_GEN5_MISCMODRST 0x20 + +#define RSTMGR_CTRL RSTMGR_GEN5_CTRL /* * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h deleted file mode 100644 index 452147b017..0000000000 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> - * - */ - -#ifndef _RESET_MANAGER_S10_ -#define _RESET_MANAGER_S10_ - -void reset_cpu(ulong addr); -int cpu_has_been_warmreset(void); - -void socfpga_bridges_reset(int enable); - -void socfpga_per_reset(u32 reset, int set); -void socfpga_per_reset_all(void); - -struct socfpga_reset_manager { - u32 status; - u32 mpu_rst_stat; - u32 misc_stat; - u32 padding1; - u32 hdsk_en; - u32 hdsk_req; - u32 hdsk_ack; - u32 hdsk_stall; - u32 mpumodrst; - u32 per0modrst; - u32 per1modrst; - u32 brgmodrst; - u32 padding2; - u32 cold_mod_reset; - u32 padding3; - u32 dbg_mod_reset; - u32 tap_mod_reset; - u32 padding4; - u32 padding5; - u32 brg_warm_mask; - u32 padding6[3]; - u32 tst_stat; - u32 padding7; - u32 hdsk_timeout; - u32 mpul2flushtimeout; - u32 dbghdsktimeout; -}; - -#define RSTMGR_MPUMODRST_CORE0 0 -#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 - -/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 - -/* - * Define a reset identifier, from which a permodrst bank ID - * and reset ID can be extracted using the subsequent macros - * RSTMGR_RESET() and RSTMGR_BANK(). - */ -#define RSTMGR_BANK_OFFSET 8 -#define RSTMGR_BANK_MASK 0x7 -#define RSTMGR_RESET_OFFSET 0 -#define RSTMGR_RESET_MASK 0x1f -#define RSTMGR_DEFINE(_bank, _offset) \ - ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) - -/* Extract reset ID from the reset identifier. */ -#define RSTMGR_RESET(_reset) \ - (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) - -/* Extract bank ID from the reset identifier. */ -#define RSTMGR_BANK(_reset) \ - (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) - -/* - * SocFPGA Stratix10 reset IDs, bank mapping is as follows: - * 0 ... mpumodrst - * 1 ... per0modrst - * 2 ... per1modrst - * 3 ... brgmodrst - */ -#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) -#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) -#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) -#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) -#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) -#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) -#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) -#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) -#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) -#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) -#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) -#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) -#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) -#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) -#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) -#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) -#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) -#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) -#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) -#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) -#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) -#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) -#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) -#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) -#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) -#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) -#define RSTMGR_SDR RSTMGR_DEFINE(3, 6) - -/* Create a human-readable reference to SoCFPGA reset. */ -#define SOCFPGA_RESET(_name) RSTMGR_##_name - -#endif /* _RESET_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h new file mode 100644 index 0000000000..3f952bcc6e --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + */ + +#ifndef _RESET_MANAGER_SOC64_H_ +#define _RESET_MANAGER_SOC64_H_ + +void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); +void socfpga_bridges_reset(int enable); + +#define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_MPUMODRST 0x20 +#define RSTMGR_SOC64_PER0MODRST 0x24 +#define RSTMGR_SOC64_PER1MODRST 0x28 +#define RSTMGR_SOC64_BRGMODRST 0x2c + +#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 + +/* + * SocFPGA Stratix10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + */ +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) + +#endif /* _RESET_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 7e76df74b7..6de0a08131 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -6,8 +6,11 @@ #ifndef _SYSTEM_MANAGER_H_ #define _SYSTEM_MANAGER_H_ -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -#include <asm/arch/system_manager_s10.h> +phys_addr_t socfpga_get_sysmgr_addr(void); + +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/system_manager_soc64.h> #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h index 14052b957c..e4fc6d2e55 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h @@ -6,73 +6,33 @@ #ifndef _SYSTEM_MANAGER_ARRIA10_H_ #define _SYSTEM_MANAGER_ARRIA10_H_ -struct socfpga_system_manager { - u32 siliconid1; - u32 siliconid2; - u32 wddbg; - u32 bootinfo; - u32 mpu_ctrl_l2_ecc; - u32 _pad_0x14_0x1f[3]; - u32 dma; - u32 dma_periph; - u32 sdmmcgrp_ctrl; - u32 sdmmc_l3master; - u32 nand_bootstrap; - u32 nand_l3master; - u32 usb0_l3master; - u32 usb1_l3master; - u32 emac_global; - u32 emac[3]; - u32 _pad_0x50_0x5f[4]; - u32 fpgaintf_en_global; - u32 fpgaintf_en_0; - u32 fpgaintf_en_1; - u32 fpgaintf_en_2; - u32 fpgaintf_en_3; - u32 _pad_0x74_0x7f[3]; - u32 noc_addr_remap_value; - u32 noc_addr_remap_set; - u32 noc_addr_remap_clear; - u32 _pad_0x8c_0x8f; - u32 ecc_intmask_value; - u32 ecc_intmask_set; - u32 ecc_intmask_clr; - u32 ecc_intstatus_serr; - u32 ecc_intstatus_derr; - u32 mpu_status_l2_ecc; - u32 mpu_clear_l2_ecc; - u32 mpu_status_l1_parity; - u32 mpu_clear_l1_parity; - u32 mpu_set_l1_parity; - u32 _pad_0xb8_0xbf[2]; - u32 noc_timeout; - u32 noc_idlereq_set; - u32 noc_idlereq_clr; - u32 noc_idlereq_value; - u32 noc_idleack; - u32 noc_idlestatus; - u32 fpga2soc_ctrl; - u32 _pad_0xdc_0xff[9]; - u32 tsmc_tsel_0; - u32 tsmc_tsel_1; - u32 tsmc_tsel_2; - u32 tsmc_tsel_3; - u32 _pad_0x110_0x200[60]; - u32 romhw_ctrl; - u32 romcode_ctrl; - u32 romcode_cpu1startaddr; - u32 romcode_initswstate; - u32 romcode_initswlastld; - u32 _pad_0x214_0x217; - u32 warmram_enable; - u32 warmram_datastart; - u32 warmram_length; - u32 warmram_execution; - u32 warmram_crc; - u32 _pad_0x22c_0x22f; - u32 isw_handoff[8]; - u32 romcode_bootromswstate[8]; -}; +#define SYSMGR_A10_WDDBG 0x08 +#define SYSMGR_A10_BOOTINFO 0x0c +#define SYSMGR_A10_DMA 0x20 +#define SYSMGR_A10_DMA_PERIPH 0x24 +#define SYSMGR_A10_SDMMC 0x28 +#define SYSMGR_A10_SDMMC_L3MASTER 0x2c +#define SYSMGR_A10_EMAC_GLOBAL 0x40 +#define SYSMGR_A10_EMAC0 0x44 +#define SYSMGR_A10_EMAC1 0x48 +#define SYSMGR_A10_EMAC2 0x4c +#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60 +#define SYSMGR_A10_FPGAINTF_EN0 0x64 +#define SYSMGR_A10_FPGAINTF_EN1 0x68 +#define SYSMGR_A10_FPGAINTF_EN2 0x6c +#define SYSMGR_A10_FPGAINTF_EN3 0x70 +#define SYSMGR_A10_ECC_INTMASK_VAL 0x90 +#define SYSMGR_A10_ECC_INTMASK_SET 0x94 +#define SYSMGR_A10_ECC_INTMASK_CLR 0x98 +#define SYSMGR_A10_NOC_TIMEOUT 0xc0 +#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_A10_NOC_IDLEACK 0xd0 +#define SYSMGR_A10_NOC_IDLESTATUS 0xd4 +#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8 + +#define SYSMGR_SDMMC SYSMGR_A10_SDMMC #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 #define SYSMGR_BOOTINFO_BSEL_SHIFT 12 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h index 52e59df513..90cb465d13 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable); void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); -struct socfpga_system_manager { - /* System Manager Module */ - u32 siliconid1; /* 0x00 */ - u32 siliconid2; - u32 _pad_0x8_0xf[2]; - u32 wddbg; /* 0x10 */ - u32 bootinfo; - u32 hpsinfo; - u32 parityinj; - /* FPGA Interface Group */ - u32 fpgaintfgrp_gbl; /* 0x20 */ - u32 fpgaintfgrp_indiv; - u32 fpgaintfgrp_module; - u32 _pad_0x2c_0x2f; - /* Scan Manager Group */ - u32 scanmgrgrp_ctrl; /* 0x30 */ - u32 _pad_0x34_0x3f[3]; - /* Freeze Control Group */ - u32 frzctrl_vioctrl; /* 0x40 */ - u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; /* 0x50 */ - u32 frzctrl_src; - u32 frzctrl_hwctrl; - u32 _pad_0x5c_0x5f; - /* EMAC Group */ - u32 emacgrp_ctrl; /* 0x60 */ - u32 emacgrp_l3master; - u32 _pad_0x68_0x6f[2]; - /* DMA Controller Group */ - u32 dmagrp_ctrl; /* 0x70 */ - u32 dmagrp_persecurity; - u32 _pad_0x78_0x7f[2]; - /* Preloader (initial software) Group */ - u32 iswgrp_handoff[8]; /* 0x80 */ - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ - /* Boot ROM Code Register Group */ - u32 romcodegrp_ctrl; /* 0xc0 */ - u32 romcodegrp_cpu1startaddr; - u32 romcodegrp_initswstate; - u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; /* 0xd0 */ - u32 __pad_0xd4_0xdf[3]; - /* Warm Boot from On-Chip RAM Group */ - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ - u32 romcodegrp_warmramgrp_datastart; - u32 romcodegrp_warmramgrp_length; - u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ - u32 __pad_0xf4_0xff[3]; - /* Boot ROM Hardware Register Group */ - u32 romhwgrp_ctrl; /* 0x100 */ - u32 _pad_0x104_0x107; - /* SDMMC Controller Group */ - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - /* NAND Flash Controller Register Group */ - u32 nandgrp_bootstrap; /* 0x110 */ - u32 nandgrp_l3master; - /* USB Controller Group */ - u32 usbgrp_l3master; - u32 _pad_0x11c_0x13f[9]; - /* ECC Management Register Group */ - u32 eccgrp_l2; /* 0x140 */ - u32 eccgrp_ocram; - u32 eccgrp_usb0; - u32 eccgrp_usb1; - u32 eccgrp_emac0; /* 0x150 */ - u32 eccgrp_emac1; - u32 eccgrp_dma; - u32 eccgrp_can0; - u32 eccgrp_can1; /* 0x160 */ - u32 eccgrp_nand; - u32 eccgrp_qspi; - u32 eccgrp_sdmmc; - u32 _pad_0x170_0x3ff[164]; - /* Pin Mux Control Group */ - u32 emacio[20]; /* 0x400 */ - u32 flashio[12]; /* 0x450 */ - u32 generalio[28]; /* 0x480 */ - u32 _pad_0x4f0_0x4ff[4]; - u32 mixed1io[22]; /* 0x500 */ - u32 mixed2io[8]; /* 0x558 */ - u32 gplinmux[23]; /* 0x578 */ - u32 gplmux[71]; /* 0x5d4 */ - u32 nandusefpga; /* 0x6f0 */ - u32 _pad_0x6f4; - u32 rgmii1usefpga; /* 0x6f8 */ - u32 _pad_0x6fc_0x700[2]; - u32 i2c0usefpga; /* 0x704 */ - u32 sdmmcusefpga; /* 0x708 */ - u32 _pad_0x70c_0x710[2]; - u32 rgmii0usefpga; /* 0x714 */ - u32 _pad_0x718_0x720[3]; - u32 i2c3usefpga; /* 0x724 */ - u32 i2c2usefpga; /* 0x728 */ - u32 i2c1usefpga; /* 0x72c */ - u32 spim1usefpga; /* 0x730 */ - u32 _pad_0x734; - u32 spim0usefpga; /* 0x738 */ -}; +#define SYSMGR_GEN5_WDDBG 0x10 +#define SYSMGR_GEN5_BOOTINFO 0x14 +#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20 +#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24 +#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28 +#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30 +#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80 +#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0 +#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0 +#define SYSMGR_GEN5_SDMMC 0x108 +#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144 +#define SYSMGR_GEN5_EMACIO 0x400 +#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0 +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8 +#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708 +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704 +#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730 +#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738 + +#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC + +#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \ + SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32)) #endif #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h deleted file mode 100644 index 297f9e1999..0000000000 --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> - * - */ - -#ifndef _SYSTEM_MANAGER_S10_ -#define _SYSTEM_MANAGER_S10_ - -void sysmgr_pinmux_init(void); -void populate_sysmgr_fpgaintf_module(void); -void populate_sysmgr_pinmux(void); -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); - -struct socfpga_system_manager { - /* System Manager Module */ - u32 siliconid1; /* 0x00 */ - u32 siliconid2; - u32 wddbg; - u32 _pad_0xc; - u32 mpu_status; /* 0x10 */ - u32 mpu_ace; - u32 _pad_0x18_0x1c[2]; - u32 dma; /* 0x20 */ - u32 dma_periph; - /* SDMMC Controller Group */ - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - /* NAND Flash Controller Register Group */ - u32 nandgrp_bootstrap; /* 0x30 */ - u32 nandgrp_l3master; - /* USB Controller Group */ - u32 usb0_l3master; - u32 usb1_l3master; - /* EMAC Group */ - u32 emac_gbl; /* 0x40 */ - u32 emac0; - u32 emac1; - u32 emac2; - u32 emac0_ace; /* 0x50 */ - u32 emac1_ace; - u32 emac2_ace; - u32 nand_axuser; - u32 _pad_0x60_0x64[2]; /* 0x60 */ - /* FPGA interface Group */ - u32 fpgaintf_en_1; - u32 fpgaintf_en_2; - u32 fpgaintf_en_3; /* 0x70 */ - u32 dma_l3master; - u32 etr_l3master; - u32 _pad_0x7c; - u32 sec_ctrl_slt; /* 0x80 */ - u32 osc_trim; - u32 _pad_0x88_0x8c[2]; - /* ECC Group */ - u32 ecc_intmask_value; /* 0x90 */ - u32 ecc_intmask_set; - u32 ecc_intmask_clr; - u32 ecc_intstatus_serr; - u32 ecc_intstatus_derr; /* 0xa0 */ - u32 _pad_0xa4_0xac[3]; - u32 noc_addr_remap; /* 0xb0 */ - u32 hmc_clk; - u32 io_pa_ctrl; - u32 _pad_0xbc; - /* NOC Group */ - u32 noc_timeout; /* 0xc0 */ - u32 noc_idlereq_set; - u32 noc_idlereq_clr; - u32 noc_idlereq_value; - u32 noc_idleack; /* 0xd0 */ - u32 noc_idlestatus; - u32 fpga2soc_ctrl; - u32 fpga_config; - u32 iocsrclk_gate; /* 0xe0 */ - u32 gpo; - u32 gpi; - u32 _pad_0xec; - u32 mpu; /* 0xf0 */ - u32 sdm_hps_spare; - u32 hps_sdm_spare; - u32 _pad_0xfc_0x1fc[65]; - /* Boot scratch register group */ - u32 boot_scratch_cold0; /* 0x200 */ - u32 boot_scratch_cold1; - u32 boot_scratch_cold2; - u32 boot_scratch_cold3; - u32 boot_scratch_cold4; /* 0x210 */ - u32 boot_scratch_cold5; - u32 boot_scratch_cold6; - u32 boot_scratch_cold7; - u32 boot_scratch_cold8; /* 0x220 */ - u32 boot_scratch_cold9; - u32 _pad_0x228_0xffc[886]; - /* Pin select and pin control group */ - u32 pinsel0[40]; /* 0x1000 */ - u32 _pad_0x10a0_0x10fc[24]; - u32 pinsel40[8]; - u32 _pad_0x1120_0x112c[4]; - u32 ioctrl0[28]; - u32 _pad_0x11a0_0x11fc[24]; - u32 ioctrl28[20]; - u32 _pad_0x1250_0x12fc[44]; - /* Use FPGA mux */ - u32 rgmii0usefpga; /* 0x1300 */ - u32 rgmii1usefpga; - u32 rgmii2usefpga; - u32 i2c0usefpga; - u32 i2c1usefpga; - u32 i2c_emac0_usefpga; - u32 i2c_emac1_usefpga; - u32 i2c_emac2_usefpga; - u32 nandusefpga; - u32 _pad_0x1324; - u32 spim0usefpga; - u32 spim1usefpga; - u32 spis0usefpga; - u32 spis1usefpga; - u32 uart0usefpga; - u32 uart1usefpga; - u32 mdio0usefpga; - u32 mdio1usefpga; - u32 mdio2usefpga; - u32 _pad_0x134c; - u32 jtagusefpga; - u32 sdmmcusefpga; - u32 hps_osc_clk; - u32 _pad_0x135c_0x13fc[41]; - u32 iodelay0[40]; - u32 _pad_0x14a0_0x14fc[24]; - u32 iodelay40[8]; - -}; - -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) -#define SYSMGR_ECC_OCRAM_EN BIT(0) -#define SYSMGR_ECC_OCRAM_SERR BIT(3) -#define SYSMGR_ECC_OCRAM_DERR BIT(4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1 - -#define SYSMGR_FPGAINTF_NAND BIT(4) -#define SYSMGR_FPGAINTF_SDMMC BIT(8) -#define SYSMGR_FPGAINTF_SPIM0 BIT(16) -#define SYSMGR_FPGAINTF_SPIM1 BIT(24) -#define SYSMGR_FPGAINTF_EMAC0 BIT(0) -#define SYSMGR_FPGAINTF_EMAC1 BIT(8) -#define SYSMGR_FPGAINTF_EMAC2 BIT(16) - -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 -#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 - -/* EMAC Group Bit definitions */ -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 - -#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 - -#define SYSMGR_NOC_H2F_MSK 0x00000001 -#define SYSMGR_NOC_LWH2F_MSK 0x00000010 -#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 - -#define SYSMGR_DMA_IRQ_NS 0xFF000000 -#define SYSMGR_DMA_MGR_NS 0x00010000 - -#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF - -#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F - -#endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h new file mode 100644 index 0000000000..3a6c9515c6 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _SYSTEM_MANAGER_SOC64_H_ +#define _SYSTEM_MANAGER_SOC64_H_ + +void sysmgr_pinmux_init(void); +void populate_sysmgr_fpgaintf_module(void); +void populate_sysmgr_pinmux(void); +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); + +#define SYSMGR_SOC64_WDDBG 0x08 +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 +#define SYSMGR_SOC64_EMAC0 0x44 +#define SYSMGR_SOC64_EMAC1 0x48 +#define SYSMGR_SOC64_EMAC2 0x4c +#define SYSMGR_SOC64_EMAC0_ACE 0x50 +#define SYSMGR_SOC64_EMAC1_ACE 0x54 +#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#define SYSMGR_SOC64_NAND_AXUSER 0x5c +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_DMA_L3MASTER 0x74 +#define SYSMGR_SOC64_HMC_CLK 0xb4 +#define SYSMGR_SOC64_IO_PA_CTRL 0xb8 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xdc +#define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 +#define SYSMGR_SOC64_GPO 0xe4 +#define SYSMGR_SOC64_GPI 0xe8 +#define SYSMGR_SOC64_MPU 0xf0 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SOC64_PINSEL0 0x1000 +#define SYSMGR_SOC64_IOCTRL0 0x1130 +#define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 +#define SYSMGR_SOC64_EMAC1_USEFPGA 0x1304 +#define SYSMGR_SOC64_EMAC2_USEFPGA 0x1308 +#define SYSMGR_SOC64_I2C0_USEFPGA 0x130c +#define SYSMGR_SOC64_I2C1_USEFPGA 0x1310 +#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA 0x1314 +#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA 0x1318 +#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA 0x131c +#define SYSMGR_SOC64_NAND_USEFPGA 0x1320 +#define SYSMGR_SOC64_SPIM0_USEFPGA 0x1328 +#define SYSMGR_SOC64_SPIM1_USEFPGA 0x132c +#define SYSMGR_SOC64_SPIS0_USEFPGA 0x1330 +#define SYSMGR_SOC64_SPIS1_USEFPGA 0x1334 +#define SYSMGR_SOC64_UART0_USEFPGA 0x1338 +#define SYSMGR_SOC64_UART1_USEFPGA 0x133c +#define SYSMGR_SOC64_MDIO0_USEFPGA 0x1340 +#define SYSMGR_SOC64_MDIO1_USEFPGA 0x1344 +#define SYSMGR_SOC64_MDIO2_USEFPGA 0x1348 +#define SYSMGR_SOC64_JTAG_USEFPGA 0x1350 +#define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354 +#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 +#define SYSMGR_SOC64_IODELAY0 0x1400 + +#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 + +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(8) +#define SYSMGR_FPGAINTF_SPIM0 BIT(16) +#define SYSMGR_FPGAINTF_SPIM1 BIT(24) +#define SYSMGR_FPGAINTF_EMAC0 BIT(0) +#define SYSMGR_FPGAINTF_EMAC1 BIT(8) +#define SYSMGR_FPGAINTF_EMAC2 BIT(16) + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#define SYSMGR_NOC_H2F_MSK 0x00000001 +#define SYSMGR_NOC_LWH2F_MSK 0x00000010 +#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 + +#define SYSMGR_DMA_IRQ_NS 0xFF000000 +#define SYSMGR_DMA_MGR_NS 0x00010000 + +#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF + +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F + +#endif /* _SYSTEM_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4498ab55df..3254bc1805 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -287,9 +287,6 @@ int mbox_qspi_close(void) int mbox_qspi_open(void) { - static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - int ret; u32 resp_buf[1]; u32 resp_buf_len; @@ -318,7 +315,8 @@ int mbox_qspi_open(void) /* We are getting QSPI ref clock and set into sysmgr boot register */ printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); - writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0); + writel(resp_buf[0], + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); return 0; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 904b3d030a..db71105af3 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -23,6 +23,10 @@ DECLARE_GLOBAL_DATA_PTR; +phys_addr_t socfpga_clkmgr_base __section(".data"); +phys_addr_t socfpga_rstmgr_base __section(".data"); +phys_addr_t socfpga_sysmgr_base __section(".data"); + #ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -146,6 +150,8 @@ void socfpga_fpga_add(void *fpga_desc) int arch_cpu_init(void) { + socfpga_get_managers_addr(); + #ifdef CONFIG_HW_WATCHDOG /* * In case the watchdog is enabled, make sure to (re-)configure it @@ -203,3 +209,63 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge, ); #endif + +static int socfpga_get_base_addr(const char *compat, phys_addr_t *base) +{ + const void *blob = gd->fdt_blob; + struct fdt_resource r; + int node; + int ret; + + node = fdt_node_offset_by_compatible(blob, -1, compat); + if (node < 0) + return node; + + if (!fdtdec_get_is_enabled(blob, node)) + return -ENODEV; + + ret = fdt_get_resource(blob, node, "reg", 0, &r); + if (ret) + return ret; + + *base = (phys_addr_t)r.start; + + return 0; +} + +void socfpga_get_managers_addr(void) +{ + int ret; + + ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base); + if (ret) + hang(); + + ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); + if (ret) + hang(); + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX + ret = socfpga_get_base_addr("intel,agilex-clkmgr", + &socfpga_clkmgr_base); +#else + ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); +#endif + if (ret) + hang(); +} + +phys_addr_t socfpga_get_rstmgr_addr(void) +{ + return socfpga_rstmgr_base; +} + +phys_addr_t socfpga_get_sysmgr_addr(void) +{ + return socfpga_sysmgr_base; +} + +phys_addr_t socfpga_get_clkmgr_addr(void) +{ + return socfpga_clkmgr_base; +} diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 2e2a40b65d..d56349b7f3 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -28,9 +28,6 @@ #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* * FPGA programming support for SoC FPGA Arria 10 */ @@ -81,7 +78,8 @@ void socfpga_init_security_policies(void) writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); - writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); + writel(0x0007FFFF, + socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET); } void socfpga_sdram_remap_zero(void) @@ -105,8 +103,9 @@ int arch_early_init_r(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - const u32 bsel = - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); + const u32 bootinfo = readl(socfpga_get_sysmgr_addr() + + SYSMGR_A10_BOOTINFO); + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo); puts("CPU: Altera SoCFPGA Arria 10\n"); diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 22042d0de0..35938b2dfc 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = @@ -120,8 +118,9 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - const u32 bsel = - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); + const u32 bootinfo = readl(socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_BOOTINFO); + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo); puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); @@ -134,7 +133,8 @@ int print_cpuinfo(void) #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; + const u32 bsel = readl(socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_BOOTINFO) & 0x7; const int fpga_id = socfpga_fpga_id(0); env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) @@ -192,10 +192,12 @@ int arch_early_init_r(void) * to support that old code, we write it here instead of in the * reset_cpu() function just before resetting the CPU. */ - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); + writel(0xae9efebc, + socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN); for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(i)); socfpga_bridges_reset(1); @@ -208,8 +210,6 @@ int arch_early_init_r(void) } #ifndef CONFIG_SPL_BUILD -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; @@ -223,20 +223,26 @@ void do_bridge_reset(int enable, unsigned int mask) !(mask & BIT(2))); for (i = 0; i < 2; i++) { /* Reload SW setting cache */ iswgrp_handoff[i] = - readl(&sysmgr_regs->iswgrp_handoff[i]); + readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(i)); } - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + writel(iswgrp_handoff[2], + socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_FPGAINFGRP_MODULE); writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[0], + socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); writel(iswgrp_handoff[1], &nic301_regs->remap); - writel(0x7, &reset_manager_base->brg_mod_reset); - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); + writel(iswgrp_handoff[0], + socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); } else { - writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_FPGAINFGRP_MODULE); writel(0, &sdr_ctrl->fpgaport_rst); - writel(0x7, &reset_manager_base->brg_mod_reset); + writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); writel(1, &nic301_regs->remap); } } diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 0a5fab11c0..a3f5b4364e 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -23,9 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* * FPGA programming support for SoC FPGA Stratix 10 */ @@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) else return -EINVAL; - clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, - modereg); + clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 + + gmac_index, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); return 0; } diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 471a3045af..aa5299415a 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -15,11 +15,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - struct bridge_cfg { int compat_id; u32 mask_noc; @@ -63,14 +58,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = { void socfpga_watchdog_disable(void) { /* assert reset for watchdog */ - setbits_le32(&reset_manager_base->per1modrst, + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); } /* Release NOC ddr scheduler from reset */ void socfpga_reset_deassert_noc_ddr_scheduler(void) { - clrbits_le32(&reset_manager_base->brgmodrst, + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK); } @@ -100,20 +95,23 @@ int socfpga_reset_deassert_bridges_handoff(void) } /* clear idle request to all bridges */ - setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR, + mask_noc); /* Release bridges from reset state per handoff value */ - clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, + mask_rstmgr); /* Poll until all idleack to 0, timeout at 1000ms */ - return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc, - false, 1000, false); + return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + + SYSMGR_A10_NOC_IDLEACK), + mask_noc, false, 1000, false); } /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */ void socfpga_reset_deassert_osc1wd0(void) { - clrbits_le32(&reset_manager_base->per1modrst, + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); } @@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void) */ void socfpga_per_reset(u32 reset, int set) { - const u32 *reg; + unsigned long reg; u32 rstmgr_bank = RSTMGR_BANK(reset); switch (rstmgr_bank) { case 0: - reg = &reset_manager_base->mpumodrst; + reg = RSTMGR_A10_MPUMODRST; break; case 1: - reg = &reset_manager_base->per0modrst; + reg = RSTMGR_A10_PER0MODRST; break; case 2: - reg = &reset_manager_base->per1modrst; + reg = RSTMGR_A10_PER1MODRST; break; case 3: - reg = &reset_manager_base->brgmodrst; + reg = RSTMGR_A10_BRGMODRST; break; case 4: - reg = &reset_manager_base->sysmodrst; + reg = RSTMGR_A10_SYSMODRST; break; default: @@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set) } if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + setbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); + clrbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); } /* @@ -174,11 +174,13 @@ void socfpga_per_reset_all(void) ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ - writel(~l4wd0, &reset_manager_base->per1modrst); - setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp); + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, + ~mask_ecc_ocp); /* Finally disable the ECC_OCP */ - setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, + mask_ecc_ocp); } int socfpga_bridges_reset(void) @@ -194,13 +196,15 @@ int socfpga_bridges_reset(void) ALT_SYSMGR_NOC_F2SDR0_SET_MSK | ALT_SYSMGR_NOC_F2SDR1_SET_MSK | ALT_SYSMGR_NOC_F2SDR2_SET_MSK, - &sysmgr_regs->noc_idlereq_set); + socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET); /* Enable the NOC timeout */ - writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout); + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, + socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack, + ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + + SYSMGR_A10_NOC_IDLEACK), ALT_SYSMGR_NOC_H2F_SET_MSK | ALT_SYSMGR_NOC_LWH2F_SET_MSK | ALT_SYSMGR_NOC_F2H_SET_MSK | @@ -212,7 +216,8 @@ int socfpga_bridges_reset(void) return ret; /* Poll until all idlestatus to 1 */ - ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus, + ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + + SYSMGR_A10_NOC_IDLESTATUS), ALT_SYSMGR_NOC_H2F_SET_MSK | ALT_SYSMGR_NOC_LWH2F_SET_MSK | ALT_SYSMGR_NOC_F2H_SET_MSK | @@ -224,16 +229,16 @@ int socfpga_bridges_reset(void) return ret; /* Put all bridges (except NOR DDR scheduler) into reset state */ - setbits_le32(&reset_manager_base->brgmodrst, + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK | - ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK | - ALT_RSTMGR_BRGMODRST_F2H_SET_MSK | - ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK | - ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK | - ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK)); + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK)); /* Disable NOC timeout */ - writel(0, &sysmgr_regs->noc_timeout); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT); return 0; } diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9a32f5abfe..1008a78dc8 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -10,32 +10,27 @@ #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { - const u32 *reg; + unsigned long reg; u32 rstmgr_bank = RSTMGR_BANK(reset); switch (rstmgr_bank) { case 0: - reg = &reset_manager_base->mpu_mod_reset; + reg = RSTMGR_GEN5_MPUMODRST; break; case 1: - reg = &reset_manager_base->per_mod_reset; + reg = RSTMGR_GEN5_PERMODRST; break; case 2: - reg = &reset_manager_base->per2_mod_reset; + reg = RSTMGR_GEN5_PER2MODRST; break; case 3: - reg = &reset_manager_base->brg_mod_reset; + reg = RSTMGR_GEN5_BRGMODRST; break; case 4: - reg = &reset_manager_base->misc_mod_reset; + reg = RSTMGR_GEN5_MISCMODRST; break; default: @@ -43,9 +38,11 @@ void socfpga_per_reset(u32 reset, int set) } if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + setbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); + clrbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); } /* @@ -57,8 +54,8 @@ void socfpga_per_reset_all(void) { const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); - writel(~l4wd0, &reset_manager_base->per_mod_reset); - writel(0xffffffff, &reset_manager_base->per2_mod_reset); + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PERMODRST); + writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PER2MODRST); } #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 @@ -83,8 +80,10 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h) if (f2h) brgmask |= BIT(2); - writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]); + writel(brgmask, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(0)); + writel(l3rmask, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(1)); } void socfpga_bridges_reset(int enable) @@ -95,7 +94,7 @@ void socfpga_bridges_reset(int enable) if (enable) { /* brdmodrst */ - writel(0x7, &reset_manager_base->brg_mod_reset); + writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS); } else { socfpga_bridges_set_handoff_regs(false, false, false); @@ -109,7 +108,7 @@ void socfpga_bridges_reset(int enable) } /* brdmodrst */ - writel(0, &reset_manager_base->brg_mod_reset); + writel(0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); /* Remap the bridges into memory map */ writel(l3mask, SOCFPGA_L3REGS_ADDRESS); diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 499a84aff5..c7430777b2 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -12,31 +12,28 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; - /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { - const void *reg; + unsigned long reg; if (RSTMGR_BANK(reset) == 0) - reg = &reset_manager_base->mpumodrst; + reg = RSTMGR_SOC64_MPUMODRST; else if (RSTMGR_BANK(reset) == 1) - reg = &reset_manager_base->per0modrst; + reg = RSTMGR_SOC64_PER0MODRST; else if (RSTMGR_BANK(reset) == 2) - reg = &reset_manager_base->per1modrst; + reg = RSTMGR_SOC64_PER1MODRST; else if (RSTMGR_BANK(reset) == 3) - reg = &reset_manager_base->brgmodrst; + reg = RSTMGR_SOC64_BRGMODRST; else /* Invalid reset register, do nothing */ return; if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + setbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); + clrbits_le32(socfpga_get_rstmgr_addr() + reg, + 1 << RSTMGR_RESET(reset)); } /* @@ -50,47 +47,52 @@ void socfpga_per_reset_all(void) /* disable all except OCP and l4wd0. OCP disable later */ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), - &reset_manager_base->per0modrst); - writel(~l4wd0, &reset_manager_base->per0modrst); - writel(0xffffffff, &reset_manager_base->per1modrst); + socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST); + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST); + writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } void socfpga_bridges_reset(int enable) { if (enable) { /* clear idle request to all bridges */ - setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); /* Release all bridges from reset state */ - clrbits_le32(&reset_manager_base->brgmodrst, ~0); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + ~0); /* Poll until all idleack to 0 */ - while (readl(&system_manager_base->noc_idleack)) + while (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK)) ; } else { /* set idle request to all bridges */ - writel(~0, &system_manager_base->noc_idlereq_set); + writel(~0, + socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET); /* Enable the NOC timeout */ - writel(1, &system_manager_base->noc_timeout); + writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - while ((readl(&system_manager_base->noc_idleack) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; /* Poll until all idlestatus to 1 */ - while ((readl(&system_manager_base->noc_idlestatus) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; /* Reset all bridges (except NOR DDR scheduler & F2S) */ - setbits_le32(&reset_manager_base->brgmodrst, + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + RSTMGR_BRGMODRST_FPGA2SOC_MASK)); /* Disable NOC timeout */ - writel(0, &system_manager_base->noc_timeout); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } } @@ -99,6 +101,6 @@ void socfpga_bridges_reset(int enable) */ int cpu_has_been_warmreset(void) { - return readl(&reset_manager_base->status) & - RSTMGR_L4WD_MPU_WARMRESET_MASK; + return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; } diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c index 52175af48b..f7ee28915e 100644 --- a/arch/arm/mach-socfpga/scan_manager.c +++ b/arch/arm/mach-socfpga/scan_manager.c @@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base = (void *)(SOCFPGA_SCANMGR_ADDRESS); static const struct socfpga_freeze_controller *freeze_controller_base = (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); -static struct socfpga_system_manager *sys_mgr_base = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /** * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle @@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void) int ret; /* Enable HPS to talk to JTAG in the FPGA through the System Manager */ - writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl); + writel(0x1, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL); /* Enable port 7 */ writel(0x80, &scan_manager_base->en); @@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void) /* Disable all port */ writel(0, &scan_manager_base->en); - writel(0, &sys_mgr_base->scanmgrgrp_ctrl); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL); return id; } diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d36732447b..7c38c50981 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -32,12 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - u32 spl_boot_device(void) { - const u32 bsel = readl(&sysmgr_regs->bootinfo); + const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO); switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ @@ -107,6 +104,11 @@ void spl_board_init(void) void board_init_f(ulong dummy) { + if (spl_early_init()) + hang(); + + socfpga_get_managers_addr(); + dcache_disable(); socfpga_init_security_policies(); @@ -117,8 +119,6 @@ void board_init_f(ulong dummy) socfpga_per_reset_all(); socfpga_watchdog_disable(); - spl_early_init(); - /* Configure the clock based on handoff */ cm_basic_init(gd->fdt_blob); diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c new file mode 100644 index 0000000000..c745d64114 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <common.h> +#include <image.h> +#include <spl.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <watchdog.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + +#ifdef CONFIG_HW_WATCHDOG + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + /* Enable watchdog before initializing the HW */ + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); + hw_watchdog_init(); +#endif + + /* ensure all processors are not released prior Linux boot */ + writeq(0, CPU_RELEASE_ADDR); + + timer_init(); + + sysmgr_pinmux_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + cm_print_clock_quick_summary(); + + firewall_setup(); + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); + if (ret) { + debug("CCU init failed: %d\n", ret); + hang(); + } + +#if CONFIG_IS_ENABLED(ALTERA_SDRAM) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } +#endif + + mbox_init(); + +#ifdef CONFIG_CADENCE_QSPI + mbox_qspi_open(); +#endif +} diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 408e409375..e19f55aa9b 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -24,12 +24,10 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - u32 spl_boot_device(void) { - const u32 bsel = readl(&sysmgr_regs->bootinfo); + const u32 bsel = readl(socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_BOOTINFO); switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ @@ -67,17 +65,23 @@ void board_init_f(ulong dummy) int ret; struct udevice *dev; + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + /* - * First C code to run. Clear fake OCRAM ECC first as SBE + * Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on */ - reg = readl(&sysmgr_regs->eccgrp_ocram); + reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM); if (reg & SYSMGR_ECC_OCRAM_SERR) writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); + socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM); if (reg & SYSMGR_ECC_OCRAM_DERR) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); + socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM); socfpga_sdram_remap_zero(); socfpga_pl310_clear(); @@ -128,12 +132,6 @@ void board_init_f(ulong dummy) debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - ret = uclass_get_device(UCLASS_RESET, 0, &dev); if (ret) debug("Reset init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index ec65e1ce64..8d96918cb4 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -12,8 +12,9 @@ #include <image.h> #include <spl.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/firewall_s10.h> +#include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <watchdog.h> @@ -21,9 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - u32 spl_boot_device(void) { /* TODO: Get from SDM or handoff */ @@ -41,88 +39,21 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -void spl_disable_firewall_l4_per(void) -{ - const struct socfpga_firwall_l4_per *firwall_l4_per_base = - (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; - u32 i; - const u32 *addr[] = { - &firwall_l4_per_base->nand, - &firwall_l4_per_base->nand_data, - &firwall_l4_per_base->usb0, - &firwall_l4_per_base->usb1, - &firwall_l4_per_base->spim0, - &firwall_l4_per_base->spim1, - &firwall_l4_per_base->emac0, - &firwall_l4_per_base->emac1, - &firwall_l4_per_base->emac2, - &firwall_l4_per_base->sdmmc, - &firwall_l4_per_base->gpio0, - &firwall_l4_per_base->gpio1, - &firwall_l4_per_base->i2c0, - &firwall_l4_per_base->i2c1, - &firwall_l4_per_base->i2c2, - &firwall_l4_per_base->i2c3, - &firwall_l4_per_base->i2c4, - &firwall_l4_per_base->timer0, - &firwall_l4_per_base->timer1, - &firwall_l4_per_base->uart0, - &firwall_l4_per_base->uart1 - }; - - /* - * The following lines of code will enable non-secure access - * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This - * is needed as most OS run in non-secure mode. Thus we need to - * enable non-secure access to these peripherals in order for the - * OS to use these peripherals. - */ - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - -void spl_disable_firewall_l4_sys(void) -{ - const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = - (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; - u32 i; - const u32 *addr[] = { - &firwall_l4_sys_base->dma_ecc, - &firwall_l4_sys_base->emac0rx_ecc, - &firwall_l4_sys_base->emac0tx_ecc, - &firwall_l4_sys_base->emac1rx_ecc, - &firwall_l4_sys_base->emac1tx_ecc, - &firwall_l4_sys_base->emac2rx_ecc, - &firwall_l4_sys_base->emac2tx_ecc, - &firwall_l4_sys_base->nand_ecc, - &firwall_l4_sys_base->nand_read_ecc, - &firwall_l4_sys_base->nand_write_ecc, - &firwall_l4_sys_base->ocram_ecc, - &firwall_l4_sys_base->sdmmc_ecc, - &firwall_l4_sys_base->usb0_ecc, - &firwall_l4_sys_base->usb1_ecc, - &firwall_l4_sys_base->clock_manager, - &firwall_l4_sys_base->io_manager, - &firwall_l4_sys_base->reset_manager, - &firwall_l4_sys_base->system_manager, - &firwall_l4_sys_base->watchdog0, - &firwall_l4_sys_base->watchdog1, - &firwall_l4_sys_base->watchdog2, - &firwall_l4_sys_base->watchdog3 - }; - - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); int ret; + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + #ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); @@ -145,29 +76,11 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(UART0), 0); debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } preloader_console_init(); cm_print_clock_quick_summary(); - /* enable non-secure interface to DMA330 DMA and peripherals */ - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); - writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); - - spl_disable_firewall_l4_per(); - - spl_disable_firewall_l4_sys(); - - /* disable lwsocf2fpga and soc2fpga bridge security */ - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); - - /* disable SMMU security */ - writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); + firewall_setup(); /* disable ocram security at CCU for non secure access */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c index 9d04aea2a8..09caebb3c8 100644 --- a/arch/arm/mach-socfpga/system_manager_gen5.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -8,9 +8,6 @@ #include <asm/arch/system_manager.h> #include <asm/arch/fpga_manager.h> -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. * The value is not wrote to SYSMGR.FPGAINTF.MODULE but @@ -21,30 +18,41 @@ static void populate_sysmgr_fpgaintf_module(void) u32 handoff_val = 0; /* ISWGRP_HANDOFF_FPGAINTF */ - writel(0, &sysmgr_regs->iswgrp_handoff[2]); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(2)); /* Enable the signal for those HPS peripherals that use FPGA. */ - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_NAND_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_NAND; - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII1_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC1; - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SDMMC_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SDMMC; - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII0_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC0; - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM0_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM0; - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM1_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM1; /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting */ - setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(2), + handoff_val); - handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); + handoff_val = readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(2)); if (fpgamgr_test_fpga_ready()) { /* Enable the required signals only */ - writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); + writel(handoff_val, + socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_FPGAINFGRP_MODULE); } } @@ -53,7 +61,7 @@ static void populate_sysmgr_fpgaintf_module(void) */ void sysmgr_pinmux_init(void) { - u32 regs = (u32)&sysmgr_regs->emacio[0]; + u32 regs = (u32)socfpga_get_sysmgr_addr() + SYSMGR_GEN5_EMACIO; const u8 *sys_mgr_init_table; unsigned int len; int i; @@ -74,9 +82,11 @@ void sysmgr_pinmux_init(void) void sysmgr_config_warmrstcfgio(int enable) { if (enable) - setbits_le32(&sysmgr_regs->romcodegrp_ctrl, + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_ROMCODEGRP_CTRL, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); else - clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_GEN5_ROMCODEGRP_CTRL, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); } diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c index 122828c9ce..cdda881efd 100644 --- a/arch/arm/mach-socfpga/system_manager_s10.c +++ b/arch/arm/mach-socfpga/system_manager_s10.c @@ -10,9 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - /* * Configure all the pin muxes */ @@ -32,24 +29,33 @@ void populate_sysmgr_fpgaintf_module(void) u32 handoff_val = 0; /* Enable the signal for those HPS peripherals that use FPGA. */ - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_NAND; - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SDMMC; - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM0; - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM1; - writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); + writel(handoff_val, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2); handoff_val = 0; - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC0; - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC1; - if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) + if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) == + SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC2; - writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); + writel(handoff_val, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3); } /* @@ -64,14 +70,16 @@ void populate_sysmgr_pinmux(void) sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); + sys_mgr_table_u32[i] + + (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0); } /* setup the pin ctrl */ sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); + sys_mgr_table_u32[i] + + (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0); } /* setup the fpga use */ @@ -79,13 +87,15 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] + - (u8 *)&sysmgr_regs->rgmii0usefpga); + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_EMAC0_USEFPGA); } /* setup the IO delay */ sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); + sys_mgr_table_u32[i] + + (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0); } } diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 7cafc7dcfc..3da85791a1 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -10,9 +10,6 @@ #include <asm/arch/handoff_s10.h> #include <asm/arch/system_manager.h> -static const struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - const struct cm_config * const cm_get_default_config(void) { struct cm_config *cm_handoff_cfg = (struct cm_config *) @@ -36,11 +33,14 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_OSC); - writel(clock, &sysmgr_regs->boot_scratch_cold1); + u32 clock = readl(HANDOFF_CLOCK_OSC); + + writel(clock, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif - return readl(&sysmgr_regs->boot_scratch_cold1); + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); } const unsigned int cm_get_intosc_clk_hz(void) @@ -51,9 +51,11 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); + u32 clock = readl(HANDOFF_CLOCK_FPGA); - writel(clock, &sysmgr_regs->boot_scratch_cold2); + writel(clock, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif - return readl(&sysmgr_regs->boot_scratch_cold2); + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); } diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index ed7d9f61dc..6a71465494 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -35,7 +35,9 @@ #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) #define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) #define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) /* DBGMCU register */ #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) @@ -206,6 +208,11 @@ int arch_cpu_init(void) security_init(); update_bootmode(); #endif + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } #endif boot_mode = get_bootmode(); diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index b3e9ccc5d3..88126b8cdb 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -86,9 +86,18 @@ enum boot_device { #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) +#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) +#define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) +#define TAMP_COPRO_STATE_OFF 0 +#define TAMP_COPRO_STATE_INIT 1 +#define TAMP_COPRO_STATE_CRUN 2 +#define TAMP_COPRO_STATE_CSTOP 3 +#define TAMP_COPRO_STATE_STANDBY 4 +#define TAMP_COPRO_STATE_CRASH 5 + #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) |