summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi12
-rw-r--r--arch/arm/dts/k3-j721e-common-proc-board.dts27
-rw-r--r--arch/arm/dts/k3-j721e-main.dtsi99
-rw-r--r--arch/arm/dts/k3-j721e-mcu-wakeup.dtsi22
-rw-r--r--arch/arm/dts/k3-j721e-r5-common-proc-board.dts45
-rw-r--r--arch/arm/dts/k3-j721e.dtsi10
-rw-r--r--arch/arm/mach-k3/include/mach/j721e_spl.h2
-rw-r--r--arch/arm/mach-k3/sysfw-loader.c30
8 files changed, 246 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 7ea4d8de36..a3a8193216 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -337,3 +337,15 @@
&wkup_i2c0 {
u-boot,dm-spl;
};
+
+&main_i2c0 {
+ u-boot,dm-spl;
+};
+
+&main_i2c0_pins_default {
+ u-boot,dm-spl;
+};
+
+&exp2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index f33a6d5bcf..d216b707fd 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -107,6 +107,13 @@
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
};
&wkup_pmx0 {
@@ -145,3 +152,23 @@
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ exp2: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 5083a0c3ae..45ac98c47e 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -200,6 +200,28 @@
clock-names = "fclk";
};
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+ <105 1 IRQ_TYPE_EDGE_RISING>,
+ <105 2 IRQ_TYPE_EDGE_RISING>,
+ <105 3 IRQ_TYPE_EDGE_RISING>,
+ <105 4 IRQ_TYPE_EDGE_RISING>,
+ <105 5 IRQ_TYPE_EDGE_RISING>,
+ <105 6 IRQ_TYPE_EDGE_RISING>,
+ <105 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <128>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 0>;
+ clock-names = "gpio";
+ };
+
main_sdhci0: sdhci@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
@@ -433,4 +455,81 @@
dma-coherent;
};
};
+
+ main_i2c0: i2c@2000000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2000000 0x0 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 187 0>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c1: i2c@2010000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2010000 0x0 0x100>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 188 0>;
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c2: i2c@2020000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2020000 0x0 0x100>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 189 0>;
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c3: i2c@2030000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2030000 0x0 0x100>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 190 0>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c4: i2c@2040000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2040000 0x0 0x100>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 191 0>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c5: i2c@2050000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2050000 0x0 0x100>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 192 0>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c6: i2c@2060000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2060000 0x0 0x100>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 193 0>;
+ power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 5dd07ac4da..fe52fd1b2f 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -144,4 +144,26 @@
assigned-clock-rates = <250000000>;
};
};
+
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x40b00000 0x0 0x100>;
+ interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 194 0>;
+ power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ mcu_i2c1: i2c@40b10000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x40b10000 0x0 0x100>;
+ interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 195 0>;
+ power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 28a355d49c..1f14d71438 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -40,6 +40,13 @@
clock-frequency = <200000000>;
u-boot,dm-spl;
};
+
+ clk_19_2mhz: dummy_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ u-boot,dm-spl;
+ };
};
&cbass_mcu_wakeup {
@@ -133,6 +140,13 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
};
&wkup_uart0 {
@@ -207,4 +221,35 @@
u-boot,dm-spl;
};
+&usbss0 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clocks = <&clk_19_2mhz>;
+ clock-names = "usb2_refclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ exp2: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
#include "k3-j721e-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
index aea17e25a2..68ba517e50 100644
--- a/arch/arm/dts/k3-j721e.dtsi
+++ b/arch/arm/dts/k3-j721e.dtsi
@@ -30,6 +30,16 @@
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
+ i2c4 = &main_i2c1;
+ i2c5 = &main_i2c2;
+ i2c6 = &main_i2c3;
+ i2c7 = &main_i2c4;
+ i2c8 = &main_i2c5;
+ i2c9 = &main_i2c6;
};
chosen { };
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index 2b52faf944..475278bd04 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -18,7 +18,7 @@
/* With BootMode B = 1 */
#define BOOT_DEVICE_MMC2 0x10
#define BOOT_DEVICE_MMC1 0x11
-#define BOOT_DEVICE_USB 0x12
+#define BOOT_DEVICE_DFU 0x12
#define BOOT_DEVICE_UFS 0x13
#define BOOT_DEVIE_GPMC 0x14
#define BOOT_DEVICE_PCIE 0x15
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 5903bbe12a..94dbeb9437 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -11,6 +11,10 @@
#include <malloc.h>
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <dfu.h>
+
#include <asm/arch/sys_proto.h>
#include "common.h"
@@ -172,6 +176,27 @@ static void k3_sysfw_configure_using_fit(void *fit,
ret);
}
+#if CONFIG_IS_ENABLED(DFU)
+static int k3_sysfw_dfu_download(void *addr)
+{
+ char dfu_str[50];
+ int ret;
+
+ sprintf(dfu_str, "sysfw.itb ram 0x%p 0x%x", addr,
+ CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+ ret = dfu_config_entities(dfu_str, "ram", "0");
+ if (ret) {
+ dfu_free_entities();
+ goto exit;
+ }
+
+ run_usb_dnl_gadget(0, "usb_dnl_dfu");
+exit:
+ dfu_free_entities();
+ return ret;
+}
+#endif
+
void k3_sysfw_loader(void (*config_pm_done_callback)(void))
{
struct spl_image_info spl_image = { 0 };
@@ -236,6 +261,11 @@ void k3_sysfw_loader(void (*config_pm_done_callback)(void))
ret = spl_ymodem_load_image(&spl_image, &bootdev);
break;
#endif
+#if CONFIG_IS_ENABLED(DFU)
+ case BOOT_DEVICE_DFU:
+ ret = k3_sysfw_dfu_download(sysfw_load_address);
+ break;
+#endif
default:
panic("Loading SYSFW image from device %u not supported!\n",
bootdev.boot_device);
generated by cgit (git 2.34.1) at 2025-01-17 05:19:50 +0000