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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/cpu/armv7/arch_timer.c3
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi4
-rw-r--r--arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi8
-rw-r--r--arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi24
-rw-r--r--arch/arm/include/asm/mach-types.h6
-rw-r--r--arch/arm/mach-davinci/Kconfig19
-rw-r--r--arch/arm/mach-omap2/omap3/Kconfig31
-rw-r--r--arch/arm/mach-rmobile/Kconfig11
-rw-r--r--arch/arm/mach-rmobile/Makefile73
-rw-r--r--arch/arm/mach-socfpga/include/mach/misc.h1
-rw-r--r--arch/arm/mach-socfpga/misc.c54
-rw-r--r--arch/arm/mach-socfpga/spl_a10.c1
-rw-r--r--arch/arm/mach-socfpga/spl_gen5.c57
-rw-r--r--arch/arm/mach-stm32mp/Kconfig24
-rw-r--r--arch/arm/mach-stm32mp/bsec.c2
-rw-r--r--arch/arm/mach-stm32mp/include/mach/ddr.h9
-rw-r--r--arch/arm/mach-stm32mp/include/mach/stm32.h1
-rw-r--r--arch/arm/mach-stm32mp/psci.c22
19 files changed, 212 insertions, 139 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index efb9aab390..01ff57cf1b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1488,6 +1488,7 @@ config ARCH_STM32MP
imply CMD_DM
imply CMD_POWEROFF
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+ imply USE_PREBOOT
help
Support for STM32MP SoC family developed by STMicroelectronics,
MPUs based on ARM cortex A core
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 3db31c0209..5de63053d5 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -49,6 +49,9 @@ unsigned long long get_ticks(void)
ulong timer_get_boot_us(void)
{
+ if (!gd->arch.timer_rate_hz)
+ timer_init();
+
return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
}
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index 0446fd441e..60c419251b 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -16,10 +16,6 @@
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
- chosen {
- cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
- };
-
/* Clock sources */
clocks {
#address-cells = <1>;
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 7d9b95ccf1..dc30360b0a 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -16,8 +16,8 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401
@@ -108,11 +108,11 @@
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 8a5a821ec4..8158a56f13 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 and ED2 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
@@ -15,10 +14,11 @@
* timing mode optimized
* Scheduling/QoS options : type = 2
* address mapping : RBC
+ * Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
#define DDR_MSTR 0x00040401
@@ -62,7 +62,7 @@
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00001201
+#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
@@ -74,15 +74,15 @@
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
-#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
-#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
-#define DDR_PCFGQOS0_1 0x02100B03
-#define DDR_PCFGQOS1_1 0x00800100
-#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
@@ -100,7 +100,7 @@
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
-#define DDR_ZQ0CR1 0x0000005B
+#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 9f82efe007..32532b3ca4 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -629,7 +629,6 @@
#define MACH_TYPE_ECIA 623
#define MACH_TYPE_CM4008 624
#define MACH_TYPE_P2001 625
-#define MACH_TYPE_TWISTER 626
#define MACH_TYPE_MUDSHARK 627
#define MACH_TYPE_HB2 628
#define MACH_TYPE_IQ80332 629
@@ -2716,7 +2715,6 @@
#define MACH_TYPE_VPNEXT_MPU 2747
#define MACH_TYPE_BCMRING_TABLET_V1 2748
#define MACH_TYPE_SGARM10 2749
-#define MACH_TYPE_CM_T3517 2750
#define MACH_TYPE_OMAP3_CPS 2751
#define MACH_TYPE_AXAR1500_RECEIVER 2752
#define MACH_TYPE_WBD222 2753
@@ -2960,7 +2958,6 @@
#define MACH_TYPE_AX8008 2999
#define MACH_TYPE_GNET_SGCE 3000
#define MACH_TYPE_PXWNAS_500_1000 3001
-#define MACH_TYPE_EA20 3002
#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
#define MACH_TYPE_SEABOARD 3005
@@ -3475,7 +3472,6 @@
#define MACH_TYPE_SGH_I710 3525
#define MACH_TYPE_INTEGREPROSCB 3526
#define MACH_TYPE_MONZA 3527
-#define MACH_TYPE_CALIMAIN 3528
#define MACH_TYPE_MX6Q_SABREAUTO 3529
#define MACH_TYPE_GMA01X 3530
#define MACH_TYPE_SBC51 3531
@@ -3600,7 +3596,6 @@
#define MACH_TYPE_TAISHAN 3653
#define MACH_TYPE_TOUCHLINK 3654
#define MACH_TYPE_STM32F103ZE 3655
-#define MACH_TYPE_MCX 3656
#define MACH_TYPE_STM_NMHDK_FLI7610 3657
#define MACH_TYPE_TOP28X 3658
#define MACH_TYPE_OKL4VP_MICROVISOR 3659
@@ -3775,7 +3770,6 @@
#define MACH_TYPE_IMXT_NAV 3829
#define MACH_TYPE_IMXT_FULL 3830
#define MACH_TYPE_AG09015 3831
-#define MACH_TYPE_AM3517_MT_VENTOUX 3832
#define MACH_TYPE_DP1ARM9 3833
#define MACH_TYPE_PICASSO_M 3834
#define MACH_TYPE_VIDEO_GADGET 3835
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 12b1e682e6..61e84e5129 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,33 +4,17 @@ choice
prompt "DaVinci board select"
optional
-config TARGET_IPAM390
- bool "IPAM390 board"
- select MACH_DAVINCI_DA850_EVM
- select SOC_DA850
- select SUPPORT_SPL
-
config TARGET_DA850EVM
bool "DA850 EVM board"
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
select SUPPORT_SPL
-config TARGET_EA20
- bool "EA20 board"
- select BOARD_LATE_INIT
- select MACH_DAVINCI_DA850_EVM
- select SOC_DA850
-
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SOC_DA8XX
select SUPPORT_SPL
-config TARGET_CALIMAIN
- bool "Calimain board"
- select SOC_DA850
-
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
select MACH_DAVINCI_DA850_EVM
@@ -146,10 +130,7 @@ config SYS_DA850_PLL1_PLLDIV3
endif
-source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/omicron/calimain/Kconfig"
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 0286b0daa3..d75fab1530 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -34,11 +34,6 @@ config TARGET_AM3517_EVM
select DM_SERIAL
imply CMD_DM
-config TARGET_MT_VENTOUX
- bool "TeeJet Mt.Ventoux"
- select OMAP3_GPIO_4
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
@@ -54,12 +49,6 @@ config TARGET_CM_T35
select OMAP3_GPIO_5
select OMAP3_GPIO_6 if LED_STATUS
-config TARGET_CM_T3517
- bool "CompuLab CM-T3517 boards"
- select OMAP3_GPIO_2
- select OMAP3_GPIO_5
- select OMAP3_GPIO_6 if LED_STATUS
-
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
@@ -112,20 +101,10 @@ config TARGET_OMAP3_PANDORA
select OMAP3_GPIO_4
select OMAP3_GPIO_6
-config TARGET_ECO5PK
- bool "ECO5PK"
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_TRICORDER
bool "Tricorder"
select OMAP3_GPIO_2
-config TARGET_MCX
- bool "MCX"
- select BOARD_LATE_INIT
- select OMAP3_GPIO_2 if USB_EHCI_HCD
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
select BOARD_LATE_INIT
@@ -148,11 +127,6 @@ config TARGET_TAO3530
select OMAP3_GPIO_5
select OMAP3_GPIO_6
-config TARGET_TWISTER
- bool "Twister"
- select OMAP3_GPIO_2
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
@@ -199,10 +173,8 @@ config SYS_SOC
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
@@ -210,13 +182,10 @@ source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
-source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
source "board/lg/sniper/Kconfig"
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index a74f16d348..aafeb355ef 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -16,11 +16,22 @@ config RCAR_GEN3
select PINCTRL
select PINCONF
select PINCTRL_PFC
+ select SUPPORT_SPL
imply CMD_FS_UUID
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
imply SUPPORT_EMMC_RPMB if MMC
+ imply SPL
+ imply SPL_BOARD_INIT
+ imply SPL_GZIP
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply SPL_TINY_MEMSET
+ imply SPL_YMODEM_SUPPORT
+ imply USE_TINY_PRINTF
config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 1f26adaca9..a3fdcc3bc0 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,3 +13,76 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+
+OBJCOPYFLAGS_u-boot-spl.srec := -O srec
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
+ $(OBJCOPYFLAGS_$(@F)) $< $@
+
+spl/u-boot-spl.srec: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
+ifneq ($(CONFIG_R8A77990)$(CONFIG_R8A77995),)
+#
+# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
+# The subsequent generate statements represent the following chunk of assembler
+# code, which copies the loaded data from 0xe6304030 to 0xe6318000. This is to
+# work around a limitation of the D3/E3 BootROM, which does not permit loading
+# to 0xe6318000 directly.
+#
+# mov x0, #0xe6000000
+# orr x0, x0, #0x00300000
+# orr x1, x0, #0x00004000
+# orr x1, x1, #0x00000030
+#
+# orr x2, x0, #0x00018000
+# mov x0, x2
+# mov x3, #0x7000
+#1: ldp x4, x5, [x1], #16
+#
+# stp x4, x5, [x2], #16
+# subs x3, x3, #16
+# b.ge 1b
+# br x0
+#
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -offset -0x13fd0 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
+ -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \
+ -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
+ -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \
+ -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \
+ -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \
+ -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \
+ -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \
+ -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \
+ -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \
+ -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \
+ -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \
+ -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \
+ -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \
+ -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \
+ -generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \
+ -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4
+else
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
+ -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
+ -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe6301264 0xe6301268 -l-e-constant $2 4
+endif
+
+spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
+ $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
+
+# if srec_cat is present build u-boot-spl.scif by default
+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
+ALL-$(has_srec_cat) += u-boot-spl.scif
+CLEAN_FILES += u-boot-spl.scif
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index c3ca8cdf3b..27d0b6a370 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index db1983dc31..49dadd4c3d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -70,6 +70,60 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
+
+void socfpga_pl310_clear(void)
+{
+ u32 mask = 0xff, ena = 0;
+
+ icache_enable();
+
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x0, &pl310->pl310_tag_latency_ctrl);
+ writel(0x10, &pl310->pl310_data_latency_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(&pl310->pl310_aux_ctrl,
+ L310_AUX_CTRL_DATA_PREFETCH_MASK |
+ L310_AUX_CTRL_INST_PREFETCH_MASK |
+ L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ ena = readl(&pl310->pl310_ctrl);
+ ena |= L2X0_CTRL_EN;
+
+ /*
+ * Invalidate the PL310 L2 cache. Keep the invalidation code
+ * entirely in L1 I-cache to avoid any bus traffic through
+ * the L2.
+ */
+ asm volatile(
+ ".align 5 \n"
+ " b 3f \n"
+ "1: str %1, [%4] \n"
+ " dsb \n"
+ " isb \n"
+ " str %0, [%2] \n"
+ " dsb \n"
+ " isb \n"
+ "2: ldr %0, [%2] \n"
+ " cmp %0, #0 \n"
+ " bne 2b \n"
+ " str %0, [%3] \n"
+ " dsb \n"
+ " isb \n"
+ " b 4f \n"
+ "3: b 1b \n"
+ "4: nop \n"
+ : "+r"(mask), "+r"(ena)
+ : "r"(&pl310->pl310_inv_way),
+ "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+ : "memory", "cc");
+
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b466307f98..b820cb0673 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -110,6 +110,7 @@ void board_init_f(ulong dummy)
socfpga_init_security_policies();
socfpga_sdram_remap_zero();
+ socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 1a60cdc897..87b76b47de 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <image.h>
@@ -25,8 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
-static void socfpga_pl310_clear(void)
-{
- u32 mask = 0xff, ena = 0;
-
- icache_enable();
-
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x111, &pl310->pl310_tag_latency_ctrl);
- writel(0x121, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
- L310_AUX_CTRL_DATA_PREFETCH_MASK |
- L310_AUX_CTRL_INST_PREFETCH_MASK |
- L310_SHARED_ATT_OVERRIDE_ENABLE);
-
- /* Enable the L2 cache */
- ena = readl(&pl310->pl310_ctrl);
- ena |= L2X0_CTRL_EN;
-
- /*
- * Invalidate the PL310 L2 cache. Keep the invalidation code
- * entirely in L1 I-cache to avoid any bus traffic through
- * the L2.
- */
- asm volatile(
- ".align 5 \n"
- " b 3f \n"
- "1: str %1, [%4] \n"
- " dsb \n"
- " isb \n"
- " str %0, [%2] \n"
- " dsb \n"
- " isb \n"
- "2: ldr %0, [%2] \n"
- " cmp %0, #0 \n"
- " bne 2b \n"
- " str %0, [%3] \n"
- " dsb \n"
- " isb \n"
- " b 4f \n"
- "3: b 1b \n"
- "4: nop \n"
- : "+r"(mask), "+r"(ena)
- : "r"(&pl310->pl310_inv_way),
- "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
- : "memory", "cc");
-
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 73aa382712..77f66c65c0 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -17,12 +17,20 @@ config SPL
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
select SPL_SYSCON
+ imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
+ imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
imply SPL_LIBDISK_SUPPORT
config SYS_SOC
default "stm32mp"
+config SYS_MALLOC_LEN
+ default 0x2000000
+
+config ENV_SIZE
+ default 0x1000
+
config TARGET_STM32MP1
bool "Support stm32mp1xx"
select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
@@ -33,6 +41,10 @@ config TARGET_STM32MP1
select STM32_RCC
select STM32_RESET
select SYS_ARCH_TIMER
+ imply BOOTCOUNT_LIMIT
+ imply BOOTSTAGE
+ imply CMD_BOOTCOUNT
+ imply CMD_BOOTSTAGE
imply SYSRESET_PSCI if STM32MP1_TRUSTED
imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
help
@@ -70,6 +82,18 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
Partition on the second MMC to load U-Boot from when the MMC is being
used in raw mode
+config BOOTSTAGE_STASH_ADDR
+ default 0xC3000000
+
+if BOOTCOUNT_LIMIT
+config SYS_BOOTCOUNT_SINGLEWORD
+ default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
+config SYS_BOOTCOUNT_ADDR
+ default 0x5C00A154
+endif
+
if DEBUG_UART
config DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 9ed8d8c56c..0166649685 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -7,9 +7,9 @@
#include <dm.h>
#include <misc.h>
#include <asm/io.h>
-#include <linux/iopoll.h>
#include <asm/arch/stm32mp1_smc.h>
#include <linux/arm-smccc.h>
+#include <linux/iopoll.h>
#define BSEC_OTP_MAX_VALUE 95
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
index 18575842ba..b8a17cfbdd 100644
--- a/arch/arm/mach-stm32mp/include/mach/ddr.h
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -6,6 +6,13 @@
#ifndef __MACH_STM32MP_DDR_H_
#define __MACH_STM32MP_DDR_H_
-int board_ddr_power_init(void);
+/* DDR power initializations */
+enum ddr_type {
+ STM32MP_DDR3,
+ STM32MP_LPDDR2,
+ STM32MP_LPDDR3,
+};
+
+int board_ddr_power_init(enum ddr_type ddr_type);
#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index c526c88e3e..6795352044 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -88,6 +88,7 @@ enum boot_device {
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index c2dff38c36..139bb09292 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -47,14 +47,14 @@ static u32 __secure stm32mp_get_gicd_base_address(void)
return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
}
-static void __secure stm32mp_smp_kick_all_cpus(void)
+static void __secure stm32mp_raise_sgi0(int cpu)
{
u32 gic_dist_addr;
gic_dist_addr = stm32mp_get_gicd_base_address();
- /* kick all CPUs (except this one) by writing to GICD_SGIR */
- writel(1U << 24, gic_dist_addr + GICD_SGIR);
+ /* ask cpu with SGI0 */
+ writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
}
void __secure psci_arch_cpu_entry(void)
@@ -62,6 +62,9 @@ void __secure psci_arch_cpu_entry(void)
u32 cpu = psci_get_cpu_id();
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+
+ /* reset magic in TAMP register */
+ writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
}
int __secure psci_features(u32 function_id, u32 psci_fid)
@@ -127,6 +130,16 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
return ARM_PSCI_RET_ALREADY_ON;
+ /* reset magic in TAMP register */
+ if (readl(TAMP_BACKUP_MAGIC_NUMBER))
+ writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
+ /*
+ * ROM code need a first SGI0 after core reset
+ * core is ready when magic is set to 0 in ROM code
+ */
+ while (readl(TAMP_BACKUP_MAGIC_NUMBER))
+ stm32mp_raise_sgi0(cpu);
+
/* store target PC and context id*/
psci_save(cpu, pc, context_id);
@@ -142,7 +155,8 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
TAMP_BACKUP_MAGIC_NUMBER);
- stm32mp_smp_kick_all_cpus();
+ /* Generate an IT to start the core */
+ stm32mp_raise_sgi0(cpu);
return ARM_PSCI_RET_SUCCESS;
}
generated by cgit (git 2.34.1) at 2025-01-12 07:13:29 +0000