diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/exynos4412-odroid.dts | 3 | ||||
| -rw-r--r-- | arch/arm/dts/exynos5422-odroidxu3.dts | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/cpu.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mq.c | 97 |
4 files changed, 6 insertions, 97 deletions
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index cc8e0dd041..ce08e8dc1e 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -17,7 +17,7 @@ serial0 = "/serial@13800000"; console = "/serial@13810000"; mmc0 = &mshc_0; - mmc1 = &sdhci2; + mmc2 = &sdhci2; }; serial@13810000 { @@ -236,6 +236,7 @@ &sdhci2 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; + cd-inverted; cd-gpios = <&gpk2 2 0>; status = "okay"; }; diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 6df6be9181..256df6d6c2 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -10,7 +10,7 @@ #include "exynos54xx.dtsi" / { - model = "Odroid XU3 based on EXYNOS5422"; + model = "Odroid XU3/XU4/HC1/HC2 based on Exynos5422"; compatible = "samsung,odroidxu3", "samsung,exynos5"; aliases { diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index 766edeeb29..fb5fdaf3ba 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -17,6 +17,7 @@ #define EXYNOS4_GPIO_PART3_BASE 0x03860000 #define EXYNOS4_PRO_ID 0x10000000 +#define EXYNOS4_OP_MODE 0x10000008 #define EXYNOS4_SYSREG_BASE 0x10010000 #define EXYNOS4_POWER_BASE 0x10020000 #define EXYNOS4_SWRESET 0x10020400 diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 878f2be166..aad9cf13ef 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -374,28 +374,6 @@ void init_wdog_clk(void) clock_enable(CCGR_WDOG3, 1); } -void init_usb_clk(void) -{ - if (!is_usb_boot()) { - clock_enable(CCGR_USB_CTRL1, 0); - clock_enable(CCGR_USB_CTRL2, 0); - clock_enable(CCGR_USB_PHY1, 0); - clock_enable(CCGR_USB_PHY2, 0); - /* 500MHz */ - clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - /* 100MHz */ - clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - /* 100MHz */ - clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - clock_enable(CCGR_USB_CTRL1, 1); - clock_enable(CCGR_USB_CTRL2, 1); - clock_enable(CCGR_USB_PHY1, 1); - clock_enable(CCGR_USB_PHY2, 1); - } -} void init_nand_clk(void) { @@ -658,7 +636,7 @@ void dram_pll_init(ulong pll_val) ; } -int frac_pll_init(u32 pll, enum frac_pll_out_val val) +static int frac_pll_init(u32 pll, enum frac_pll_out_val val) { void __iomem *pll_cfg0, __iomem *pll_cfg1; u32 val_cfg0, val_cfg1; @@ -699,77 +677,6 @@ int frac_pll_init(u32 pll, enum frac_pll_out_val val) return 0; } -int sscg_pll_init(u32 pll) -{ - void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2; - u32 val_cfg0, val_cfg1, val_cfg2, val; - u32 bypass1_mask = 0x20, bypass2_mask = 0x10; - int ret; - - switch (pll) { - case ANATOP_SYSTEM_PLL1: - pll_cfg0 = &ana_pll->sys_pll1_cfg0; - pll_cfg1 = &ana_pll->sys_pll1_cfg1; - pll_cfg2 = &ana_pll->sys_pll1_cfg2; - /* 800MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | - SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | - SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | - SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | - SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - case ANATOP_SYSTEM_PLL2: - pll_cfg0 = &ana_pll->sys_pll2_cfg0; - pll_cfg1 = &ana_pll->sys_pll2_cfg1; - pll_cfg2 = &ana_pll->sys_pll2_cfg2; - /* 1000MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | - SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | - SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | - SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | - SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - case ANATOP_SYSTEM_PLL3: - pll_cfg0 = &ana_pll->sys_pll3_cfg0; - pll_cfg1 = &ana_pll->sys_pll3_cfg1; - pll_cfg2 = &ana_pll->sys_pll3_cfg2; - /* 800MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - default: - return -EINVAL; - } - - /*bypass*/ - setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask); - /* set value */ - writel(val_cfg2, pll_cfg2); - writel(val_cfg1, pll_cfg1); - /*unbypass1 and wait 70us */ - writel(val_cfg0 | bypass2_mask, pll_cfg1); - - __udelay(70); - - /* unbypass2 and wait lock */ - writel(val_cfg0, pll_cfg1); - ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1); - if (ret) - printf("%s timeout\n", __func__); - - return ret; -} int clock_init(void) { @@ -833,7 +740,7 @@ int clock_init(void) * Dump some clockes. */ #ifndef CONFIG_SPL_BUILD -int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, +static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; |